upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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82 lines
2.6 KiB
82 lines
2.6 KiB
15 years ago
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/*
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* Copyright 2010 Freescale Semiconductor, Inc.
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include <config.h>
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#include <common.h>
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#include <asm/io.h>
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#include <asm/immap_85xx.h>
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#include <asm/fsl_serdes.h>
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#define SRDS1_MAX_LANES 8
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static u32 serdes1_prtcl_map;
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static u8 serdes1_cfg_tbl[][SRDS1_MAX_LANES] = {
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[0x2] = {PCIE1, PCIE1, PCIE1, PCIE1, NONE, NONE, NONE, NONE},
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[0x3] = {PCIE1, PCIE1, PCIE1, PCIE1, PCIE2, PCIE2, PCIE2, PCIE2},
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[0x6] = {NONE, NONE, NONE, NONE, SRIO1, SRIO1, SRIO1, SRIO1},
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[0x7] = {PCIE1, PCIE1, PCIE1, PCIE1, PCIE2, PCIE2, PCIE3, PCIE3},
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[0xb] = {PCIE1, PCIE1, PCIE1, PCIE1, SRIO1, SRIO1, SRIO1, SRIO1},
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[0xc] = {PCIE1, PCIE1, PCIE1, PCIE1, SRIO1, SRIO1, SRIO1, SRIO1},
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[0xd] = {NONE, NONE, NONE, NONE, SRIO1, SRIO1, SRIO1, SRIO1},
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[0xe] = {NONE, NONE, NONE, NONE, SRIO1, SRIO1, SRIO1, SRIO1},
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[0xf] = {PCIE1, PCIE1, PCIE1, PCIE1, PCIE1, PCIE1, PCIE1, PCIE1},
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};
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int is_serdes_configured(enum srds_prtcl prtcl)
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{
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return (1 << prtcl) & serdes1_prtcl_map;
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}
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void fsl_serdes_init(void)
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{
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ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
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u32 pordevsr = in_be32(&gur->pordevsr);
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u32 srds_cfg = (pordevsr & MPC85xx_PORDEVSR_IO_SEL) >>
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MPC85xx_PORDEVSR_IO_SEL_SHIFT;
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int lane;
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debug("PORDEVSR[IO_SEL_SRDS] = %x\n", srds_cfg);
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if (srds_cfg > ARRAY_SIZE(serdes1_cfg_tbl)) {
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printf("Invalid PORDEVSR[IO_SEL_SRDS] = %d\n", srds_cfg);
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return;
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}
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for (lane = 0; lane < SRDS1_MAX_LANES; lane++) {
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enum srds_prtcl lane_prtcl = serdes1_cfg_tbl[srds_cfg][lane];
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serdes1_prtcl_map |= (1 << lane_prtcl);
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}
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if (!(pordevsr & MPC85xx_PORDEVSR_SGMII1_DIS))
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serdes1_prtcl_map |= (1 << SGMII_TSEC1);
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if (!(pordevsr & MPC85xx_PORDEVSR_SGMII2_DIS))
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serdes1_prtcl_map |= (1 << SGMII_TSEC2);
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if (!(pordevsr & MPC85xx_PORDEVSR_SGMII3_DIS))
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serdes1_prtcl_map |= (1 << SGMII_TSEC3);
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if (!(pordevsr & MPC85xx_PORDEVSR_SGMII4_DIS))
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serdes1_prtcl_map |= (1 << SGMII_TSEC4);
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}
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