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/*
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* include/asm-nds32/macro.h
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*
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* Copyright (C) 2009 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
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* Copyright (C) 2011 Andes Technology Corporation
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* Macpaul Lin, Andes Technology Corporation <macpaul@andestech.com>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#ifndef __ASM_NDS_MACRO_H
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#define __ASM_NDS_MACRO_H
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#ifdef __ASSEMBLY__
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/*
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* These macros provide a convenient way to write 8, 16 and 32 bit data
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* to an "immediate address (address used by periphal)" only.
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* Registers r4 and r5 are used, any data in these registers are
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* overwritten by the macros.
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* The macros are valid for any NDS32 architecture, they do not implement
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* any memory barriers so caution is recommended when using these when the
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* caches are enabled or on a multi-core system.
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*/
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.macro write32, addr, data
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li $r4, addr
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li $r5, data
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swi $r5, [$r4]
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.endm
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.macro write16, addr, data
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li $r4, addr
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li $r5, data
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shi $r5, [$r4]
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.endm
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.macro write8, addr, data
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li $r4, addr
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li $r5, data
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sbi $r5, [$r4]
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.endm
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/*
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* This macro read a value from a register, then do OR operation
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* (set bit fields) to the value, and then store it back to the register.
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* Note: Instruction 'ori' supports immediate value up to 15 bits.
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*/
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.macro setbf32, addr, data
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li $r4, addr
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lwi $r5, [$r4]
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li $r6, data
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or $r5, $r5, $r6
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swi $r5, [$r4]
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.endm
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.macro setbf15, addr, data
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li $r4, addr
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lwi $r5, [$r4]
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ori $r5, $r5, data
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swi $r5, [$r4]
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.endm
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/*
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* This macro generates a loop that can be used for delays in the code.
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* Register r4 is used, any data in this register is overwritten by the
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* macro.
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* The macro is valid for any NDS32 architeture. The actual time spent in the
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* loop will vary from CPU to CPU though.
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*/
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.macro wait_timer, time
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li $r4, time
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1:
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nop
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addi $r4, $r4, -1
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bnez $r4, 1b
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.endm
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#endif /* __ASSEMBLY__ */
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#endif /* __ASM_ARM_MACRO_H */
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