upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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334 lines
13 KiB
334 lines
13 KiB
20 years ago
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/*
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* (C) Copyright 2001-2005
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* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include <common.h>
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#include <ioports.h>
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#include <mpc8260.h>
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#include "cpu87.h"
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#include <pci.h>
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/*
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* I/O Port configuration table
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*
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* if conf is 1, then that port pin will be configured at boot time
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* according to the five values podr/pdir/ppar/psor/pdat for that entry
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*/
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const iop_conf_t iop_conf_tab[4][32] = {
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/* Port A configuration */
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{ /* conf ppar psor pdir podr pdat */
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/* PA31 */ { 1, 1, 1, 0, 0, 0 }, /* FCC1 MII COL */
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/* PA30 */ { 1, 1, 1, 0, 0, 0 }, /* FCC1 MII CRS */
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/* PA29 */ { 1, 1, 1, 1, 0, 0 }, /* FCC1 MII TX_ER */
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/* PA28 */ { 1, 1, 1, 1, 0, 0 }, /* FCC1 MII TX_EN */
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/* PA27 */ { 1, 1, 1, 0, 0, 0 }, /* FCC1 MII RX_DV */
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/* PA26 */ { 1, 1, 1, 0, 0, 0 }, /* FCC1 MII RX_ER */
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/* PA25 */ { 1, 0, 0, 1, 0, 0 }, /* FCC2 MII MDIO */
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/* PA24 */ { 1, 0, 0, 1, 0, 0 }, /* FCC2 MII MDC */
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/* PA23 */ { 1, 0, 0, 1, 0, 0 }, /* FCC1 MII MDIO */
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/* PA22 */ { 1, 0, 0, 1, 0, 0 }, /* FCC1 MII MDC */
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/* PA21 */ { 1, 1, 0, 1, 0, 0 }, /* FCC1 MII TxD[3] */
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/* PA20 */ { 1, 1, 0, 1, 0, 0 }, /* FCC1 MII TxD[2] */
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/* PA19 */ { 1, 1, 0, 1, 0, 0 }, /* FCC1 MII TxD[1] */
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/* PA18 */ { 1, 1, 0, 1, 0, 0 }, /* FCC1 MII TxD[0] */
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/* PA17 */ { 1, 1, 0, 0, 0, 0 }, /* FCC1 MII RxD[0] */
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/* PA16 */ { 1, 1, 0, 0, 0, 0 }, /* FCC1 MII RxD[1] */
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/* PA15 */ { 1, 1, 0, 0, 0, 0 }, /* FCC1 MII RxD[2] */
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/* PA14 */ { 1, 1, 0, 0, 0, 0 }, /* FCC1 MII RxD[3] */
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/* PA13 */ { 1, 0, 0, 1, 0, 0 }, /* FCC2 MII TXSL1 */
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/* PA12 */ { 1, 0, 0, 1, 0, 1 }, /* FCC2 MII TXSL0 */
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/* PA11 */ { 1, 0, 0, 1, 0, 0 }, /* FCC1 MII TXSL1 */
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/* PA10 */ { 1, 0, 0, 1, 0, 1 }, /* FCC1 MII TXSL0 */
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/* PA9 */ { 0, 1, 0, 1, 0, 0 }, /* SMC2 TXD */
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/* PA8 */ { 0, 1, 0, 0, 0, 0 }, /* SMC2 RXD */
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/* PA7 */ { 0, 0, 0, 0, 0, 0 }, /* PA7 */
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/* PA6 */ { 1, 0, 0, 1, 0, 1 }, /* FCC2 MII PAUSE */
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/* PA5 */ { 1, 0, 0, 1, 0, 1 }, /* FCC1 MII PAUSE */
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/* PA4 */ { 1, 0, 0, 1, 0, 0 }, /* FCC2 MII PWRDN */
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/* PA3 */ { 1, 0, 0, 1, 0, 0 }, /* FCC1 MII PWRDN */
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/* PA2 */ { 0, 0, 0, 0, 0, 0 }, /* PA2 */
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/* PA1 */ { 1, 0, 0, 0, 0, 0 }, /* FCC2 MII MDINT */
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/* PA0 */ { 1, 0, 0, 1, 0, 0 } /* FCC1 MII MDINT */
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},
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/* Port B configuration */
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{ /* conf ppar psor pdir podr pdat */
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/* PB31 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TX_ER */
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/* PB30 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_DV */
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/* PB29 */ { 1, 1, 1, 1, 0, 0 }, /* FCC2 MII TX_EN */
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/* PB28 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_ER */
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/* PB27 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII COL */
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/* PB26 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII CRS */
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/* PB25 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[3] */
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/* PB24 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[2] */
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/* PB23 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[1] */
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/* PB22 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[0] */
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/* PB21 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[0] */
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/* PB20 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[1] */
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/* PB19 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[2] */
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/* PB18 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[3] */
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/* PB17 */ { 0, 0, 0, 0, 0, 0 }, /* PB17 */
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/* PB16 */ { 0, 0, 0, 0, 0, 0 }, /* PB16 */
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/* PB15 */ { 0, 0, 0, 0, 0, 0 }, /* PB15 */
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/* PB14 */ { 0, 0, 0, 0, 0, 0 }, /* PB14 */
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/* PB13 */ { 0, 0, 0, 0, 0, 0 }, /* PB13 */
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/* PB12 */ { 0, 0, 0, 0, 0, 0 }, /* PB12 */
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/* PB11 */ { 0, 0, 0, 0, 0, 0 }, /* PB11 */
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/* PB10 */ { 0, 0, 0, 0, 0, 0 }, /* PB10 */
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/* PB9 */ { 0, 0, 0, 0, 0, 0 }, /* PB9 */
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/* PB8 */ { 0, 0, 0, 0, 0, 0 }, /* PB8 */
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/* PB7 */ { 0, 0, 0, 0, 0, 0 }, /* PB7 */
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/* PB6 */ { 0, 0, 0, 0, 0, 0 }, /* PB6 */
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/* PB5 */ { 0, 0, 0, 0, 0, 0 }, /* PB5 */
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/* PB4 */ { 0, 0, 0, 0, 0, 0 }, /* PB4 */
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/* PB3 */ { 0, 0, 0, 0, 0, 0 }, /* PB3 */
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/* PB2 */ { 0, 0, 0, 0, 0, 0 }, /* PB2 */
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/* PB1 */ { 0, 0, 0, 0, 0, 0 }, /* PB1 */
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/* PB0 */ { 0, 0, 0, 0, 0, 0 } /* PB0 */
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},
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/* Port C */
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{ /* conf ppar psor pdir podr pdat */
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/* PC31 */ { 0, 0, 0, 0, 0, 0 }, /* PC31 */
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/* PC30 */ { 0, 0, 0, 0, 0, 0 }, /* PC30 */
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/* PC29 */ { 1, 0, 0, 0, 0, 0 }, /* SCC1 CTS */
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/* PC28 */ { 1, 0, 0, 0, 0, 0 }, /* SCC2 CTS */
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/* PC27 */ { 0, 0, 0, 0, 0, 0 }, /* PC27 */
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/* PC26 */ { 0, 0, 0, 0, 0, 0 }, /* PC26 */
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/* PC25 */ { 0, 0, 0, 0, 0, 0 }, /* PC25 */
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/* PC24 */ { 0, 0, 0, 0, 0, 0 }, /* PC24 */
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/* PC23 */ { 0, 0, 0, 0, 0, 0 }, /* FDC37C78 DACFD */
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/* PC22 */ { 0, 0, 0, 0, 0, 0 }, /* FDC37C78 DNFD */
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/* PC21 */ { 1, 1, 0, 0, 0, 0 }, /* FCC1 MII RX_CLK */
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/* PC20 */ { 1, 1, 0, 0, 0, 0 }, /* FCC1 MII TX_CLK */
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/* PC19 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_CLK */
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/* PC18 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII TX_CLK */
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/* PC17 */ { 0, 0, 0, 0, 0, 0 }, /* PC17 */
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/* PC16 */ { 0, 0, 0, 0, 0, 0 }, /* PC16 */
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/* PC15 */ { 0, 0, 0, 0, 0, 0 }, /* PC15 */
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/* PC14 */ { 0, 0, 0, 0, 0, 0 }, /* PC14 */
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/* PC13 */ { 0, 0, 0, 0, 0, 0 }, /* PC13 */
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/* PC12 */ { 0, 0, 0, 0, 0, 0 }, /* PC12 */
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/* PC11 */ { 0, 0, 0, 0, 0, 0 }, /* PC11 */
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/* PC10 */ { 0, 0, 0, 0, 0, 0 }, /* PC10 */
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/* PC9 */ { 0, 0, 0, 0, 0, 0 }, /* FC9 */
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/* PC8 */ { 0, 0, 0, 0, 0, 0 }, /* PC8 */
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/* PC7 */ { 0, 0, 0, 0, 0, 0 }, /* PC7 */
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/* PC6 */ { 0, 0, 0, 0, 0, 0 }, /* PC6 */
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/* PC5 */ { 0, 0, 0, 0, 0, 0 }, /* PC5 */
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/* PC4 */ { 0, 0, 0, 0, 0, 0 }, /* PC4 */
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/* PC3 */ { 0, 0, 0, 0, 0, 0 }, /* PC3 */
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/* PC2 */ { 0, 0, 0, 0, 0, 0 }, /* PC2 */
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/* PC1 */ { 0, 0, 0, 0, 0, 0 }, /* PC1 */
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/* PC0 */ { 0, 0, 0, 0, 0, 0 }, /* FDC37C78 DRQFD */
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},
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/* Port D */
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{ /* conf ppar psor pdir podr pdat */
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/* PD31 */ { 1, 1, 0, 0, 0, 0 }, /* SCC1 RXD */
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/* PD30 */ { 1, 1, 1, 1, 0, 0 }, /* SCC1 TXD */
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/* PD29 */ { 1, 0, 0, 1, 0, 0 }, /* SCC1 RTS */
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/* PD28 */ { 1, 1, 0, 0, 0, 0 }, /* SCC2 RXD */
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/* PD27 */ { 1, 1, 0, 1, 0, 0 }, /* SCC2 TXD */
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/* PD26 */ { 1, 0, 0, 1, 0, 0 }, /* SCC2 RTS */
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/* PD25 */ { 0, 0, 0, 0, 0, 0 }, /* PD25 */
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/* PD24 */ { 0, 0, 0, 0, 0, 0 }, /* PD24 */
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/* PD23 */ { 0, 0, 0, 0, 0, 0 }, /* PD23 */
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/* PD22 */ { 0, 0, 0, 0, 0, 0 }, /* PD22 */
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/* PD21 */ { 0, 0, 0, 0, 0, 0 }, /* PD21 */
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/* PD20 */ { 0, 0, 0, 0, 0, 0 }, /* PD20 */
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/* PD19 */ { 0, 0, 0, 0, 0, 0 }, /* PD19 */
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/* PD18 */ { 0, 0, 0, 0, 0, 0 }, /* PD18 */
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/* PD17 */ { 0, 0, 0, 0, 0, 0 }, /* PD17 */
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/* PD16 */ { 0, 0, 0, 0, 0, 0 }, /* PD16 */
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#if defined(CONFIG_SOFT_I2C)
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/* PD15 */ { 1, 0, 0, 1, 1, 1 }, /* I2C SDA */
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/* PD14 */ { 1, 0, 0, 1, 1, 1 }, /* I2C SCL */
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#else
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#if defined(CONFIG_HARD_I2C)
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/* PD15 */ { 1, 1, 1, 0, 1, 0 }, /* I2C SDA */
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/* PD14 */ { 1, 1, 1, 0, 1, 0 }, /* I2C SCL */
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#else /* normal I/O port pins */
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/* PD15 */ { 1, 1, 1, 0, 1, 0 }, /* I2C SDA */
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/* PD14 */ { 1, 1, 1, 0, 1, 0 }, /* I2C SCL */
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#endif
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#endif
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/* PD13 */ { 0, 0, 0, 0, 0, 0 }, /* PD13 */
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/* PD12 */ { 0, 0, 0, 0, 0, 0 }, /* PD12 */
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/* PD11 */ { 0, 0, 0, 0, 0, 0 }, /* PD11 */
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/* PD10 */ { 0, 0, 0, 0, 0, 0 }, /* PD10 */
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/* PD9 */ { 1, 1, 0, 1, 0, 0 }, /* SMC1 TXD */
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/* PD8 */ { 1, 1, 0, 0, 0, 0 }, /* SMC1 RXD */
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/* PD7 */ { 0, 0, 0, 0, 0, 0 }, /* PD7 */
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/* PD6 */ { 0, 0, 0, 0, 0, 0 }, /* PD6 */
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/* PD5 */ { 0, 0, 0, 0, 0, 0 }, /* PD5 */
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/* PD4 */ { 0, 0, 0, 0, 0, 0 }, /* PD4 */
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/* PD3 */ { 0, 0, 0, 0, 0, 0 }, /* PD3 */
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/* PD2 */ { 0, 0, 0, 0, 0, 0 }, /* PD2 */
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/* PD1 */ { 0, 0, 0, 0, 0, 0 }, /* PD1 */
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/* PD0 */ { 0, 0, 0, 0, 0, 0 } /* PD0 */
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}
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};
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/* ------------------------------------------------------------------------- */
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/* Check Board Identity:
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*/
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int checkboard (void)
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{
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printf ("Board: CPU87 (Rev %02x)\n", CPU86_REV);
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return 0;
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}
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/* ------------------------------------------------------------------------- */
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/* Try SDRAM initialization with P/LSDMR=sdmr and ORx=orx
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*
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* This routine performs standard 8260 initialization sequence
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* and calculates the available memory size. It may be called
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* several times to try different SDRAM configurations on both
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* 60x and local buses.
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*/
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static long int try_init (volatile memctl8260_t * memctl, ulong sdmr,
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ulong orx, volatile uchar * base)
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{
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volatile uchar c = 0xff;
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volatile uint *sdmr_ptr;
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volatile uint *orx_ptr;
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ulong maxsize, size;
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int i;
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/* We must be able to test a location outsize the maximum legal size
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* to find out THAT we are outside; but this address still has to be
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* mapped by the controller. That means, that the initial mapping has
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* to be (at least) twice as large as the maximum expected size.
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*/
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maxsize = (1 + (~orx | 0x7fff)) / 2;
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/* Since CFG_SDRAM_BASE is always 0 (??), we assume that
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* we are configuring CS1 if base != 0
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*/
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sdmr_ptr = &memctl->memc_psdmr;
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orx_ptr = &memctl->memc_or2;
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*orx_ptr = orx;
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/*
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* Quote from 8260 UM (10.4.2 SDRAM Power-On Initialization, 10-35):
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*
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* "At system reset, initialization software must set up the
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* programmable parameters in the memory controller banks registers
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* (ORx, BRx, P/LSDMR). After all memory parameters are configured,
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* system software should execute the following initialization sequence
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* for each SDRAM device.
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*
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* 1. Issue a PRECHARGE-ALL-BANKS command
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* 2. Issue eight CBR REFRESH commands
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* 3. Issue a MODE-SET command to initialize the mode register
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*
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* The initial commands are executed by setting P/LSDMR[OP] and
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* accessing the SDRAM with a single-byte transaction."
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*
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* The appropriate BRx/ORx registers have already been set when we
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* get here. The SDRAM can be accessed at the address CFG_SDRAM_BASE.
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*/
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*sdmr_ptr = sdmr | PSDMR_OP_PREA;
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*base = c;
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*sdmr_ptr = sdmr | PSDMR_OP_CBRR;
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for (i = 0; i < 8; i++)
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*base = c;
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*sdmr_ptr = sdmr | PSDMR_OP_MRW;
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*(base + CFG_MRS_OFFS) = c; /* setting MR on address lines */
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*sdmr_ptr = sdmr | PSDMR_OP_NORM | PSDMR_RFEN;
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*base = c;
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size = get_ram_size((long *)base, maxsize);
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*orx_ptr = orx | ~(size - 1);
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return (size);
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}
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long int initdram (int board_type)
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{
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volatile immap_t *immap = (immap_t *) CFG_IMMR;
|
||
|
|
volatile memctl8260_t *memctl = &immap->im_memctl;
|
||
|
|
|
||
|
|
#ifndef CFG_RAMBOOT
|
||
|
|
ulong size8, size9;
|
||
|
|
#endif
|
||
|
|
long psize;
|
||
|
|
|
||
|
|
psize = 32 * 1024 * 1024;
|
||
|
|
|
||
|
|
memctl->memc_mptpr = CFG_MPTPR;
|
||
|
|
memctl->memc_psrt = CFG_PSRT;
|
||
|
|
|
||
|
|
#ifndef CFG_RAMBOOT
|
||
|
|
/* 60x SDRAM setup:
|
||
|
|
*/
|
||
|
|
size8 = try_init (memctl, CFG_PSDMR_8COL, CFG_OR2_8COL,
|
||
|
|
(uchar *) CFG_SDRAM_BASE);
|
||
|
|
size9 = try_init (memctl, CFG_PSDMR_9COL, CFG_OR2_9COL,
|
||
|
|
(uchar *) CFG_SDRAM_BASE);
|
||
|
|
|
||
|
|
if (size8 < size9) {
|
||
|
|
psize = size9;
|
||
|
|
printf ("(60x:9COL) ");
|
||
|
|
} else {
|
||
|
|
psize = try_init (memctl, CFG_PSDMR_8COL, CFG_OR2_8COL,
|
||
|
|
(uchar *) CFG_SDRAM_BASE);
|
||
|
|
printf ("(60x:8COL) ");
|
||
|
|
}
|
||
|
|
|
||
|
|
#endif /* CFG_RAMBOOT */
|
||
|
|
|
||
|
|
icache_enable ();
|
||
|
|
|
||
|
|
return (psize);
|
||
|
|
}
|
||
|
|
|
||
|
|
#if (CONFIG_COMMANDS & CFG_CMD_DOC)
|
||
|
|
extern void doc_probe (ulong physadr);
|
||
|
|
void doc_init (void)
|
||
|
|
{
|
||
|
|
doc_probe (CFG_DOC_BASE);
|
||
|
|
}
|
||
|
|
#endif
|
||
|
|
|
||
|
|
#ifdef CONFIG_PCI
|
||
|
|
struct pci_controller hose;
|
||
|
|
|
||
|
|
extern void pci_mpc8250_init(struct pci_controller *);
|
||
|
|
|
||
|
|
void pci_init_board(void)
|
||
|
|
{
|
||
|
|
pci_mpc8250_init(&hose);
|
||
|
|
}
|
||
|
|
#endif
|