upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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78 lines
1.9 KiB
78 lines
1.9 KiB
15 years ago
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/*
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* Register definitions for the AMBA CLCD logic cell.
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*
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* derived from David A Rusling, although rearranged as a C structure
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* linux/include/asm-arm/hardware/amba_clcd.h -- Integrator LCD panel.
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*
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* Copyright (C) 2001 ARM Limited
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*
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* This file is subject to the terms and conditions of the GNU General Public
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* License. See the file COPYING in the main directory of this archive
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* for more details.
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*/
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/*
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* CLCD Controller Internal Register addresses
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*/
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struct clcd_registers {
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u32 tim0; /* 0x00 */
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u32 tim1;
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u32 tim2;
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u32 tim3;
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u32 ubas; /* 0x10 */
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u32 lbas;
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#if !defined(CONFIG_ARCH_VERSATILE) && !defined(CONFIG_ARCH_REALVIEW)
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u32 ienb;
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u32 cntl;
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#else /* Someone rearranged these two registers on the Versatile */
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u32 cntl;
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u32 ienb;
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#endif
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u32 stat; /* 0x20 */
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u32 intr;
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u32 ucur;
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u32 lcur;
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u32 unused[0x74]; /* 0x030..0x1ff */
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u32 palette[0x80]; /* 0x200..0x3ff */
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};
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/* Bit definition for TIM2 */
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#define TIM2_CLKSEL (1 << 5)
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#define TIM2_IVS (1 << 11)
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#define TIM2_IHS (1 << 12)
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#define TIM2_IPC (1 << 13)
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#define TIM2_IOE (1 << 14)
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#define TIM2_BCD (1 << 26)
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/* Bit definitions for control register */
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#define CNTL_LCDEN (1 << 0)
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#define CNTL_LCDBPP1 (0 << 1)
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#define CNTL_LCDBPP2 (1 << 1)
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#define CNTL_LCDBPP4 (2 << 1)
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#define CNTL_LCDBPP8 (3 << 1)
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#define CNTL_LCDBPP16 (4 << 1)
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#define CNTL_LCDBPP16_565 (6 << 1)
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#define CNTL_LCDBPP24 (5 << 1)
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#define CNTL_LCDBW (1 << 4)
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#define CNTL_LCDTFT (1 << 5)
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#define CNTL_LCDMONO8 (1 << 6)
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#define CNTL_LCDDUAL (1 << 7)
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#define CNTL_BGR (1 << 8)
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#define CNTL_BEBO (1 << 9)
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#define CNTL_BEPO (1 << 10)
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#define CNTL_LCDPWR (1 << 11)
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#define CNTL_LCDVCOMP(x) ((x) << 12)
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#define CNTL_LDMAFIFOTIME (1 << 15)
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#define CNTL_WATERMARK (1 << 16)
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/* u-boot specific: information passed by the board file */
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struct clcd_config {
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struct clcd_registers *address;
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u32 tim0;
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u32 tim1;
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u32 tim2;
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u32 tim3;
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u32 cntl;
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unsigned long pixclock;
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};
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