upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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97 lines
4.4 KiB
97 lines
4.4 KiB
17 years ago
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/*
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* PLL Masks
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*/
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#ifndef __BFIN_PERIPHERAL_PLL__
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#define __BFIN_PERIPHERAL_PLL__
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/* PLL_CTL Masks */
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#define DF 0x0001 /* 0: PLL = CLKIN, 1: PLL = CLKIN/2 */
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#define PLL_OFF 0x0002 /* PLL Not Powered */
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#define STOPCK 0x0008 /* Core Clock Off */
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#define PDWN 0x0020 /* Enter Deep Sleep Mode */
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#define IN_DELAY 0x0040 /* Add 200ps Delay To EBIU Input Latches */
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#define OUT_DELAY 0x0080 /* Add 200ps Delay To EBIU Output Signals */
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#define BYPASS 0x0100 /* Bypass the PLL */
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#define MSEL 0x7E00 /* Multiplier Select For CCLK/VCO Factors */
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#define SPORT_HYST 0x8000 /* Enable Additional Hysteresis on SPORT Input Pins */
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/* PLL_DIV Masks */
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#define SSEL 0x000F /* System Select */
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#define CSEL 0x0030 /* Core Select */
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#define CSEL_DIV1 0x0000 /* CCLK = VCO / 1 */
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#define CSEL_DIV2 0x0010 /* CCLK = VCO / 2 */
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#define CSEL_DIV4 0x0020 /* CCLK = VCO / 4 */
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#define CSEL_DIV8 0x0030 /* CCLK = VCO / 8 */
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#define CCLK_DIV1 CSEL_DIV1
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#define CCLK_DIV2 CSEL_DIV2
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#define CCLK_DIV4 CSEL_DIV4
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#define CCLK_DIV8 CSEL_DIV8
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/* PLL_STAT Masks */
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#define ACTIVE_PLLENABLED 0x0001 /* Processor In Active Mode With PLL Enabled */
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#define FULL_ON 0x0002 /* Processor In Full On Mode */
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#define ACTIVE_PLLDISABLED 0x0004 /* Processor In Active Mode With PLL Disabled */
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#define DEEP_SLEEP 0x0008 /* Processor In Deep Sleep Mode */
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#define SLEEP 0x0010 /* Processor In Sleep Mode */
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#define PLL_LOCKED 0x0020 /* PLL_LOCKCNT Has Been Reached */
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#define CORE_IDLE 0x0040 /* Processor In IDLE Mode */
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#define VSTAT 0x0080 /* Voltage Regulator Has Reached Programmed Voltage */
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/* VR_CTL Masks */
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#ifdef __ADSPBF52x__
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#define FREQ_MASK 0x3000 /* Switching Oscillator Frequency For Regulator */
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#define FREQ_HIBERNATE 0x0000 /* Powerdown/Bypass On-Board Regulation */
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#define FREQ_1000 0x3000 /* Switching Frequency Is 1 MHz */
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#else
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#define FREQ_MASK 0x0003 /* Switching Oscillator Frequency For Regulator */
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#define FREQ_HIBERNATE 0x0000 /* Powerdown/Bypass On-Board Regulation */
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#define FREQ_333 0x0001 /* Switching Frequency Is 333 kHz */
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#define FREQ_667 0x0002 /* Switching Frequency Is 667 kHz */
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#define FREQ_1000 0x0003 /* Switching Frequency Is 1 MHz */
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#endif
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#define GAIN_MASK 0x000C /* Voltage Level Gain */
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#define GAIN_5 0x0000 /* GAIN = 5 */
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#define GAIN_10 0x0004 /* GAIN = 10 */
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#define GAIN_20 0x0008 /* GAIN = 20 */
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#define GAIN_50 0x000C /* GAIN = 50 */
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#ifdef __ADSPBF52x__
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#define VLEV_MASK 0x00F0 /* Internal Voltage Level */
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#define VLEV_085 0x0040 /* VLEV = 0.85 V (-5% - +10% Accuracy) */
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#define VLEV_090 0x0050 /* VLEV = 0.90 V (-5% - +10% Accuracy) */
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#define VLEV_095 0x0060 /* VLEV = 0.95 V (-5% - +10% Accuracy) */
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#define VLEV_100 0x0070 /* VLEV = 1.00 V (-5% - +10% Accuracy) */
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#define VLEV_105 0x0080 /* VLEV = 1.05 V (-5% - +10% Accuracy) */
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#define VLEV_110 0x0090 /* VLEV = 1.10 V (-5% - +10% Accuracy) */
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#define VLEV_115 0x00A0 /* VLEV = 1.15 V (-5% - +10% Accuracy) */
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#define VLEV_120 0x00B0 /* VLEV = 1.20 V (-5% - +10% Accuracy) */
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#else
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#define VLEV_MASK 0x00F0 /* Internal Voltage Level */
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#define VLEV_085 0x0060 /* VLEV = 0.85 V (-5% - +10% Accuracy) */
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#define VLEV_090 0x0070 /* VLEV = 0.90 V (-5% - +10% Accuracy) */
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#define VLEV_095 0x0080 /* VLEV = 0.95 V (-5% - +10% Accuracy) */
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#define VLEV_100 0x0090 /* VLEV = 1.00 V (-5% - +10% Accuracy) */
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#define VLEV_105 0x00A0 /* VLEV = 1.05 V (-5% - +10% Accuracy) */
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#define VLEV_110 0x00B0 /* VLEV = 1.10 V (-5% - +10% Accuracy) */
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#define VLEV_115 0x00C0 /* VLEV = 1.15 V (-5% - +10% Accuracy) */
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#define VLEV_120 0x00D0 /* VLEV = 1.20 V (-5% - +10% Accuracy) */
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#define VLEV_125 0x00E0 /* VLEV = 1.25 V (-5% - +10% Accuracy) */
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#define VLEV_130 0x00F0 /* VLEV = 1.30 V (-5% - +10% Accuracy) */
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#endif
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#define WAKE 0x0100 /* Enable RTC/Reset Wakeup From Hibernate */
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#define CANWE 0x0200 /* Enable CAN Wakeup From Hibernate */
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#define PHYWE 0x0400 /* Enable PHY Wakeup From Hibernate */
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#define GPWE 0x0400 /* General-purpose Wakeup From Hibernate */
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#define MXVRWE 0x0400 /* MXVR Wakeup From Hibernate */
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#define USBWE 0x0800 /* USB Wakeup From Hibernate */
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#define KPADWE 0x1000 /* Keypad Wakeup From Hibernate */
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#define ROTWE 0x2000 /* Rotary Counter Wakeup From Hibernate */
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#define CLKBUFOE 0x4000 /* CLKIN Buffer Output Enable */
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#define CKELOW 0x8000 /* Enable Drive CKE Low During Reset */
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#endif
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