upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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79 lines
3.4 KiB
79 lines
3.4 KiB
17 years ago
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/*
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* General Purpose Timer Masks
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*/
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#ifndef __BFIN_PERIPHERAL_TIMER__
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#define __BFIN_PERIPHERAL_TIMER__
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/* TIMER_ENABLE Masks */
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#define TIMEN0 0x0001 /* Enable Timer 0 */
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#define TIMEN1 0x0002 /* Enable Timer 1 */
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#define TIMEN2 0x0004 /* Enable Timer 2 */
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#define TIMEN3 0x0008 /* Enable Timer 3 */
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#define TIMEN4 0x0010 /* Enable Timer 4 */
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#define TIMEN5 0x0020 /* Enable Timer 5 */
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#define TIMEN6 0x0040 /* Enable Timer 6 */
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#define TIMEN7 0x0080 /* Enable Timer 7 */
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/* TIMER_DISABLE Masks */
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#define TIMDIS0 TIMEN0 /* Disable Timer 0 */
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#define TIMDIS1 TIMEN1 /* Disable Timer 1 */
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#define TIMDIS2 TIMEN2 /* Disable Timer 2 */
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#define TIMDIS3 TIMEN3 /* Disable Timer 3 */
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#define TIMDIS4 TIMEN4 /* Disable Timer 4 */
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#define TIMDIS5 TIMEN5 /* Disable Timer 5 */
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#define TIMDIS6 TIMEN6 /* Disable Timer 6 */
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#define TIMDIS7 TIMEN7 /* Disable Timer 7 */
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/* TIMER_STATUS Masks */
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#define TIMIL0 0x00000001 /* Timer 0 Interrupt */
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#define TIMIL1 0x00000002 /* Timer 1 Interrupt */
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#define TIMIL2 0x00000004 /* Timer 2 Interrupt */
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#define TIMIL3 0x00000008 /* Timer 3 Interrupt */
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#define TOVF_ERR0 0x00000010 /* Timer 0 Counter Overflow */
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#define TOVF_ERR1 0x00000020 /* Timer 1 Counter Overflow */
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#define TOVF_ERR2 0x00000040 /* Timer 2 Counter Overflow */
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#define TOVF_ERR3 0x00000080 /* Timer 3 Counter Overflow */
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#define TRUN0 0x00001000 /* Timer 0 Slave Enable Status */
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#define TRUN1 0x00002000 /* Timer 1 Slave Enable Status */
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#define TRUN2 0x00004000 /* Timer 2 Slave Enable Status */
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#define TRUN3 0x00008000 /* Timer 3 Slave Enable Status */
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#define TIMIL4 0x00010000 /* Timer 4 Interrupt */
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#define TIMIL5 0x00020000 /* Timer 5 Interrupt */
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#define TIMIL6 0x00040000 /* Timer 6 Interrupt */
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#define TIMIL7 0x00080000 /* Timer 7 Interrupt */
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#define TOVF_ERR4 0x00100000 /* Timer 4 Counter Overflow */
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#define TOVF_ERR5 0x00200000 /* Timer 5 Counter Overflow */
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#define TOVF_ERR6 0x00400000 /* Timer 6 Counter Overflow */
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#define TOVF_ERR7 0x00800000 /* Timer 7 Counter Overflow */
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#define TRUN4 0x10000000 /* Timer 4 Slave Enable Status */
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#define TRUN5 0x20000000 /* Timer 5 Slave Enable Status */
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#define TRUN6 0x40000000 /* Timer 6 Slave Enable Status */
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#define TRUN7 0x80000000 /* Timer 7 Slave Enable Status */
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/* Alternate Deprecated Macros Provided For Backwards Code Compatibility */
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#define TOVL_ERR0 TOVF_ERR0
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#define TOVL_ERR1 TOVF_ERR1
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#define TOVL_ERR2 TOVF_ERR2
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#define TOVL_ERR3 TOVF_ERR3
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#define TOVL_ERR4 TOVF_ERR4
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#define TOVL_ERR5 TOVF_ERR5
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#define TOVL_ERR6 TOVF_ERR6
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#define TOVL_ERR7 TOVF_ERR7
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/* TIMERx_CONFIG Masks */
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#define PWM_OUT 0x0001 /* Pulse-Width Modulation Output Mode */
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#define WDTH_CAP 0x0002 /* Width Capture Input Mode */
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#define EXT_CLK 0x0003 /* External Clock Mode */
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#define PULSE_HI 0x0004 /* Action Pulse (Positive/Negative*) */
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#define PERIOD_CNT 0x0008 /* Period Count */
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#define IRQ_ENA 0x0010 /* Interrupt Request Enable */
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#define TIN_SEL 0x0020 /* Timer Input Select */
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#define OUT_DIS 0x0040 /* Output Pad Disable */
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#define CLK_SEL 0x0080 /* Timer Clock Select */
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#define TOGGLE_HI 0x0100 /* PWM_OUT PULSE_HI Toggle Mode */
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#define EMU_RUN 0x0200 /* Emulation Behavior Select */
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#define ERR_TYP 0xC000 /* Error Type */
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#endif
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