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/*
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* (C) Copyright 2011 Freescale Semiconductor, Inc.
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include <common.h>
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#include <asm/io.h>
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#include <asm/arch/imx-regs.h>
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#include <asm/arch/mx5x_pins.h>
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#include <asm/arch/sys_proto.h>
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#include <asm/arch/crm_regs.h>
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#include <asm/arch/iomux.h>
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#include <asm/errno.h>
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#include <netdev.h>
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#include <mmc.h>
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#include <fsl_esdhc.h>
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#include <asm/gpio.h>
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DECLARE_GLOBAL_DATA_PTR;
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u32 get_board_rev(void)
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{
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return get_cpu_rev();
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}
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int dram_init(void)
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{
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u32 size1, size2;
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size1 = get_ram_size((void *)PHYS_SDRAM_1, PHYS_SDRAM_1_SIZE);
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size2 = get_ram_size((void *)PHYS_SDRAM_2, PHYS_SDRAM_2_SIZE);
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gd->ram_size = size1 + size2;
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return 0;
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}
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void dram_init_banksize(void)
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{
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gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
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gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
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gd->bd->bi_dram[1].start = PHYS_SDRAM_2;
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gd->bd->bi_dram[1].size = PHYS_SDRAM_2_SIZE;
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}
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static void setup_iomux_uart(void)
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{
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/* UART1 RXD */
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mxc_request_iomux(MX53_PIN_CSI0_D11, IOMUX_CONFIG_ALT2);
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mxc_iomux_set_pad(MX53_PIN_CSI0_D11,
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PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH |
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PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE |
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PAD_CTL_HYS_ENABLE | PAD_CTL_100K_PU |
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PAD_CTL_ODE_OPENDRAIN_ENABLE);
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mxc_iomux_set_input(MX53_UART1_IPP_UART_RXD_MUX_SELECT_INPUT, 0x1);
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/* UART1 TXD */
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mxc_request_iomux(MX53_PIN_CSI0_D10, IOMUX_CONFIG_ALT2);
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mxc_iomux_set_pad(MX53_PIN_CSI0_D10,
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PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH |
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PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE |
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PAD_CTL_HYS_ENABLE | PAD_CTL_100K_PU |
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PAD_CTL_ODE_OPENDRAIN_ENABLE);
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}
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static void setup_iomux_fec(void)
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{
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/*FEC_MDIO*/
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mxc_request_iomux(MX53_PIN_FEC_MDIO, IOMUX_CONFIG_ALT0);
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mxc_iomux_set_pad(MX53_PIN_FEC_MDIO,
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PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH |
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PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE |
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PAD_CTL_22K_PU | PAD_CTL_ODE_OPENDRAIN_ENABLE);
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mxc_iomux_set_input(MX53_FEC_FEC_MDI_SELECT_INPUT, 0x1);
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/*FEC_MDC*/
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mxc_request_iomux(MX53_PIN_FEC_MDC, IOMUX_CONFIG_ALT0);
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mxc_iomux_set_pad(MX53_PIN_FEC_MDC, PAD_CTL_DRV_HIGH);
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/* FEC RXD1 */
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mxc_request_iomux(MX53_PIN_FEC_RXD1, IOMUX_CONFIG_ALT0);
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mxc_iomux_set_pad(MX53_PIN_FEC_RXD1,
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PAD_CTL_HYS_ENABLE | PAD_CTL_PKE_ENABLE);
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/* FEC RXD0 */
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mxc_request_iomux(MX53_PIN_FEC_RXD0, IOMUX_CONFIG_ALT0);
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mxc_iomux_set_pad(MX53_PIN_FEC_RXD0,
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PAD_CTL_HYS_ENABLE | PAD_CTL_PKE_ENABLE);
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/* FEC TXD1 */
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mxc_request_iomux(MX53_PIN_FEC_TXD1, IOMUX_CONFIG_ALT0);
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mxc_iomux_set_pad(MX53_PIN_FEC_TXD1, PAD_CTL_DRV_HIGH);
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/* FEC TXD0 */
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mxc_request_iomux(MX53_PIN_FEC_TXD0, IOMUX_CONFIG_ALT0);
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mxc_iomux_set_pad(MX53_PIN_FEC_TXD0, PAD_CTL_DRV_HIGH);
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/* FEC TX_EN */
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mxc_request_iomux(MX53_PIN_FEC_TX_EN, IOMUX_CONFIG_ALT0);
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mxc_iomux_set_pad(MX53_PIN_FEC_TX_EN, PAD_CTL_DRV_HIGH);
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/* FEC TX_CLK */
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mxc_request_iomux(MX53_PIN_FEC_REF_CLK, IOMUX_CONFIG_ALT0);
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mxc_iomux_set_pad(MX53_PIN_FEC_REF_CLK,
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PAD_CTL_HYS_ENABLE | PAD_CTL_PKE_ENABLE);
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/* FEC RX_ER */
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mxc_request_iomux(MX53_PIN_FEC_RX_ER, IOMUX_CONFIG_ALT0);
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mxc_iomux_set_pad(MX53_PIN_FEC_RX_ER,
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PAD_CTL_HYS_ENABLE | PAD_CTL_PKE_ENABLE);
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/* FEC CRS */
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mxc_request_iomux(MX53_PIN_FEC_CRS_DV, IOMUX_CONFIG_ALT0);
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mxc_iomux_set_pad(MX53_PIN_FEC_CRS_DV,
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PAD_CTL_HYS_ENABLE | PAD_CTL_PKE_ENABLE);
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}
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#ifdef CONFIG_FSL_ESDHC
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struct fsl_esdhc_cfg esdhc_cfg[1] = {
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{MMC_SDHC1_BASE_ADDR, 1},
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};
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int board_mmc_getcd(u8 *cd, struct mmc *mmc)
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{
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*cd = gpio_get_value(77); /*GPIO3_13*/
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return 0;
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}
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int board_mmc_init(bd_t *bis)
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{
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u32 index;
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s32 status = 0;
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for (index = 0; index < CONFIG_SYS_FSL_ESDHC_NUM; index++) {
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switch (index) {
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case 0:
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mxc_request_iomux(MX53_PIN_SD1_CMD, IOMUX_CONFIG_ALT0);
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mxc_request_iomux(MX53_PIN_SD1_CLK, IOMUX_CONFIG_ALT0);
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mxc_request_iomux(MX53_PIN_SD1_DATA0,
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IOMUX_CONFIG_ALT0);
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mxc_request_iomux(MX53_PIN_SD1_DATA1,
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IOMUX_CONFIG_ALT0);
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mxc_request_iomux(MX53_PIN_SD1_DATA2,
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IOMUX_CONFIG_ALT0);
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mxc_request_iomux(MX53_PIN_SD1_DATA3,
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IOMUX_CONFIG_ALT0);
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mxc_request_iomux(MX53_PIN_EIM_DA13,
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IOMUX_CONFIG_ALT1);
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mxc_iomux_set_pad(MX53_PIN_SD1_CMD,
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PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH |
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PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE |
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PAD_CTL_HYS_ENABLE | PAD_CTL_100K_PU);
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mxc_iomux_set_pad(MX53_PIN_SD1_CLK,
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PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE |
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PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU |
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PAD_CTL_DRV_HIGH);
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mxc_iomux_set_pad(MX53_PIN_SD1_DATA0,
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PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH |
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PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE |
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PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU);
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mxc_iomux_set_pad(MX53_PIN_SD1_DATA1,
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PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH |
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PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE |
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PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU);
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mxc_iomux_set_pad(MX53_PIN_SD1_DATA2,
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PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH |
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PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE |
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PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU);
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mxc_iomux_set_pad(MX53_PIN_SD1_DATA3,
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PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH |
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PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE |
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PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU);
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break;
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default:
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printf("Warning: you configured more ESDHC controller"
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"(%d) as supported by the board(1)\n",
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CONFIG_SYS_FSL_ESDHC_NUM);
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return status;
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}
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status |= fsl_esdhc_initialize(bis, &esdhc_cfg[index]);
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}
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return status;
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}
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#endif
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int board_early_init_f(void)
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{
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setup_iomux_uart();
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setup_iomux_fec();
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return 0;
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}
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int board_init(void)
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{
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gd->bd->bi_arch_number = MACH_TYPE_MX53_SMD;
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/* address of boot parameters */
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gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100;
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return 0;
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}
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int checkboard(void)
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{
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puts("Board: MX53SMD\n");
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return 0;
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}
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