upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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333 lines
6.8 KiB
333 lines
6.8 KiB
7 years ago
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/*
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* Copyright 2017 NXP
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <i2c.h>
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#include <malloc.h>
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#include <errno.h>
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#include <netdev.h>
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#include <fsl_ifc.h>
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#include <fsl_ddr.h>
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#include <fsl_sec.h>
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#include <asm/io.h>
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#include <fdt_support.h>
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#include <libfdt.h>
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#include <fsl-mc/fsl_mc.h>
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#include <environment.h>
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#include <asm/arch-fsl-layerscape/soc.h>
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#include <asm/arch/ppa.h>
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#include "../common/qixis.h"
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#include "ls1088a_qixis.h"
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DECLARE_GLOBAL_DATA_PTR;
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unsigned long long get_qixis_addr(void)
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{
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unsigned long long addr;
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if (gd->flags & GD_FLG_RELOC)
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addr = QIXIS_BASE_PHYS;
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else
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addr = QIXIS_BASE_PHYS_EARLY;
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/*
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* IFC address under 256MB is mapped to 0x30000000, any address above
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* is mapped to 0x5_10000000 up to 4GB.
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*/
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addr = addr > 0x10000000 ? addr + 0x500000000ULL : addr + 0x30000000;
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return addr;
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}
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int checkboard(void)
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{
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char buf[64];
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u8 sw;
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static const char *const freq[] = {"100", "125", "156.25",
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"100 separate SSCG"};
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int clock;
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printf("Board: LS1088A-RDB, ");
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sw = QIXIS_READ(arch);
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printf("Board Arch: V%d, ", sw >> 4);
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printf("Board version: %c, boot from ", (sw & 0xf) + 'A');
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memset((u8 *)buf, 0x00, ARRAY_SIZE(buf));
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sw = QIXIS_READ(brdcfg[0]);
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sw = (sw & QIXIS_LBMAP_MASK) >> QIXIS_LBMAP_SHIFT;
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#ifdef CONFIG_SD_BOOT
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puts("SD card\n");
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#endif
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switch (sw) {
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case 0:
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puts("QSPI:");
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sw = QIXIS_READ(brdcfg[0]);
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sw = (sw & QIXIS_QMAP_MASK) >> QIXIS_QMAP_SHIFT;
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if (sw == 0 || sw == 4)
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puts("0\n");
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else if (sw == 1)
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puts("1\n");
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else
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puts("EMU\n");
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break;
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default:
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printf("invalid setting of SW%u\n", QIXIS_LBMAP_SWITCH);
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break;
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}
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printf("CPLD: v%d.%d\n", QIXIS_READ(scver), QIXIS_READ(tagdata));
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/*
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* Display the actual SERDES reference clocks as configured by the
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* dip switches on the board. Note that the SWx registers could
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* technically be set to force the reference clocks to match the
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* values that the SERDES expects (or vice versa). For now, however,
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* we just display both values and hope the user notices when they
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* don't match.
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*/
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puts("SERDES1 Reference : ");
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sw = QIXIS_READ(brdcfg[2]);
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clock = (sw >> 6) & 3;
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printf("Clock1 = %sMHz ", freq[clock]);
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clock = (sw >> 4) & 3;
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printf("Clock2 = %sMHz", freq[clock]);
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puts("\nSERDES2 Reference : ");
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clock = (sw >> 2) & 3;
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printf("Clock1 = %sMHz ", freq[clock]);
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clock = (sw >> 0) & 3;
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printf("Clock2 = %sMHz\n", freq[clock]);
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return 0;
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}
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bool if_board_diff_clk(void)
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{
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u8 diff_conf = QIXIS_READ(dutcfg[11]);
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return diff_conf & 0x80;
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}
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unsigned long get_board_sys_clk(void)
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{
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u8 sysclk_conf = QIXIS_READ(brdcfg[1]);
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switch (sysclk_conf & 0x0f) {
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case QIXIS_SYSCLK_83:
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return 83333333;
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case QIXIS_SYSCLK_100:
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return 100000000;
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case QIXIS_SYSCLK_125:
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return 125000000;
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case QIXIS_SYSCLK_133:
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return 133333333;
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case QIXIS_SYSCLK_150:
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return 150000000;
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case QIXIS_SYSCLK_160:
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return 160000000;
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case QIXIS_SYSCLK_166:
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return 166666666;
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}
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return 66666666;
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}
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unsigned long get_board_ddr_clk(void)
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{
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u8 ddrclk_conf = QIXIS_READ(brdcfg[1]);
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if (if_board_diff_clk())
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return get_board_sys_clk();
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switch ((ddrclk_conf & 0x30) >> 4) {
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case QIXIS_DDRCLK_100:
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return 100000000;
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case QIXIS_DDRCLK_125:
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return 125000000;
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case QIXIS_DDRCLK_133:
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return 133333333;
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}
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return 66666666;
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}
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int select_i2c_ch_pca9547(u8 ch)
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{
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int ret;
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ret = i2c_write(I2C_MUX_PCA_ADDR_PRI, 0, 1, &ch, 1);
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if (ret) {
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puts("PCA: failed to select proper channel\n");
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return ret;
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}
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return 0;
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}
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void board_retimer_init(void)
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{
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u8 reg;
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/* Retimer is connected to I2C1_CH5 */
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select_i2c_ch_pca9547(I2C_MUX_CH5);
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/* Access to Control/Shared register */
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reg = 0x0;
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i2c_write(I2C_RETIMER_ADDR, 0xff, 1, ®, 1);
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/* Read device revision and ID */
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i2c_read(I2C_RETIMER_ADDR, 1, 1, ®, 1);
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debug("Retimer version id = 0x%x\n", reg);
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/* Enable Broadcast. All writes target all channel register sets */
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reg = 0x0c;
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i2c_write(I2C_RETIMER_ADDR, 0xff, 1, ®, 1);
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/* Reset Channel Registers */
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i2c_read(I2C_RETIMER_ADDR, 0, 1, ®, 1);
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reg |= 0x4;
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i2c_write(I2C_RETIMER_ADDR, 0, 1, ®, 1);
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/* Set data rate as 10.3125 Gbps */
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reg = 0x90;
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i2c_write(I2C_RETIMER_ADDR, 0x60, 1, ®, 1);
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reg = 0xb3;
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i2c_write(I2C_RETIMER_ADDR, 0x61, 1, ®, 1);
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reg = 0x90;
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i2c_write(I2C_RETIMER_ADDR, 0x62, 1, ®, 1);
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reg = 0xb3;
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i2c_write(I2C_RETIMER_ADDR, 0x63, 1, ®, 1);
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reg = 0xcd;
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i2c_write(I2C_RETIMER_ADDR, 0x64, 1, ®, 1);
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/* Select VCO Divider to full rate (000) */
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i2c_read(I2C_RETIMER_ADDR, 0x2F, 1, ®, 1);
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reg &= 0x0f;
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reg |= 0x70;
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i2c_write(I2C_RETIMER_ADDR, 0x2F, 1, ®, 1);
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/*return the default channel*/
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select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT);
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}
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int board_init(void)
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{
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init_final_memctl_regs();
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#if defined(CONFIG_TARGET_LS1088ARDB) && defined(CONFIG_FSL_MC_ENET)
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u32 __iomem *irq_ccsr = (u32 __iomem *)ISC_BASE;
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#endif
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select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT);
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board_retimer_init();
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#ifdef CONFIG_ENV_IS_NOWHERE
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gd->env_addr = (ulong)&default_environment[0];
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#endif
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#if defined(CONFIG_TARGET_LS1088ARDB) && defined(CONFIG_FSL_MC_ENET)
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/* invert AQR105 IRQ pins polarity */
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out_le32(irq_ccsr + IRQCR_OFFSET / 4, AQR105_IRQ_MASK);
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#endif
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#ifdef CONFIG_FSL_LS_PPA
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ppa_init();
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#endif
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return 0;
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}
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int board_early_init_f(void)
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{
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fsl_lsch3_early_init_f();
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return 0;
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}
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void detail_board_ddr_info(void)
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{
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puts("\nDDR ");
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print_size(gd->bd->bi_dram[0].size + gd->bd->bi_dram[1].size, "");
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print_ddr_info(0);
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}
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#if defined(CONFIG_ARCH_MISC_INIT)
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int arch_misc_init(void)
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{
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#ifdef CONFIG_FSL_CAAM
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sec_init();
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#endif
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return 0;
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}
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#endif
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#ifdef CONFIG_FSL_MC_ENET
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void fdt_fixup_board_enet(void *fdt)
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{
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int offset;
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offset = fdt_path_offset(fdt, "/fsl-mc");
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if (offset < 0)
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offset = fdt_path_offset(fdt, "/fsl,dprc@0");
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if (offset < 0) {
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printf("%s: ERROR: fsl-mc node not found in device tree (error %d)\n",
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__func__, offset);
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return;
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}
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if (get_mc_boot_status() == 0)
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fdt_status_okay(fdt, offset);
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else
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fdt_status_fail(fdt, offset);
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}
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#endif
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#ifdef CONFIG_OF_BOARD_SETUP
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int ft_board_setup(void *blob, bd_t *bd)
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{
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int err, i;
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u64 base[CONFIG_NR_DRAM_BANKS];
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u64 size[CONFIG_NR_DRAM_BANKS];
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ft_cpu_setup(blob, bd);
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/* fixup DT for the two GPP DDR banks */
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for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) {
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base[i] = gd->bd->bi_dram[i].start;
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size[i] = gd->bd->bi_dram[i].size;
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}
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#ifdef CONFIG_RESV_RAM
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/* reduce size if reserved memory is within this bank */
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if (gd->arch.resv_ram >= base[0] &&
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gd->arch.resv_ram < base[0] + size[0])
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size[0] = gd->arch.resv_ram - base[0];
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else if (gd->arch.resv_ram >= base[1] &&
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gd->arch.resv_ram < base[1] + size[1])
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size[1] = gd->arch.resv_ram - base[1];
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#endif
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fdt_fixup_memory_banks(blob, base, size, CONFIG_NR_DRAM_BANKS);
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#ifdef CONFIG_FSL_MC_ENET
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fdt_fixup_board_enet(blob);
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err = fsl_mc_ldpaa_exit(bd);
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if (err)
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return err;
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#endif
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return 0;
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}
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#endif
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