upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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54 lines
1.2 KiB
54 lines
1.2 KiB
9 years ago
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/*
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* From Coreboot soc/intel/broadwell/include/soc/iomap.h
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*
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* Copyright (C) 2016 Google Inc.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#ifndef __asm_arch_iomap_h
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#define __asm_arch_iomap_h
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#define MCFG_BASE_ADDRESS 0xf0000000
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#define MCFG_BASE_SIZE 0x4000000
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#define HPET_BASE_ADDRESS 0xfed00000
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#define MCH_BASE_ADDRESS 0xfed10000
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#define MCH_BASE_SIZE 0x8000
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#define DMI_BASE_ADDRESS 0xfed18000
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#define DMI_BASE_SIZE 0x1000
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#define EP_BASE_ADDRESS 0xfed19000
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#define EP_BASE_SIZE 0x1000
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#define EDRAM_BASE_ADDRESS 0xfed80000
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#define EDRAM_BASE_SIZE 0x4000
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#define GDXC_BASE_ADDRESS 0xfed84000
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#define GDXC_BASE_SIZE 0x1000
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#define RCBA_BASE_ADDRESS 0xfed1c000
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#define RCBA_BASE_SIZE 0x4000
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#define HPET_BASE_ADDRESS 0xfed00000
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#define ACPI_BASE_ADDRESS 0x1000
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#define ACPI_BASE_SIZE 0x100
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#define GPIO_BASE_ADDRESS 0x1400
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#define GPIO_BASE_SIZE 0x400
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#define SMBUS_BASE_ADDRESS 0x0400
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#define SMBUS_BASE_SIZE 0x10
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/* Temporary addresses used before relocation */
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#define EARLY_GTT_BAR 0xe0000000
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#define EARLY_XHCI_BAR 0xd7000000
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#define EARLY_EHCI_BAR 0xd8000000
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#define EARLY_UART_BAR 0x3f8
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#define EARLY_TEMP_MMIO 0xfed08000
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#endif
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