upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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129 lines
4.0 KiB
129 lines
4.0 KiB
22 years ago
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/*
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* Copyright (C) 1998 Dan Malek <dmalek@jlc.net>
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* Copyright (C) 1999 Magnus Damm <kieraypc01.p.y.kie.era.ericsson.se>
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* Copyright (C) 2001 Sysgo Real-Time Solutions, GmbH <www.elinos.com>
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* Andreas Heppel <aheppel@sysgo.de>
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* Copyright (C) 2003 Wolfgang Denk <wd@denx.de>
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include <config.h>
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#include <ppc_asm.tmpl>
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/* ------------------------------------------------------------------------------- */
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/* Function: in8 */
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/* Description: Input 8 bits */
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/* ------------------------------------------------------------------------------- */
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.globl in8
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in8:
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lbz r3,0(r3)
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sync
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blr
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/* ------------------------------------------------------------------------------- */
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/* Function: in16 */
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/* Description: Input 16 bits */
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/* ------------------------------------------------------------------------------- */
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.globl in16
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in16:
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lhz r3,0(r3)
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sync
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blr
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/* ------------------------------------------------------------------------------- */
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/* Function: in16r */
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/* Description: Input 16 bits and byte reverse */
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/* ------------------------------------------------------------------------------- */
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.globl in16r
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in16r:
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lhbrx r3,0,r3
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sync
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blr
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/* ------------------------------------------------------------------------------- */
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/* Function: in32 */
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/* Description: Input 32 bits */
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/* ------------------------------------------------------------------------------- */
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.globl in32
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in32:
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lwz 3,0(3)
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sync
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blr
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/* ------------------------------------------------------------------------------- */
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/* Function: in32r */
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/* Description: Input 32 bits and byte reverse */
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/* ------------------------------------------------------------------------------- */
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.globl in32r
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in32r:
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lwbrx r3,0,r3
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sync
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blr
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/* ------------------------------------------------------------------------------- */
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/* Function: out8 */
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/* Description: Output 8 bits */
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/* ------------------------------------------------------------------------------- */
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.globl out8
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out8:
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stb r4,0(r3)
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sync
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blr
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/* ------------------------------------------------------------------------------- */
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/* Function: out16 */
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/* Description: Output 16 bits */
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/* ------------------------------------------------------------------------------- */
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.globl out16
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out16:
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sth r4,0(r3)
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sync
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blr
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/* ------------------------------------------------------------------------------- */
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/* Function: out16r */
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/* Description: Byte reverse and output 16 bits */
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/* ------------------------------------------------------------------------------- */
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.globl out16r
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out16r:
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sthbrx r4,0,r3
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sync
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blr
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/* ------------------------------------------------------------------------------- */
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/* Function: out32 */
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/* Description: Output 32 bits */
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/* ------------------------------------------------------------------------------- */
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.globl out32
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out32:
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stw r4,0(r3)
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sync
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blr
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/* ------------------------------------------------------------------------------- */
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/* Function: out32r */
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/* Description: Byte reverse and output 32 bits */
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/* ------------------------------------------------------------------------------- */
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.globl out32r
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out32r:
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stwbrx r4,0,r3
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sync
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blr
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