upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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126 lines
4.8 KiB
126 lines
4.8 KiB
21 years ago
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/***********************************************************************
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*
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* Copyright (C) 2004 by FS Forth-Systeme GmbH.
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* All rights reserved.
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*
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* $Id: ns9750_bbus.h,v 1.1 2004/02/16 10:37:20 mpietrek Exp $
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* @Author: Markus Pietrek
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* @Descr: Definitions for BBus usage
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* @References: [1] NS9750 Hardware Reference Manual/December 2003 Chap. 10
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*
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*
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***********************************************************************/
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#ifndef FS_NS9750_BBUS_H
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#define FS_NS9750_BBUS_H
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#define NS9750_BBUS_MODULE_BASE (0x90600000)
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#define get_bbus_reg_addr(c) \
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((volatile unsigned int *)(NS9750_BBUS_MODULE_BASE+(unsigned int) (c)))
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/* We have support for 50 GPIO pins */
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#define get_gpio_cfg_reg_addr(pin) \
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get_bbus_reg_addr( NS9750_BBUS_GPIO_CFG_BASE + (((pin) >> 3) * 4) )
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/* To Read/Modify/Write a pin configuration register, use it like
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set_gpio_cfg_reg_val( 12, NS9750_GPIO_CFG_FUNC_GPIO|NS9750_GPIO_CFG_OUTPUT );
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They should be wrapped by cli()/sti() */
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#define set_gpio_cfg_reg_val(pin,cfg) \
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*get_gpio_cfg_reg_addr(pin)=(*get_gpio_cfg_reg_addr((pin)) & \
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~NS9750_GPIO_CFG_MASK((pin))) |\
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NS9750_GPIO_CFG_VAL((pin),(cfg));
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#define NS9750_GPIO_CFG_MASK(pin) (NS9750_GPIO_CFG_VAL(pin, \
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NS9750_GPIO_CFG_MA))
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#define NS9750_GPIO_CFG_VAL(pin,cfg) ((cfg) << (((pin) % 8) * 4))
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#define NS9750_GPIO_CFG_MA (0x0F)
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#define NS9750_GPIO_CFG_INPUT (0x00)
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#define NS9750_GPIO_CFG_OUTPUT (0x08)
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#define NS9750_GPIO_CFG_FUNC_GPIO (0x03)
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#define NS9750_GPIO_CFG_FUNC_2 (0x02)
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#define NS9750_GPIO_CFG_FUNC_1 (0x01)
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#define NS9750_GPIO_CFG_FUNC_0 (0x00)
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/* the register addresses */
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#define NS9750_BBUS_MASTER_RESET (0x00)
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#define NS9750_BBUS_GPIO_CFG_BASE (0x10)
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#define NS9750_BBUS_GPIO_CTRL_BASE (0x30)
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#define NS9750_BBUS_GPIO_STAT_BASE (0x40)
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#define NS9750_BBUS_MONITOR (0x50)
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#define NS9750_BBUS_DMA_INT_STAT (0x60)
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#define NS9750_BBUS_DMA_INT_ENABLE (0x64)
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#define NS9750_BBUS_USB_CFG (0x70)
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#define NS9750_BBUS_ENDIAN_CFG (0x80)
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#define NS9750_BBUS_ARM_WAKE_UP (0x90)
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/* register bit fields */
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#define NS9750_BBUS_MASTER_RESET_UTIL (0x00000100)
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#define NS9750_BBUS_MASTER_RESET_I2C (0x00000080)
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#define NS9750_BBUS_MASTER_RESET_1284 (0x00000040)
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#define NS9750_BBUS_MASTER_RESET_SER4 (0x00000020)
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#define NS9750_BBUS_MASTER_RESET_SER3 (0x00000010)
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#define NS9750_BBUS_MASTER_RESET_SER2 (0x00000008)
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#define NS9750_BBUS_MASTER_RESET_SER1 (0x00000004)
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#define NS9750_BBUS_MASTER_RESET_USB (0x00000002)
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#define NS9750_BBUS_MASTER_RESET_DMA (0x00000001)
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/* BS9750_BBUS_DMA_INT_BINT* are valid for *DMA_INT_STAT and *DMA_INT_ENABLE */
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#define NS9750_BBUS_DMA_INT_BINT16 (0x00010000)
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#define NS9750_BBUS_DMA_INT_BINT15 (0x00008000)
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#define NS9750_BBUS_DMA_INT_BINT14 (0x00004000)
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#define NS9750_BBUS_DMA_INT_BINT13 (0x00002000)
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#define NS9750_BBUS_DMA_INT_BINT12 (0x00001000)
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#define NS9750_BBUS_DMA_INT_BINT11 (0x00000800)
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#define NS9750_BBUS_DMA_INT_BINT10 (0x00000400)
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#define NS9750_BBUS_DMA_INT_BINT9 (0x00000200)
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#define NS9750_BBUS_DMA_INT_BINT8 (0x00000100)
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#define NS9750_BBUS_DMA_INT_BINT7 (0x00000080)
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#define NS9750_BBUS_DMA_INT_BINT6 (0x00000040)
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#define NS9750_BBUS_DMA_INT_BINT5 (0x00000020)
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#define NS9750_BBUS_DMA_INT_BINT4 (0x00000010)
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#define NS9750_BBUS_DMA_INT_BINT3 (0x00000008)
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#define NS9750_BBUS_DMA_INT_BINT2 (0x00000004)
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#define NS9750_BBUS_DMA_INT_BINT1 (0x00000002)
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#define NS9750_BBUS_DMA_INT_BINT0 (0x00000001)
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#define NS9750_BBUS_USB_CFG_OUTEN (0x00000008)
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#define NS9750_BBUS_USB_CFG_SPEED (0x00000004)
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#define NS9750_BBUS_USB_CFG_CFG_MA (0x00000003)
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#define NS9750_BBUS_USB_CFG_CFG_HOST_SOFT (0x00000003)
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#define NS9750_BBUS_USB_CFG_CFG_DEVICE (0x00000002)
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#define NS9750_BBUS_USB_CFG_CFG_HOST (0x00000001)
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#define NS9750_BBUS_USB_CFG_CFG_DIS (0x00000000)
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#define NS9750_BBUS_ENDIAN_CFG_AHBM (0x00001000)
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#define NS9750_BBUS_ENDIAN_CFG_I2C (0x00000080)
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#define NS9750_BBUS_ENDIAN_CFG_IEEE1284 (0x00000040)
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#define NS9750_BBUS_ENDIAN_CFG_SER4 (0x00000020)
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#define NS9750_BBUS_ENDIAN_CFG_SER3 (0x00000010)
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#define NS9750_BBUS_ENDIAN_CFG_SER2 (0x00000008)
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#define NS9750_BBUS_ENDIAN_CFG_SER1 (0x00000004)
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#define NS9750_BBUS_ENDIAN_CFG_USB (0x00000002)
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#define NS9750_BBUS_ENDIAN_CFG_DMA (0x00000001)
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#endif /* FS_NS9750_BBUS_H */
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