upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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101 lines
5.2 KiB
101 lines
5.2 KiB
22 years ago
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/*
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* Copyright (C) 2002 Scott McNutt <smcnutt@artesyncp.com>
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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/*
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* Interrupt vector number definitions to ease the
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* 405 -- 440 porting pain ;-)
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*
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* NOTE: They're not all here yet ... update as needed.
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*
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*/
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#ifndef _VECNUMS_H_
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#define _VECNUMS_H_
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#if defined(CONFIG_440)
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/* UIC 0 */
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#define VECNUM_U0 0 /* UART0 */
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#define VECNUM_U1 1 /* UART1 */
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#define VECNUM_IIC0 2 /* IIC0 */
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#define VECNUM_IIC1 3 /* IIC1 */
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#define VECNUM_PIM 4 /* PCI inbound message */
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#define VECNUM_PCRW 5 /* PCI command reg write */
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#define VECNUM_PPM 6 /* PCI power management */
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#define VECNUM_MSI0 7 /* PCI MSI level 0 */
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#define VECNUM_MSI1 8 /* PCI MSI level 0 */
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#define VECNUM_MSI2 9 /* PCI MSI level 0 */
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#define VECNUM_MTE 10 /* MAL TXEOB */
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#define VECNUM_MRE 11 /* MAL RXEOB */
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#define VECNUM_D0 12 /* DMA channel 0 */
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#define VECNUM_D1 13 /* DMA channel 1 */
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#define VECNUM_D2 14 /* DMA channel 2 */
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#define VECNUM_D3 15 /* DMA channel 3 */
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#define VECNUM_CT0 18 /* GPT compare timer 0 */
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#define VECNUM_CT1 19 /* GPT compare timer 1 */
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#define VECNUM_CT2 20 /* GPT compare timer 2 */
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#define VECNUM_CT3 21 /* GPT compare timer 3 */
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#define VECNUM_CT4 22 /* GPT compare timer 4 */
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#define VECNUM_EIR0 23 /* External interrupt 0 */
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#define VECNUM_EIR1 24 /* External interrupt 1 */
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#define VECNUM_EIR2 25 /* External interrupt 2 */
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#define VECNUM_EIR3 26 /* External interrupt 3 */
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#define VECNUM_EIR4 27 /* External interrupt 4 */
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#define VECNUM_EIR5 28 /* External interrupt 5 */
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#define VECNUM_EIR6 29 /* External interrupt 6 */
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#define VECNUM_UIC1NC 30 /* UIC1 non-critical interrupt */
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#define VECNUM_UIC1C 31 /* UIC1 critical interrupt */
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/* UIC 1 */
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#define VECNUM_MS (32 + 0 ) /* MAL SERR */
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#define VECNUM_TXDE (32 + 1 ) /* MAL TXDE */
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#define VECNUM_RXDE (32 + 2 ) /* MAL RXDE */
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#define VECNUM_ETH0 (32 + 28) /* Ethernet 0 interrupt status */
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#define VECNUM_EWU0 (32 + 29) /* Ethernet 0 wakeup */
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#else /* !defined(CONFIG_440) */
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#define VECNUM_U0 0 /* UART0 */
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#define VECNUM_U1 1 /* UART1 */
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#define VECNUM_D0 5 /* DMA channel 0 */
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#define VECNUM_D1 6 /* DMA channel 1 */
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#define VECNUM_D2 7 /* DMA channel 2 */
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#define VECNUM_D3 8 /* DMA channel 3 */
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#define VECNUM_EWU0 9 /* Ethernet wakeup */
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#define VECNUM_MS 10 /* MAL SERR */
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#define VECNUM_MTE 11 /* MAL TXEOB */
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#define VECNUM_MRE 12 /* MAL RXEOB */
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#define VECNUM_TXDE 13 /* MAL TXDE */
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#define VECNUM_RXDE 14 /* MAL RXDE */
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#define VECNUM_ETH0 15 /* Ethernet interrupt status */
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#define VECNUM_EIR0 25 /* External interrupt 0 */
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#define VECNUM_EIR1 26 /* External interrupt 1 */
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#define VECNUM_EIR2 27 /* External interrupt 2 */
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#define VECNUM_EIR3 28 /* External interrupt 3 */
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#define VECNUM_EIR4 29 /* External interrupt 4 */
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#define VECNUM_EIR5 30 /* External interrupt 5 */
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#define VECNUM_EIR6 31 /* External interrupt 6 */
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#endif /* defined(CONFIG_440) */
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#endif /* _VECNUMS_H_ */
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