upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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219 lines
5.6 KiB
219 lines
5.6 KiB
14 years ago
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/*
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* Copyright (C) 2011 Renesas Solutions Corp.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*
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*/
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#ifndef _ASM_CPU_SH7757_H_
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#define _ASM_CPU_SH7757_H_
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#define CCR 0xFF00001C
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#define WTCNT 0xFFCC0000
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#define CCR_CACHE_INIT 0x0000090b
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#define CACHE_OC_NUM_WAYS 1
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#ifndef __ASSEMBLY__ /* put C only stuff in this section */
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/* MMU */
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struct mmu_regs {
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unsigned int reserved[4];
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unsigned int mmucr;
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};
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#define MMU_BASE ((struct mmu_regs *)0xff000000)
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/* Watchdog */
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#define WTCSR0 0xffcc0002
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#define WRSTCSR_R 0xffcc0003
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#define WRSTCSR_W 0xffcc0002
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#define WTCSR_PREFIX 0xa500
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#define WRSTCSR_PREFIX 0x6900
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#define WRSTCSR_WOVF_PREFIX 0x9600
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/* SCIF */
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#define SCIF0_BASE 0xfe4b0000 /* The real name is SCIF2 */
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#define SCIF1_BASE 0xfe4c0000 /* The real name is SCIF3 */
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#define SCIF2_BASE 0xfe4d0000 /* The real name is SCIF4 */
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/* SerMux */
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#define SMR0 0xfe470000
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/* TMU0 */
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#define TSTR 0xFE430004
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#define TOCR 0xFE430000
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#define TSTR0 0xFE430004
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#define TCOR0 0xFE430008
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#define TCNT0 0xFE43000C
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#define TCR0 0xFE430010
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#define TCOR1 0xFE430014
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#define TCNT1 0xFE430018
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#define TCR1 0xFE43001C
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#define TCOR2 0xFE430020
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#define TCNT2 0xFE430024
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#define TCR2 0xFE430028
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#define TCPR2 0xFE43002C
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/* ETHER, GETHER MAC address */
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struct ether_mac_regs {
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unsigned int reserved[114];
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unsigned int mahr;
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unsigned int reserved2;
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unsigned int malr;
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};
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#define GETHER0_MAC_BASE ((struct ether_mac_regs *)0xfee0400)
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#define GETHER1_MAC_BASE ((struct ether_mac_regs *)0xfee0c00)
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#define ETHER0_MAC_BASE ((struct ether_mac_regs *)0xfef0000)
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#define ETHER1_MAC_BASE ((struct ether_mac_regs *)0xfef0800)
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/* GETHER */
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struct gether_control_regs {
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unsigned int gbecont;
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};
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#define GETHER_CONTROL_BASE ((struct gether_control_regs *)0xffc10100)
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#define GBECONT_RMII1 0x00020000
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#define GBECONT_RMII0 0x00010000
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/* USB0/1 */
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struct usb_common_regs {
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unsigned short reserved[129];
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unsigned short suspmode;
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};
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#define USB0_COMMON_BASE ((struct usb_common_regs *)0xfe450000)
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#define USB1_COMMON_BASE ((struct usb_common_regs *)0xfe4f0000)
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struct usb0_phy_regs {
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unsigned short reset;
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unsigned short reserved[4];
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unsigned short portsel;
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};
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#define USB0_PHY_BASE ((struct usb0_phy_regs *)0xfe5f0000)
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struct usb1_port_regs {
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unsigned int port1sel;
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unsigned int reserved;
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unsigned int usb1intsts;
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};
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#define USB1_PORT_BASE ((struct usb1_port_regs *)0xfe4f2000)
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struct usb1_alignment_regs {
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unsigned int ehcidatac; /* 0xfe4fe018 */
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unsigned int reserved[63];
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unsigned int ohcidatac;
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};
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#define USB1_ALIGNMENT_BASE ((struct usb1_alignment_regs *)0xfe4fe018)
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/* GCTRL, GRA */
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struct gctrl_regs {
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unsigned int wprotect;
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unsigned int gplldiv;
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unsigned int gracr2; /* GRA */
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unsigned int gracr3; /* GRA */
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unsigned int reserved[4];
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unsigned int fcntcr1;
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unsigned int fcntcr2;
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unsigned int reserved2[2];
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unsigned int gpll1div;
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unsigned int vcompsel;
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unsigned int reserved3[62];
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unsigned int fdlmon;
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unsigned int reserved4[2];
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unsigned int flcrmon;
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unsigned int reserved5[944];
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unsigned int spibootcan;
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};
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#define GCTRL_BASE ((struct gctrl_regs *)0xffc10000)
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/* PCIe setup */
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struct pcie_setup_regs {
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unsigned int pbictl0;
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unsigned int gradevctl;
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unsigned int reserved[2];
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unsigned int bmcinf[6];
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unsigned int reserved2[118];
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unsigned int idset[2];
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unsigned int subidset;
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unsigned int reserved3[2];
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unsigned int linkconfset[4];
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unsigned int trsid;
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unsigned int reserved4[6];
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unsigned int toutset;
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unsigned int reserved5[7];
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unsigned int lad0;
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unsigned int ladmsk0;
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unsigned int lad1;
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unsigned int ladmsk1;
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unsigned int lad2;
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unsigned int ladmsk2;
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unsigned int lad3;
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unsigned int ladmsk3;
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unsigned int lad4;
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unsigned int ladmsk4;
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unsigned int lad5;
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unsigned int ladmsk5;
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unsigned int reserved6[94];
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unsigned int vdmrxvid[2];
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unsigned int reserved7;
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unsigned int pbiintfr;
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unsigned int pbiinten;
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unsigned int msimap;
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unsigned int barmap;
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unsigned int baracsize;
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unsigned int advserest;
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unsigned int pbictl3;
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unsigned int reserved8[8];
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unsigned int pbictl1;
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unsigned int scratch0;
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unsigned int reserved9[6];
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unsigned int pbictl2;
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unsigned int reserved10;
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unsigned int pbirev;
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};
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#define PCIE_SETUP_BASE ((struct pcie_setup_regs *)0xffca1000)
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struct pcie_system_bus_regs {
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unsigned int reserved[3];
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unsigned int endictl0;
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unsigned int endictl1;
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};
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#define PCIE_SYSTEM_BUS_BASE ((struct pcie_system_bus_regs *)0xffca1600)
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/* PCIe-Bridge */
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struct pciebrg_regs {
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unsigned short ctrl_h8s;
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unsigned short reserved[7];
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unsigned short cp_addr;
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unsigned short reserved2;
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unsigned short cp_data;
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unsigned short reserved3;
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unsigned short cp_ctrl;
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};
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#define PCIEBRG_BASE ((struct pciebrg_regs *)0xffd60000)
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/* CPU version */
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#define CCN_PRR 0xff000044
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#define prr_mask(_val) ((_val >> 4) & 0xff)
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#define PRR_SH7757_B0 0x10
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#define PRR_SH7757_C0 0x11
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#define is_sh7757_b0(_val) \
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({ \
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int __ret = prr_mask(__raw_readl(CCN_PRR)) == PRR_SH7757_B0; \
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__ret; \
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})
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#endif /* ifndef __ASSEMBLY__ */
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#endif /* _ASM_CPU_SH7757_H_ */
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