upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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237 lines
7.4 KiB
237 lines
7.4 KiB
18 years ago
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/*
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* (C) Copyright 2007
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* Stefan Roese, DENX Software Engineering, sr@denx.de.
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include <config.h>
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#include <common.h>
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#include <command.h>
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#include <asm/processor.h>
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#include <pci.h>
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void show_reset_reg(void)
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{
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unsigned long reg;
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/* read clock regsiter */
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printf("===== Display reset and initialize register Start =========\n");
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mfclk(clk_pllc,reg);
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printf("cpr_pllc = %#010x\n",reg);
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mfclk(clk_plld,reg);
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printf("cpr_plld = %#010x\n",reg);
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mfclk(clk_primad,reg);
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printf("cpr_primad = %#010x\n",reg);
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mfclk(clk_primbd,reg);
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printf("cpr_primbd = %#010x\n",reg);
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mfclk(clk_opbd,reg);
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printf("cpr_opbd = %#010x\n",reg);
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mfclk(clk_perd,reg);
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printf("cpr_perd = %#010x\n",reg);
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mfclk(clk_mald,reg);
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printf("cpr_mald = %#010x\n",reg);
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/* read sdr register */
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mfsdr(sdr_ebc,reg);
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printf("sdr_ebc = %#010x\n",reg);
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mfsdr(sdr_cp440,reg);
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printf("sdr_cp440 = %#010x\n",reg);
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mfsdr(sdr_xcr,reg);
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printf("sdr_xcr = %#010x\n",reg);
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mfsdr(sdr_xpllc,reg);
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printf("sdr_xpllc = %#010x\n",reg);
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mfsdr(sdr_xplld,reg);
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printf("sdr_xplld = %#010x\n",reg);
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mfsdr(sdr_pfc0,reg);
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printf("sdr_pfc0 = %#010x\n",reg);
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mfsdr(sdr_pfc1,reg);
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printf("sdr_pfc1 = %#010x\n",reg);
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mfsdr(sdr_cust0,reg);
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printf("sdr_cust0 = %#010x\n",reg);
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mfsdr(sdr_cust1,reg);
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printf("sdr_cust1 = %#010x\n",reg);
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mfsdr(sdr_uart0,reg);
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printf("sdr_uart0 = %#010x\n",reg);
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mfsdr(sdr_uart1,reg);
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printf("sdr_uart1 = %#010x\n",reg);
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printf("===== Display reset and initialize register End =========\n");
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}
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void show_xbridge_info(void)
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{
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unsigned long reg;
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printf("PCI-X chip control registers\n");
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mfsdr(sdr_xcr, reg);
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printf("sdr_xcr = %#010x\n", reg);
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mfsdr(sdr_xpllc, reg);
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printf("sdr_xpllc = %#010x\n", reg);
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mfsdr(sdr_xplld, reg);
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printf("sdr_xplld = %#010x\n", reg);
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printf("PCI-X Bridge Configure registers\n");
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printf("PCIX0_VENDID = %#06x\n", in16r(PCIX0_VENDID));
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printf("PCIX0_DEVID = %#06x\n", in16r(PCIX0_DEVID));
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printf("PCIX0_CMD = %#06x\n", in16r(PCIX0_CMD));
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printf("PCIX0_STATUS = %#06x\n", in16r(PCIX0_STATUS));
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printf("PCIX0_REVID = %#04x\n", in8(PCIX0_REVID));
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printf("PCIX0_CACHELS = %#04x\n", in8(PCIX0_CACHELS));
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printf("PCIX0_LATTIM = %#04x\n", in8(PCIX0_LATTIM));
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printf("PCIX0_HDTYPE = %#04x\n", in8(PCIX0_HDTYPE));
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printf("PCIX0_BIST = %#04x\n", in8(PCIX0_BIST));
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printf("PCIX0_BAR0 = %#010x\n", in32r(PCIX0_BAR0));
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printf("PCIX0_BAR1 = %#010x\n", in32r(PCIX0_BAR1));
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printf("PCIX0_BAR2 = %#010x\n", in32r(PCIX0_BAR2));
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printf("PCIX0_BAR3 = %#010x\n", in32r(PCIX0_BAR3));
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printf("PCIX0_BAR4 = %#010x\n", in32r(PCIX0_BAR4));
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printf("PCIX0_BAR5 = %#010x\n", in32r(PCIX0_BAR5));
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printf("PCIX0_CISPTR = %#010x\n", in32r(PCIX0_CISPTR));
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printf("PCIX0_SBSSYSVID = %#010x\n", in16r(PCIX0_SBSYSVID));
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printf("PCIX0_SBSSYSID = %#010x\n", in16r(PCIX0_SBSYSID));
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printf("PCIX0_EROMBA = %#010x\n", in32r(PCIX0_EROMBA));
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printf("PCIX0_CAP = %#04x\n", in8(PCIX0_CAP));
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printf("PCIX0_INTLN = %#04x\n", in8(PCIX0_INTLN));
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printf("PCIX0_INTPN = %#04x\n", in8(PCIX0_INTPN));
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printf("PCIX0_MINGNT = %#04x\n", in8(PCIX0_MINGNT));
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printf("PCIX0_MAXLTNCY = %#04x\n", in8(PCIX0_MAXLTNCY));
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printf("PCIX0_BRDGOPT1 = %#010x\n", in32r(PCIX0_BRDGOPT1));
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printf("PCIX0_BRDGOPT2 = %#010x\n", in32r(PCIX0_BRDGOPT2));
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printf("PCIX0_POM0LAL = %#010x\n", in32r(PCIX0_POM0LAL));
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printf("PCIX0_POM0LAH = %#010x\n", in32r(PCIX0_POM0LAH));
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printf("PCIX0_POM0SA = %#010x\n", in32r(PCIX0_POM0SA));
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printf("PCIX0_POM0PCILAL = %#010x\n", in32r(PCIX0_POM0PCIAL));
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printf("PCIX0_POM0PCILAH = %#010x\n", in32r(PCIX0_POM0PCIAH));
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printf("PCIX0_POM1LAL = %#010x\n", in32r(PCIX0_POM1LAL));
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printf("PCIX0_POM1LAH = %#010x\n", in32r(PCIX0_POM1LAH));
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printf("PCIX0_POM1SA = %#010x\n", in32r(PCIX0_POM1SA));
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printf("PCIX0_POM1PCILAL = %#010x\n", in32r(PCIX0_POM1PCIAL));
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printf("PCIX0_POM1PCILAH = %#010x\n", in32r(PCIX0_POM1PCIAH));
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printf("PCIX0_POM2SA = %#010x\n", in32r(PCIX0_POM2SA));
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printf("PCIX0_PIM0SA = %#010x\n", in32r(PCIX0_PIM0SA));
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printf("PCIX0_PIM0LAL = %#010x\n", in32r(PCIX0_PIM0LAL));
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printf("PCIX0_PIM0LAH = %#010x\n", in32r(PCIX0_PIM0LAH));
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printf("PCIX0_PIM1SA = %#010x\n", in32r(PCIX0_PIM1SA));
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printf("PCIX0_PIM1LAL = %#010x\n", in32r(PCIX0_PIM1LAL));
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printf("PCIX0_PIM1LAH = %#010x\n", in32r(PCIX0_PIM1LAH));
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printf("PCIX0_PIM2SA = %#010x\n", in32r(PCIX0_PIM1SA));
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printf("PCIX0_PIM2LAL = %#010x\n", in32r(PCIX0_PIM1LAL));
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printf("PCIX0_PIM2LAH = %#010x\n", in32r(PCIX0_PIM1LAH));
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printf("PCIX0_XSTS = %#010x\n", in32r(PCIX0_STS));
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}
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int do_show_xbridge_info(cmd_tbl_t * cmdtp, int flag, int argc, char *argv[])
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{
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show_xbridge_info();
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return 0;
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}
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U_BOOT_CMD(xbriinfo, 1, 1, do_show_xbridge_info,
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"xbriinfo - Show PCIX bridge info\n", NULL);
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#define TAISHAN_PCI_DEV_ID0 0x800
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#define TAISHAN_PCI_DEV_ID1 0x1000
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void show_pcix_device_info(void)
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{
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int ii;
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int dev;
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u8 capp;
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u8 xcapid;
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u16 status;
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u16 xcommand;
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u32 xstatus;
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for (ii = 0; ii < 2; ii++) {
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if (ii == 0)
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dev = TAISHAN_PCI_DEV_ID0;
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else
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dev = TAISHAN_PCI_DEV_ID1;
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pci_read_config_word(dev, PCI_STATUS, &status);
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if (status & PCI_STATUS_CAP_LIST) {
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pci_read_config_byte(dev, PCI_CAPABILITY_LIST, &capp);
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pci_read_config_byte(dev, (int)(capp), &xcapid);
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if (xcapid == 0x07) {
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pci_read_config_word(dev, (int)(capp + 2),
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&xcommand);
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pci_read_config_dword(dev, (int)(capp + 4),
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&xstatus);
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printf("BUS0 dev%d Xcommand=%#06x,Xstatus=%#010x\n",
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(ii + 1), xcommand, xstatus);
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} else {
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printf("BUS0 dev%d PCI-X CAP ID error,"
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"CAP=%#04x,XCAPID=%#04x\n",
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(ii + 1), capp, xcapid);
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}
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} else {
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printf("BUS0 dev%d not found PCI_STATUS_CAP_LIST supporting\n",
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ii + 1);
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}
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}
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}
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int do_show_pcix_device_info(cmd_tbl_t * cmdtp, int flag, int argc,
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char *argv[])
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{
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show_pcix_device_info();
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return 0;
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}
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U_BOOT_CMD(xdevinfo, 1, 1, do_show_pcix_device_info,
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"xdevinfo - Show PCIX Device info\n", NULL);
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extern void show_reset_reg(void);
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int do_show_reset_reg_info(cmd_tbl_t * cmdtp, int flag, int argc, char *argv[])
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{
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show_reset_reg();
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return 0;
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}
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U_BOOT_CMD(resetinfo, 1, 1, do_show_reset_reg_info,
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"resetinfo - Show Reset REG info\n", NULL);
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