upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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60 lines
1.8 KiB
60 lines
1.8 KiB
14 years ago
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Matrix Vision MergerBox
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1. Board Description
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The MergerBox is a 120x160mm single board computing platform
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for 3D Full-HD digital video processing.
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Power Supply is 10-32VDC.
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2 System Components
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2.1 CPU
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Freescale MPC8377 CPU running at 800MHz core and 333MHz csb.
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256 MByte DDR-II memory @ 333MHz data rate.
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64 MByte Nor Flash on local bus.
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1 GByte Nand Flash on FCM.
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1 Vitesse VSC8601 RGMII ethernet Phys.
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1 USB host controller over ULPI I/F with 4-Port hub.
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2 serial ports. Console running on ttyS0 @ 115200 8N1.
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1 mPCIe expansion slot (PCIe x1 + USB) used for Wifi/Bt.
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2 PCIe x1 busses on local mPCIe and cutom expansion connector.
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2 SATA host ports.
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System configuration (HRCW) is taken from I2C EEPROM.
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2.2 Graphics
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SM107 emebedded video controller driving a 5" 800x480 TFT panel.
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Connected over 32-Bit/66MHz PCI utilizing 4 MByte embedded memory.
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2.3 FPGA
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Altera Cyclone-IV EP4C115 with several PCI DMA engines.
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Connects to 7x Gennum 3G-SDI transceivers as video interconnect
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as well as a HDMI v1.4 compliant output for 3D monitoring.
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Utilizes two more DDR-II controllers providing 256MB memory.
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2.4 I2C
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Bus1:
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AD7418 @ 0x50 for voltage/temp. monitoring.
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SX8650 @ 0x90 touch controller for HMI.
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EEPROM @ 0xA0 for system setup (HRCW etc.) + vendor specifics.
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Bus2:
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mPCIe SMBus
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SiI9022A @ 0x72/0xC0 HDMI transmitter.
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TCA6416A @ 0x40 + 0x42 16-Bit I/O expander.
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LMH1983 @ 0xCA video PLL.
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DS1338C @ 0xD0 real-time clock with embedded crystal.
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9FG104 @ 0xDC 4x 100MHz LVDS SerDes reference clock.
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3 Flash layout.
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reset vector is 0x00000100, i.e. low boot.
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00000000 u-boot binary.
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00100000 FPGA raw bit file.
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00300000 FIT image holding kernel, dtb and rescue squashfs.
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03d00000 u-boot environment.
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03e00000 splash image
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mtd partitions are propagated to linux kernel via device tree blob.
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