upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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58 lines
1.7 KiB
58 lines
1.7 KiB
17 years ago
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Notes for the MIPS architecture port of U-Boot
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Toolchains
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http://www.denx.de/wiki/DULG/ELDK
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ELDK < DULG < DENX
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http://www.emdebian.org/crosstools.html
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Embedded Debian -- Cross-development toolchains
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http://buildroot.uclibc.org/
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Buildroot
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Known Issues
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------------
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* Little endian build problem
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If use non-ELDK toolchains, -EB will be set to CPPFLAGS. Therefore all
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objects will be generated in big-endian format.
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* Cache incoherency issue caused by do_bootelf_exec() at cmd_elf.c
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Cache will be disabled before entering the loaded ELF image without
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writing back and invalidating cache lines. This leads to cache
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incoherency in most cases, unless the code gets loaded after U-Boot
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re-initializes the cache. The more common uImage 'bootm' command does
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not suffer this problem.
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[workaround] To avoid this cache incoherency,
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1) insert flush_cache(all) before calling dcache_disable(), or
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2) fix dcache_disable() to do both flushing and disabling cache.
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* Note that Linux users need to kill dcache_disable() in do_bootelf_exec()
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or override do_bootelf_exec() not to disable I-/D-caches, because most
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Linux/MIPS ports don't re-enable caches after entering kernel_entry.
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TODOs
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-----
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* Probe CPU types, I-/D-cache and TLB size etc. automatically
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* Secondary cache support missing
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* Centralize the link directive files
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* Initialize TLB entries redardless of their use
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* R2000/R3000 class parts are not supported
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* Limited testing across different MIPS variants
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* Due to cache initialization issues, the DRAM on board must be
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initialized in board specific assembler language before the cache init
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code is run -- that is, initialize the DRAM in lowlevel_init().
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