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Matrix Vision mvSMR
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1. Board Description
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The mvSMR is a 75x130mm single image processing board used
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in automation. Power Supply is 24VDC.
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2 System Components
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2.1 CPU
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Freescale MPC5200B CPU running at 400MHz core and 133MHz XLB/IPB.
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64MB DDR-I @ 133MHz.
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8 MByte Nor Flash on local bus.
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2 serial ports. Console running on ttyS0 @ 115200 8N1.
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2.2 PCI
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PCI clock fixed at 33MHz due to old'n'slow Xilinx PCI core.
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2.3 FPGA
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Xilinx Spartan-3 XC3S200 with PCI DMA engine.
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Connects to Matrix Vision specific CCD/CMOS sensor interface.
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2.4 I2C
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EEPROM @ 0xA0 for vendor specifics.
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image sensor interface (slave addresses depend on sensor)
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3 Flash layout.
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reset vector is 0x00000100, i.e. "LOWBOOT".
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FF800000 u-boot
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FF806000 u-boot script image
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FF808000 u-boot environment
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FF840000 FPGA raw bit file
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FF880000 root FS
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FFF00000 kernel
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4 Booting
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On startup the bootscript @ FF806000 is executed. This script can be
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exchanged easily. Default boot mode is "boot from flash", i.e. system
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works stand-alone.
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This behaviour depends on some environment variables :
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"netboot" : yes ->try dhcp/bootp and boot from network.
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A "dhcp_client_id" and "dhcp_vendor-class-identifier" can be used for
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DHCP server configuration, e.g. to provide different images to
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different devices.
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During netboot the system tries to get 3 image files:
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1. Kernel - name + data is given during BOOTP.
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2. Initrd - name is stored in "initrd_name"
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Fallback files are the flash versions.
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