upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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183 lines
5.8 KiB
183 lines
5.8 KiB
21 years ago
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/* * include/asm-armnommu/arch-netarm/netarm_dma_module.h
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21 years ago
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*
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* Copyright (C) 2000 NETsilicon, Inc.
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* Copyright (C) 2000 WireSpeed Communications Corporation
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*
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* This software is copyrighted by WireSpeed. LICENSEE agrees that
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* it will not delete this copyright notice, trademarks or protective
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* notices from any copy made by LICENSEE.
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*
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* This software is provided "AS-IS" and any express or implied
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* warranties or conditions, including but not limited to any
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* implied warranties of merchantability and fitness for a particular
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* purpose regarding this software. In no event shall WireSpeed
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* be liable for any indirect, consequential, or incidental damages,
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* loss of profits or revenue, loss of use or data, or interruption
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* of business, whether the alleged damages are labeled in contract,
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* tort, or indemnity.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
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*
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* author(s) : Joe deBlaquiere
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* David Smith
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*/
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#ifndef __NETARM_DMA_MODULE_REGISTERS_H
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#define __NETARM_DMA_MODULE_REGISTERS_H
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/* GEN unit register offsets */
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#define NETARM_DMA_MODULE_BASE (0xFF900000)
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#define get_dma_reg_addr(c) ((volatile unsigned int *)(NETARM_DMA_MODULE_BASE + (c)))
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#define NETARM_DMA1A_BFR_DESCRPTOR_PTR (0x00)
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#define NETARM_DMA1A_CONTROL (0x10)
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#define NETARM_DMA1A_STATUS (0x14)
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#define NETARM_DMA1B_BFR_DESCRPTOR_PTR (0x20)
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#define NETARM_DMA1B_CONTROL (0x30)
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#define NETARM_DMA1B_STATUS (0x34)
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#define NETARM_DMA1C_BFR_DESCRPTOR_PTR (0x40)
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#define NETARM_DMA1C_CONTROL (0x50)
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#define NETARM_DMA1C_STATUS (0x54)
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#define NETARM_DMA1D_BFR_DESCRPTOR_PTR (0x60)
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#define NETARM_DMA1D_CONTROL (0x70)
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#define NETARM_DMA1D_STATUS (0x74)
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#define NETARM_DMA2_BFR_DESCRPTOR_PTR (0x80)
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#define NETARM_DMA2_CONTROL (0x90)
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#define NETARM_DMA2_STATUS (0x94)
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#define NETARM_DMA3_BFR_DESCRPTOR_PTR (0xA0)
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#define NETARM_DMA3_CONTROL (0xB0)
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#define NETARM_DMA3_STATUS (0xB4)
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#define NETARM_DMA4_BFR_DESCRPTOR_PTR (0xC0)
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#define NETARM_DMA4_CONTROL (0xD0)
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#define NETARM_DMA4_STATUS (0xD4)
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#define NETARM_DMA5_BFR_DESCRPTOR_PTR (0xE0)
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#define NETARM_DMA5_CONTROL (0xF0)
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#define NETARM_DMA5_STATUS (0xF4)
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#define NETARM_DMA6_BFR_DESCRPTOR_PTR (0x100)
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#define NETARM_DMA6_CONTROL (0x110)
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#define NETARM_DMA6_STATUS (0x114)
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#define NETARM_DMA7_BFR_DESCRPTOR_PTR (0x120)
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#define NETARM_DMA7_CONTROL (0x130)
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#define NETARM_DMA7_STATUS (0x134)
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#define NETARM_DMA8_BFR_DESCRPTOR_PTR (0x140)
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#define NETARM_DMA8_CONTROL (0x150)
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#define NETARM_DMA8_STATUS (0x154)
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#define NETARM_DMA9_BFR_DESCRPTOR_PTR (0x160)
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#define NETARM_DMA9_CONTROL (0x170)
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#define NETARM_DMA9_STATUS (0x174)
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#define NETARM_DMA10_BFR_DESCRPTOR_PTR (0x180)
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#define NETARM_DMA10_CONTROL (0x190)
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#define NETARM_DMA10_STATUS (0x194)
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/* select bitfield defintions */
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/* DMA Control Register ( 0xFF90_0XX0 ) */
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#define NETARM_DMA_CTL_ENABLE (0x80000000)
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#define NETARM_DMA_CTL_ABORT (0x40000000)
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#define NETARM_DMA_CTL_BUS_100_PERCENT (0x00000000)
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#define NETARM_DMA_CTL_BUS_75_PERCENT (0x10000000)
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#define NETARM_DMA_CTL_BUS_50_PERCENT (0x20000000)
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#define NETARM_DMA_CTL_BUS_25_PERCENT (0x30000000)
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#define NETARM_DMA_CTL_BUS_MASK (0x30000000)
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#define NETARM_DMA_CTL_MODE_FB_TO_MEM (0x00000000)
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#define NETARM_DMA_CTL_MODE_FB_FROM_MEM (0x04000000)
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#define NETARM_DMA_CTL_MODE_MEM_TO_MEM (0x08000000)
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#define NETARM_DMA_CTL_BURST_NONE (0x00000000)
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#define NETARM_DMA_CTL_BURST_8_BYTE (0x01000000)
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#define NETARM_DMA_CTL_BURST_16_BYTE (0x02000000)
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#define NETARM_DMA_CTL_BURST_MASK (0x03000000)
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#define NETARM_DMA_CTL_SRC_INCREMENT (0x00200000)
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#define NETARM_DMA_CTL_DST_INCREMENT (0x00100000)
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/* these apply only to ext xfers on DMA 3 or 4 */
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#define NETARM_DMA_CTL_CH_3_4_REQ_EXT (0x00800000)
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#define NETARM_DMA_CTL_CH_3_4_DATA_32 (0x00000000)
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#define NETARM_DMA_CTL_CH_3_4_DATA_16 (0x00010000)
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#define NETARM_DMA_CTL_CH_3_4_DATA_8 (0x00020000)
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#define NETARM_DMA_CTL_STATE(X) ((X) & 0xFC00)
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#define NETARM_DMA_CTL_INDEX(X) ((X) & 0x03FF)
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/* DMA Status Register ( 0xFF90_0XX4 ) */
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#define NETARM_DMA_STAT_NC_INTPEN (0x80000000)
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#define NETARM_DMA_STAT_EC_INTPEN (0x40000000)
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#define NETARM_DMA_STAT_NR_INTPEN (0x20000000)
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#define NETARM_DMA_STAT_CA_INTPEN (0x10000000)
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#define NETARM_DMA_STAT_INTPEN_MASK (0xF0000000)
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#define NETARM_DMA_STAT_NC_INT_EN (0x00800000)
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#define NETARM_DMA_STAT_EC_INT_EN (0x00400000)
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#define NETARM_DMA_STAT_NR_INT_EN (0x00200000)
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#define NETARM_DMA_STAT_CA_INT_EN (0x00100000)
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#define NETARM_DMA_STAT_INT_EN_MASK (0x00F00000)
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#define NETARM_DMA_STAT_WRAP (0x00080000)
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#define NETARM_DMA_STAT_IDONE (0x00040000)
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#define NETARM_DMA_STAT_LAST (0x00020000)
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#define NETARM_DMA_STAT_FULL (0x00010000)
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#define NETARM_DMA_STAT_BUFLEN(X) ((X) & 0x7FFF)
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/* DMA Buffer Descriptor Word 0 bitfields. */
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#define NETARM_DMA_BD0_WRAP (0x80000000)
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#define NETARM_DMA_BD0_IDONE (0x40000000)
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#define NETARM_DMA_BD0_LAST (0x20000000)
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#define NETARM_DMA_BD0_BUFPTR_MASK (0x1FFFFFFF)
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/* DMA Buffer Descriptor Word 1 bitfields. */
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#define NETARM_DMA_BD1_STATUS_MASK (0xFFFF0000)
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#define NETARM_DMA_BD1_FULL (0x00008000)
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#define NETARM_DMA_BD1_BUFLEN_MASK (0x00007FFF)
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#ifndef __ASSEMBLER__
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typedef struct __NETARM_DMA_Buff_Desc_FlyBy
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{
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unsigned int word0;
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unsigned int word1;
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} NETARM_DMA_Buff_Desc_FlyBy, *pNETARM_DMA_Buff_Desc_FlyBy ;
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typedef struct __NETARM_DMA_Buff_Desc_M_to_M
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{
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unsigned int word0;
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unsigned int word1;
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unsigned int word2;
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unsigned int word3;
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} NETARM_DMA_Buff_Desc_M_to_M, *pNETARM_DMA_Buff_Desc_M_to_M ;
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#endif
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#endif
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