upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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78 lines
3.1 KiB
78 lines
3.1 KiB
17 years ago
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/*
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* TWI Masks
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*/
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#ifndef __BFIN_PERIPHERAL_TWI__
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#define __BFIN_PERIPHERAL_TWI__
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/* TWI_CLKDIV Macros (Use: *pTWI_CLKDIV = CLKLOW(x)|CLKHI(y); ) */
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#define CLKLOW(x) ((x) & 0xFF) /* Periods Clock Is Held Low */
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#define CLKHI(y) (((y)&0xFF)<<0x8) /* Periods Before New Clock Low */
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/* TWI_PRESCALE Masks */
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#define PRESCALE 0x007F /* SCLKs Per Internal Time Reference (10MHz) */
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#define TWI_ENA 0x0080 /* TWI Enable */
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#define SCCB 0x0200 /* SCCB Compatibility Enable */
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/* TWI_SLAVE_CTL Masks */
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#define SEN 0x0001 /* Slave Enable */
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#define SADD_LEN 0x0002 /* Slave Address Length */
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#define STDVAL 0x0004 /* Slave Transmit Data Valid */
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#define TSC_NAK 0x0008 /* NAK/ACK* Generated At Conclusion Of Transfer */
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#define GEN 0x0010 /* General Call Adrress Matching Enabled */
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/* TWI_SLAVE_STAT Masks */
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#define SDIR 0x0001 /* Slave Transfer Direction (Transmit/Receive*) */
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#define GCALL 0x0002 /* General Call Indicator */
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/* TWI_MASTER_CTRL Masks */
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#define MEN 0x0001 /* Master Mode Enable */
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#define MADD_LEN 0x0002 /* Master Address Length */
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#define MDIR 0x0004 /* Master Transmit Direction (RX/TX*) */
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#define FAST 0x0008 /* Use Fast Mode Timing Specs */
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#define STOP 0x0010 /* Issue Stop Condition */
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#define RSTART 0x0020 /* Repeat Start or Stop* At End Of Transfer */
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#define DCNT 0x3FC0 /* Data Bytes To Transfer */
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#define SDAOVR 0x4000 /* Serial Data Override */
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#define SCLOVR 0x8000 /* Serial Clock Override */
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/* TWI_MASTER_STAT Masks */
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#define MPROG 0x0001 /* Master Transfer In Progress */
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#define LOSTARB 0x0002 /* Lost Arbitration Indicator (Xfer Aborted) */
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#define ANAK 0x0004 /* Address Not Acknowledged */
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#define DNAK 0x0008 /* Data Not Acknowledged */
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#define BUFRDERR 0x0010 /* Buffer Read Error */
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#define BUFWRERR 0x0020 /* Buffer Write Error */
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#define SDASEN 0x0040 /* Serial Data Sense */
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#define SCLSEN 0x0080 /* Serial Clock Sense */
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#define BUSBUSY 0x0100 /* Bus Busy Indicator */
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/* TWI_INT_SRC and TWI_INT_ENABLE Masks */
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#define SINIT 0x0001 /* Slave Transfer Initiated */
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#define SCOMP 0x0002 /* Slave Transfer Complete */
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#define SERR 0x0004 /* Slave Transfer Error */
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#define SOVF 0x0008 /* Slave Overflow */
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#define MCOMP 0x0010 /* Master Transfer Complete */
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#define MERR 0x0020 /* Master Transfer Error */
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#define XMTSERV 0x0040 /* Transmit FIFO Service */
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#define RCVSERV 0x0080 /* Receive FIFO Service */
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/* TWI_FIFO_CTRL Masks */
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#define XMTFLUSH 0x0001 /* Transmit Buffer Flush */
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#define RCVFLUSH 0x0002 /* Receive Buffer Flush */
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#define XMTINTLEN 0x0004 /* Transmit Buffer Interrupt Length */
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#define RCVINTLEN 0x0008 /* Receive Buffer Interrupt Length */
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/* TWI_FIFO_STAT Masks */
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#define XMTSTAT 0x0003 /* Transmit FIFO Status */
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#define XMT_EMPTY 0x0000 /* Transmit FIFO Empty */
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#define XMT_HALF 0x0001 /* Transmit FIFO Has 1 Byte To Write */
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#define XMT_FULL 0x0003 /* Transmit FIFO Full (2 Bytes To Write) */
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#define RCVSTAT 0x000C /* Receive FIFO Status */
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#define RCV_EMPTY 0x0000 /* Receive FIFO Empty */
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#define RCV_HALF 0x0004 /* Receive FIFO Has 1 Byte To Read */
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#define RCV_FULL 0x000C /* Receive FIFO Full (2 Bytes To Read) */
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#endif
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