upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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166 lines
5.4 KiB
166 lines
5.4 KiB
21 years ago
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/*
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* Copyright (C) 2002,2003, Motorola Inc.
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* Xianghua Xiao <X.Xiao@motorola.com>
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*
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* (C) Copyright 2004 Wind River Systems Inc <www.windriver.com>.
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* Added support for Wind River SBC8560 board
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include <ppc_asm.tmpl>
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#include <ppc_defs.h>
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#include <asm/cache.h>
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#include <asm/mmu.h>
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#include <config.h>
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#include <mpc85xx.h>
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#define entry_start \
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mflr r1 ; \
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bl 0f ;
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#define entry_end \
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0: mflr r0 ; \
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mtlr r1 ; \
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blr ;
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/* LAW(Local Access Window) configuration:
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* 0000_0000-0800_0000: DDR(512M) -or- larger
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* c000_0000-cfff_ffff: PCI(256M)
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* d000_0000-dfff_ffff: RapidIO(256M)
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* e000_0000-ffff_ffff: localbus(512M)
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* e000_0000-e3ff_ffff: LBC 64M, 32-bit flash on CS6
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* e400_0000-e7ff_ffff: LBC 64M, 32-bit flash on CS1
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* e800_0000-efff_ffff: LBC 128M, nothing here
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* f000_0000-f3ff_ffff: LBC 64M, SDRAM on CS3
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* f400_0000-f7ff_ffff: LBC 64M, SDRAM on CS4
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* f800_0000-fdff_ffff: LBC 64M, nothing here
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* fc00_0000-fcff_ffff: LBC 16M, CSR,RTC,UART,etc on CS5
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* fd00_0000-fdff_ffff: LBC 16M, nothing here
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* fe00_0000-feff_ffff: LBC 16M, nothing here
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* ff00_0000-ff6f_ffff: LBC 7M, nothing here
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* ff70_0000-ff7f_ffff: CCSRBAR 1M
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* ff80_0000-ffff_ffff: LBC 8M, 8-bit flash on CS0
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* Note: CCSRBAR and L2-as-SRAM don't need configure Local Access
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* Window.
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* Note: If flash is 8M at default position(last 8M),no LAW needed.
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*/
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#if !defined(CONFIG_SPD_EEPROM)
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#define LAWBAR0 ((CFG_DDR_SDRAM_BASE>>12) & 0xfffff)
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#define LAWAR0 (LAWAR_EN | LAWAR_TRGT_IF_DDR | (LAWAR_SIZE & LAWAR_SIZE_512M))
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#else
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#define LAWBAR0 0
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#define LAWAR0 ((LAWAR_TRGT_IF_DDR | (LAWAR_SIZE & LAWAR_SIZE_512M)) & ~LAWAR_EN)
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#endif
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#define LAWBAR1 ((CFG_PCI_MEM_BASE>>12) & 0xfffff)
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#define LAWAR1 (LAWAR_EN | LAWAR_TRGT_IF_PCIX | (LAWAR_SIZE & LAWAR_SIZE_256M))
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#define LAWBAR2 ((0xe0000000>>12) & 0xfffff)
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#define LAWAR2 (LAWAR_EN | LAWAR_TRGT_IF_LBC | (LAWAR_SIZE & LAWAR_SIZE_512M))
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.section .bootpg, "ax"
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.globl law_entry
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law_entry:
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entry_start
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.long 0x03
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.long LAWBAR0,LAWAR0,LAWBAR1,LAWAR1,LAWBAR2,LAWAR2
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entry_end
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/* TLB1 entries configuration: */
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.section .bootpg, "ax"
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.globl tlb1_entry
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tlb1_entry:
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entry_start
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.long 0x08 /* the following data table uses a few of 16 TLB entries */
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/* TLB for CCSRBAR (IMMR) */
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.long TLB1_MAS0(1,1,0)
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.long TLB1_MAS1(1,1,0,0,BOOKE_PAGESZ_1M)
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.long TLB1_MAS2(((CFG_CCSRBAR>>12) & 0xfffff),0,0,0,0,1,0,1,0)
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.long TLB1_MAS3(((CFG_CCSRBAR>>12) & 0xfffff),0,0,0,0,0,1,0,1,0,1)
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/* TLB for Local Bus stuff, just map the whole 512M */
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/* note that the LBC SDRAM is cache-inhibit and guarded, like everything else */
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.long TLB1_MAS0(1,2,0)
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.long TLB1_MAS1(1,1,0,0,BOOKE_PAGESZ_256M)
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.long TLB1_MAS2(((0xe0000000>>12) & 0xfffff),0,0,0,0,1,0,1,0)
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.long TLB1_MAS3(((0xe0000000>>12) & 0xfffff),0,0,0,0,0,1,0,1,0,1)
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.long TLB1_MAS0(1,3,0)
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.long TLB1_MAS1(1,1,0,0,BOOKE_PAGESZ_256M)
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.long TLB1_MAS2(((0xf0000000>>12)&0xfffff),0,0,0,0,1,0,1,0)
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.long TLB1_MAS3(((0xf0000000>>12)&0xfffff),0,0,0,0,0,1,0,1,0,1)
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#if !defined(CONFIG_SPD_EEPROM)
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.long TLB1_MAS0(1,4,0)
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.long TLB1_MAS1(1,1,0,0,BOOKE_PAGESZ_256M)
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.long TLB1_MAS2(((CFG_DDR_SDRAM_BASE>>12) & 0xfffff),0,0,0,0,0,0,0,0)
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.long TLB1_MAS3(((CFG_DDR_SDRAM_BASE>>12) & 0xfffff),0,0,0,0,0,1,0,1,0,1)
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.long TLB1_MAS0(1,5,0)
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.long TLB1_MAS1(1,1,0,0,BOOKE_PAGESZ_256M)
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.long TLB1_MAS2((((CFG_DDR_SDRAM_BASE+0x10000000)>>12) & 0xfffff),0,0,0,0,0,0,0,0)
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.long TLB1_MAS3((((CFG_DDR_SDRAM_BASE+0x10000000)>>12) & 0xfffff),0,0,0,0,0,1,0,1,0,1)
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#else
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.long TLB1_MAS0(1,4,0)
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.long TLB1_MAS1(0,0,0,0,BOOKE_PAGESZ_1M)
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.long TLB1_MAS2(0,0,0,0,0,0,0,0,0)
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.long TLB1_MAS3(0,0,0,0,0,0,1,0,1,0,1)
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.long TLB1_MAS0(1,5,0)
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.long TLB1_MAS1(0,0,0,0,BOOKE_PAGESZ_1M)
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.long TLB1_MAS2(0,0,0,0,0,0,0,0,0)
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.long TLB1_MAS3(0,0,0,0,0,0,1,0,1,0,1)
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#endif
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.long TLB1_MAS0(1,6,0)
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.long TLB1_MAS1(1,1,0,0,BOOKE_PAGESZ_16K)
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#ifdef CONFIG_L2_INIT_RAM
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.long TLB1_MAS2(((CFG_INIT_RAM_ADDR>>12) & 0xfffff),0,0,0,1,0,0,0,0)
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#else
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.long TLB1_MAS2(((CFG_INIT_RAM_ADDR>>12) & 0xfffff),0,0,0,0,0,0,0,0)
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#endif
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.long TLB1_MAS3(((CFG_INIT_RAM_ADDR>>12) & 0xfffff),0,0,0,0,0,1,0,1,0,1)
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.long TLB1_MAS0(1,7,0)
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.long TLB1_MAS1(1,1,0,0,BOOKE_PAGESZ_256M)
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.long TLB1_MAS2(((CFG_PCI_MEM_BASE>>12) & 0xfffff),0,0,0,0,1,0,1,0)
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.long TLB1_MAS3(((CFG_PCI_MEM_BASE>>12) & 0xfffff),0,0,0,0,0,1,0,1,0,1)
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#if (CFG_CCSRBAR_DEFAULT != CFG_CCSRBAR)
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.long TLB1_MAS0(1,15,0)
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.long TLB1_MAS1(1,1,0,0,BOOKE_PAGESZ_1M)
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.long TLB1_MAS2(((CFG_CCSRBAR_DEFAULT>>12) & 0xfffff),0,0,0,0,1,0,1,0)
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.long TLB1_MAS3(((CFG_CCSRBAR_DEFAULT>>12) & 0xfffff),0,0,0,0,0,1,0,1,0,1)
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#else
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.long TLB1_MAS0(1,15,0)
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.long TLB1_MAS1(0,0,0,0,BOOKE_PAGESZ_1M)
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.long TLB1_MAS2(0,0,0,0,0,0,0,0,0)
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.long TLB1_MAS3(0,0,0,0,0,0,1,0,1,0,1)
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#endif
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entry_end
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