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#ifndef _ASM_CPU_SH7710_H_
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#define _ASM_CPU_SH7710_H_
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#define CACHE_OC_NUM_WAYS 4
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#define CCR_CACHE_INIT 0x0000000D
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/* MMU and Cache control */
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#define MMUCR 0xFFFFFFE0
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#define CCR 0xFFFFFFEC
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/* PFC */
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#define PACR 0xA4050100
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#define PBCR 0xA4050102
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#define PCCR 0xA4050104
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#define PETCR 0xA4050106
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/* Port Data Registers */
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#define PADR 0xA4050120
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#define PBDR 0xA4050122
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#define PCDR 0xA4050124
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/* BSC */
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#define CMNCR 0xA4FD0000
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#define CS0BCR 0xA4FD0004
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#define CS2BCR 0xA4FD0008
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#define CS3BCR 0xA4FD000C
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#define CS4BCR 0xA4FD0010
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#define CS5ABCR 0xA4FD0014
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#define CS5BBCR 0xA4FD0018
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#define CS6ABCR 0xA4FD001C
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#define CS6BBCR 0xA4FD0020
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#define CS0WCR 0xA4FD0024
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#define CS2WCR 0xA4FD0028
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#define CS3WCR 0xA4FD002C
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#define CS4WCR 0xA4FD0030
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#define CS5AWCR 0xA4FD0034
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#define CS5BWCR 0xA4FD0038
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#define CS6AWCR 0xA4FD003C
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#define CS6BWCR 0xA4FD0040
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/* SDRAM controller */
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#define SDCR 0xA4FD0044
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#define RTCSR 0xA4FD0048
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#define RTCNT 0xA4FD004C
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#define RTCOR 0xA4FD0050
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/* SCIF */
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#define SCSMR_0 0xA4400000
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#define SCIF0_BASE SCSMR_0
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#define SCSMR_0 0xA4410000
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#define SCIF1_BASE SCSMR_1
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/* Timer */
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#define TMU_BASE 0xA412FE90
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/* On chip oscillator circuits */
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#define FRQCR 0xA415FF80
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#define WTCNT 0xA415FF84
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#define WTCSR 0xA415FF86
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#endif /* _ASM_CPU_SH7710_H_ */
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