upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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199 lines
5.8 KiB
199 lines
5.8 KiB
24 years ago
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/*
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* (C) Copyright 2001
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* Erik Theisen, Wave 7 Optics, etheisen@mindspring.com
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include <config.h>
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#if defined(CONFIG_4xx) && defined(CFG_CMD_SETGETDCR)
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#include <ppc4xx.h>
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#define _LINUX_CONFIG_H 1 /* avoid reading Linux autoconf.h file */
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#include <ppc_asm.tmpl>
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#include <ppc_defs.h>
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#include <asm/cache.h>
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#include <asm/mmu.h>
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#define _ASMLANGUAGE
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/*****************************************************************************
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*
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* XXX - DANGER
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* These routines make use of self modifying code. DO NOT CALL THEM
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* UNTIL THEY ARE RELOCATED TO RAM. Additionally, I do not
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* recommend them for use in anything other than an interactive
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* debugging environment. This is mainly due to performance reasons.
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*
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****************************************************************************/
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/*
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* static void _create_MFDCR(unsigned short dcrn)
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*
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* Builds a 'mfdcr' instruction for get_dcr
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* function.
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*/
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.section ".text"
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.align 2
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.type _create_MFDCR,@function
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_create_MFDCR:
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/*
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* Build up a 'mfdcr' instruction formatted as follows:
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*
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* OPCD | RT | DCRF | XO | CR |
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* ---------------|--------------|--------------|----|
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* 0 5 | 6 10 | 11 20 | 21 30 | 31 |
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* | | DCRN | | |
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* 31 | %r3 | (5..9|0..4) | 323 | 0 |
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*
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* Where:
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* OPCD = opcode - 31
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* RT = destination register - %r3 return register
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* DCRF = DCRN # with upper and lower halves swapped
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* XO = extended opcode - 323
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* CR = CR[CR0] NOT undefined - 0
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*/
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rlwinm r0, r3, 27, 27, 31 /* OPCD = 31 */
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rlwinm r3, r3, 5, 22, 26
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or r3, r3, r0
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slwi r3, r3, 10
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oris r3, r3, 0x3e30 /* RT = %r3 */
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ori r3, r3, 323 /* XO = 323 */
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slwi r3, r3, 1 /* CR = 0 */
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mflr r4
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stw r3, 0(r4) /* Store instr in get_dcr() */
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dcbst r0, r4 /* Make sure val is written out */
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sync /* Wait for write to complete */
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icbi r0, r4 /* Make sure old instr is dumped */
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isync /* Wait for icbi to complete */
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blr
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.Lfe1: .size _create_MFDCR,.Lfe1-_create_MFDCR
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/* end _create_MFDCR() */
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/*
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* static void _create_MTDCR(unsigned short dcrn, unsigned long value)
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*
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* Builds a 'mtdcr' instruction for set_dcr
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* function.
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*/
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.section ".text"
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.align 2
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.type _create_MTDCR,@function
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_create_MTDCR:
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/*
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* Build up a 'mtdcr' instruction formatted as follows:
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*
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* OPCD | RS | DCRF | XO | CR |
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* ---------------|--------------|--------------|----|
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* 0 5 | 6 10 | 11 20 | 21 30 | 31 |
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* | | DCRN | | |
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* 31 | %r3 | (5..9|0..4) | 451 | 0 |
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*
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* Where:
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* OPCD = opcode - 31
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* RS = source register - %r4
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* DCRF = dest. DCRN # with upper and lower halves swapped
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* XO = extended opcode - 451
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* CR = CR[CR0] NOT undefined - 0
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*/
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rlwinm r0, r3, 27, 27, 31 /* OPCD = 31 */
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rlwinm r3, r3, 5, 22, 26
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or r3, r3, r0
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slwi r3, r3, 10
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oris r3, r3, 0x3e40 /* RS = %r4 */
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ori r3, r3, 451 /* XO = 451 */
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slwi r3, r3, 1 /* CR = 0 */
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mflr r5
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stw r3, 0(r5) /* Store instr in set_dcr() */
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dcbst r0, r5 /* Make sure val is written out */
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sync /* Wait for write to complete */
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icbi r0, r5 /* Make sure old instr is dumped */
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isync /* Wait for icbi to complete */
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blr
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.Lfe2: .size _create_MTDCR,.Lfe2-_create_MTDCR
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/* end _create_MTDCR() */
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/*
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* unsigned long get_dcr(unsigned short dcrn)
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*
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* Return a given DCR's value.
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*/
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/* */
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/* XXX - This is self modifying code, hence */
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/* it is in the data section. */
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/* */
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.section ".data"
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.align 2
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.globl get_dcr
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.type get_dcr,@function
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get_dcr:
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mflr r0 /* Get link register */
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stwu r1, -32(r1) /* Save back chain and move SP */
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stw r0, +36(r1) /* Save link register */
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bl _create_MFDCR /* Build following instruction */
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/* XXX - we build this instuction up on the fly. */
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.long 0 /* Get DCR's value */
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lwz r0, +36(r1) /* Get saved link register */
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mtlr r0 /* Restore link register */
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addi r1, r1, +32 /* Remove frame from stack */
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blr /* Return to calling function */
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.Lfe3: .size get_dcr,.Lfe3-get_dcr
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/* end get_dcr() */
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/*
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* unsigned void set_dcr(unsigned short dcrn, unsigned long value)
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*
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* Return a given DCR's value.
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*/
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/*
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* XXX - This is self modifying code, hence
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* it is in the data section.
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*/
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.section ".data"
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.align 2
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.globl set_dcr
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.type set_dcr,@function
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set_dcr:
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mflr r0 /* Get link register */
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stwu r1, -32(r1) /* Save back chain and move SP */
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stw r0, +36(r1) /* Save link register */
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bl _create_MTDCR /* Build following instruction */
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/* XXX - we build this instuction up on the fly. */
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.long 0 /* Set DCR's value */
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lwz r0, +36(r1) /* Get saved link register */
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mtlr r0 /* Restore link register */
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addi r1, r1, +32 /* Remove frame from stack */
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blr /* Return to calling function */
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.Lfe4: .size set_dcr,.Lfe4-set_dcr
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/* end set_dcr() */
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#endif /* CONFIG_4xx & CFG_CMD_SETGETDCR */
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