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/*
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* Copyright (C) 2014 Freescale Semiconductor
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include "qbman_private.h"
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#include <fsl-mc/fsl_qbman_portal.h>
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#include <fsl-mc/fsl_dpaa_fd.h>
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/* All QBMan command and result structures use this "valid bit" encoding */
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#define QB_VALID_BIT ((uint32_t)0x80)
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/* Management command result codes */
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#define QBMAN_MC_RSLT_OK 0xf0
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/* TBD: as of QBMan 4.1, DQRR will be 8 rather than 4! */
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#define QBMAN_DQRR_SIZE 4
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/* --------------------- */
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/* portal data structure */
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/* --------------------- */
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struct qbman_swp {
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const struct qbman_swp_desc *desc;
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/* The qbman_sys (ie. arch/OS-specific) support code can put anything it
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* needs in here. */
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struct qbman_swp_sys sys;
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/* Management commands */
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struct {
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#ifdef QBMAN_CHECKING
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enum swp_mc_check {
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swp_mc_can_start, /* call __qbman_swp_mc_start() */
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swp_mc_can_submit, /* call __qbman_swp_mc_submit() */
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swp_mc_can_poll, /* call __qbman_swp_mc_result() */
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} check;
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#endif
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uint32_t valid_bit; /* 0x00 or 0x80 */
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} mc;
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/* Push dequeues */
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uint32_t sdq;
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/* Volatile dequeues */
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struct {
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/* VDQCR supports a "1 deep pipeline", meaning that if you know
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* the last-submitted command is already executing in the
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* hardware (as evidenced by at least 1 valid dequeue result),
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* you can write another dequeue command to the register, the
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* hardware will start executing it as soon as the
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* already-executing command terminates. (This minimises latency
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* and stalls.) With that in mind, this "busy" variable refers
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* to whether or not a command can be submitted, not whether or
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* not a previously-submitted command is still executing. In
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* other words, once proof is seen that the previously-submitted
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* command is executing, "vdq" is no longer "busy".
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*/
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atomic_t busy;
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uint32_t valid_bit; /* 0x00 or 0x80 */
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/* We need to determine when vdq is no longer busy. This depends
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* on whether the "busy" (last-submitted) dequeue command is
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* targeting DQRR or main-memory, and detected is based on the
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* presence of the dequeue command's "token" showing up in
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* dequeue entries in DQRR or main-memory (respectively). Debug
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* builds will, when submitting vdq commands, verify that the
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* dequeue result location is not already equal to the command's
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* token value. */
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struct ldpaa_dq *storage; /* NULL if DQRR */
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uint32_t token;
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} vdq;
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/* DQRR */
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struct {
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uint32_t next_idx;
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uint32_t valid_bit;
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} dqrr;
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};
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/* -------------------------- */
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/* portal management commands */
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/* -------------------------- */
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/* Different management commands all use this common base layer of code to issue
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* commands and poll for results. The first function returns a pointer to where
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* the caller should fill in their MC command (though they should ignore the
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* verb byte), the second function commits merges in the caller-supplied command
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* verb (which should not include the valid-bit) and submits the command to
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* hardware, and the third function checks for a completed response (returns
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* non-NULL if only if the response is complete). */
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void *qbman_swp_mc_start(struct qbman_swp *p);
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void qbman_swp_mc_submit(struct qbman_swp *p, void *cmd, uint32_t cmd_verb);
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void *qbman_swp_mc_result(struct qbman_swp *p);
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/* Wraps up submit + poll-for-result */
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static inline void *qbman_swp_mc_complete(struct qbman_swp *swp, void *cmd,
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uint32_t cmd_verb)
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{
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int loopvar;
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qbman_swp_mc_submit(swp, cmd, cmd_verb);
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DBG_POLL_START(loopvar);
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do {
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DBG_POLL_CHECK(loopvar);
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cmd = qbman_swp_mc_result(swp);
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} while (!cmd);
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return cmd;
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}
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/* ------------ */
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/* qb_attr_code */
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/* ------------ */
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/* This struct locates a sub-field within a QBMan portal (CENA) cacheline which
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* is either serving as a configuration command or a query result. The
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* representation is inherently little-endian, as the indexing of the words is
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* itself little-endian in nature and layerscape is little endian for anything
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* that crosses a word boundary too (64-bit fields are the obvious examples).
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*/
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struct qb_attr_code {
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unsigned int word; /* which uint32_t[] array member encodes the field */
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unsigned int lsoffset; /* encoding offset from ls-bit */
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unsigned int width; /* encoding width. (bool must be 1.) */
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};
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/* Macros to define codes */
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#define QB_CODE(a, b, c) { a, b, c}
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/* decode a field from a cacheline */
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static inline uint32_t qb_attr_code_decode(const struct qb_attr_code *code,
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const uint32_t *cacheline)
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{
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return d32_uint32_t(code->lsoffset, code->width, cacheline[code->word]);
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}
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/* encode a field to a cacheline */
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static inline void qb_attr_code_encode(const struct qb_attr_code *code,
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uint32_t *cacheline, uint32_t val)
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{
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cacheline[code->word] =
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r32_uint32_t(code->lsoffset, code->width, cacheline[code->word])
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| e32_uint32_t(code->lsoffset, code->width, val);
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}
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static inline void qb_attr_code_encode_64(const struct qb_attr_code *code,
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uint64_t *cacheline, uint64_t val)
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{
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cacheline[code->word / 2] = val;
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}
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/* ---------------------- */
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/* Descriptors/cachelines */
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/* ---------------------- */
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/* To avoid needless dynamic allocation, the driver API often gives the caller
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* a "descriptor" type that the caller can instantiate however they like.
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* Ultimately though, it is just a cacheline of binary storage (or something
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* smaller when it is known that the descriptor doesn't need all 64 bytes) for
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* holding pre-formatted pieces of hardware commands. The performance-critical
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* code can then copy these descriptors directly into hardware command
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* registers more efficiently than trying to construct/format commands
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* on-the-fly. The API user sees the descriptor as an array of 32-bit words in
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* order for the compiler to know its size, but the internal details are not
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* exposed. The following macro is used within the driver for converting *any*
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* descriptor pointer to a usable array pointer. The use of a macro (instead of
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* an inline) is necessary to work with different descriptor types and to work
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* correctly with const and non-const inputs (and similarly-qualified outputs).
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*/
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#define qb_cl(d) (&(d)->dont_manipulate_directly[0])
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