upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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87 lines
2.8 KiB
87 lines
2.8 KiB
16 years ago
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/*
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* Copyright (c) 2005 freescale semiconductor
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* Copyright (c) 2005 MontaVista Software
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* Copyright (c) 2008 Excito Elektronik i Sk=E5ne AB
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#ifndef _EHCI_FSL_H
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#define _EHCI_FSL_H
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/* Global offsets */
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#define FSL_SKIP_PCI 0x100
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/* offsets for the non-ehci registers in the FSL SOC USB controller */
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#define FSL_SOC_USB_ULPIVP 0x170
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#define FSL_SOC_USB_PORTSC1 0x184
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#define PORT_PTS_MSK (3 << 30)
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#define PORT_PTS_UTMI (0 << 30)
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#define PORT_PTS_ULPI (2 << 30)
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#define PORT_PTS_SERIAL (3 << 30)
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#define PORT_PTS_PTW (1 << 28)
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/* USBMODE Register bits */
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#define CM_IDLE (0 << 0)
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#define CM_RESERVED (1 << 0)
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#define CM_DEVICE (2 << 0)
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#define CM_HOST (3 << 0)
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#define USBMODE_RESERVED_2 (0 << 2)
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#define SLOM (1 << 3)
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#define SDIS (1 << 4)
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/* CONTROL Register bits */
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#define ULPI_INT_EN (1 << 0)
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#define WU_INT_EN (1 << 1)
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#define USB_EN (1 << 2)
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#define LSF_EN (1 << 3)
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#define KEEP_OTG_ON (1 << 4)
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#define OTG_PORT (1 << 5)
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#define REFSEL_12MHZ (0 << 6)
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#define REFSEL_16MHZ (1 << 6)
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#define REFSEL_48MHZ (2 << 6)
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#define PLL_RESET (1 << 8)
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#define UTMI_PHY_EN (1 << 9)
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#define PHY_CLK_SEL_UTMI (0 << 10)
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#define PHY_CLK_SEL_ULPI (1 << 10)
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#define CLKIN_SEL_USB_CLK (0 << 11)
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#define CLKIN_SEL_USB_CLK2 (1 << 11)
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#define CLKIN_SEL_SYS_CLK (2 << 11)
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#define CLKIN_SEL_SYS_CLK2 (3 << 11)
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#define RESERVED_18 (0 << 13)
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#define RESERVED_17 (0 << 14)
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#define RESERVED_16 (0 << 15)
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#define WU_INT (1 << 16)
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#define PHY_CLK_VALID (1 << 17)
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#define FSL_SOC_USB_PORTSC2 0x188
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#define FSL_SOC_USB_USBMODE 0x1a8
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#define FSL_SOC_USB_SNOOP1 0x400 /* NOTE: big-endian */
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#define FSL_SOC_USB_SNOOP2 0x404 /* NOTE: big-endian */
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#define FSL_SOC_USB_AGECNTTHRSH 0x408 /* NOTE: big-endian */
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#define FSL_SOC_USB_PRICTRL 0x40c /* NOTE: big-endian */
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#define FSL_SOC_USB_SICTRL 0x410 /* NOTE: big-endian */
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#define FSL_SOC_USB_CTRL 0x500 /* NOTE: big-endian */
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#define SNOOP_SIZE_2GB 0x1e
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/* System Clock Control Register */
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#define MPC83XX_SCCR_USB_MASK 0x00f00000
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#define MPC83XX_SCCR_USB_DRCM_11 0x00300000
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#define MPC83XX_SCCR_USB_DRCM_01 0x00100000
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#define MPC83XX_SCCR_USB_DRCM_10 0x00200000
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#endif /* _EHCI_FSL_H */
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