upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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123 lines
6.6 KiB
123 lines
6.6 KiB
16 years ago
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/*
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* SDH Masks
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*/
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#ifndef __BFIN_PERIPHERAL_SDH__
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#define __BFIN_PERIPHERAL_SDH__
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/* Bit masks for SDH_COMMAND */
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#define CMD_IDX 0x3f /* Command Index */
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#define CMD_RSP 0x40 /* Response */
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#define CMD_L_RSP 0x80 /* Long Response */
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#define CMD_INT_E 0x100 /* Command Interrupt */
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#define CMD_PEND_E 0x200 /* Command Pending */
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#define CMD_E 0x400 /* Command Enable */
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/* Bit masks for SDH_PWR_CTL */
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#define PWR_ON 0x3 /* Power On */
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#define SD_CMD_OD 0x40 /* Open Drain Output */
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#define ROD_CTL 0x80 /* Rod Control */
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/* Bit masks for SDH_CLK_CTL */
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#define CLKDIV 0xff /* MC_CLK Divisor */
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#define CLK_E 0x100 /* MC_CLK Bus Clock Enable */
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#define PWR_SV_E 0x200 /* Power Save Enable */
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#define CLKDIV_BYPASS 0x400 /* Bypass Divisor */
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#define WIDE_BUS 0x800 /* Wide Bus Mode Enable */
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/* Bit masks for SDH_RESP_CMD */
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#define RESP_CMD 0x3f /* Response Command */
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/* Bit masks for SDH_DATA_CTL */
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#define DTX_E 0x1 /* Data Transfer Enable */
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#define DTX_DIR 0x2 /* Data Transfer Direction */
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#define DTX_MODE 0x4 /* Data Transfer Mode */
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#define DTX_DMA_E 0x8 /* Data Transfer DMA Enable */
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#define DTX_BLK_LGTH 0xf0 /* Data Transfer Block Length */
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/* Bit masks for SDH_STATUS */
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#define CMD_CRC_FAIL 0x1 /* CMD CRC Fail */
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#define DAT_CRC_FAIL 0x2 /* Data CRC Fail */
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#define CMD_TIME_OUT 0x4 /* CMD Time Out */
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#define DAT_TIME_OUT 0x8 /* Data Time Out */
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#define TX_UNDERRUN 0x10 /* Transmit Underrun */
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#define RX_OVERRUN 0x20 /* Receive Overrun */
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#define CMD_RESP_END 0x40 /* CMD Response End */
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#define CMD_SENT 0x80 /* CMD Sent */
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#define DAT_END 0x100 /* Data End */
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#define START_BIT_ERR 0x200 /* Start Bit Error */
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#define DAT_BLK_END 0x400 /* Data Block End */
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#define CMD_ACT 0x800 /* CMD Active */
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#define TX_ACT 0x1000 /* Transmit Active */
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#define RX_ACT 0x2000 /* Receive Active */
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#define TX_FIFO_STAT 0x4000 /* Transmit FIFO Status */
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#define RX_FIFO_STAT 0x8000 /* Receive FIFO Status */
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#define TX_FIFO_FULL 0x10000 /* Transmit FIFO Full */
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#define RX_FIFO_FULL 0x20000 /* Receive FIFO Full */
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#define TX_FIFO_ZERO 0x40000 /* Transmit FIFO Empty */
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#define RX_DAT_ZERO 0x80000 /* Receive FIFO Empty */
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#define TX_DAT_RDY 0x100000 /* Transmit Data Available */
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#define RX_FIFO_RDY 0x200000 /* Receive Data Available */
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/* Bit masks for SDH_STATUS_CLR */
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#define CMD_CRC_FAIL_STAT 0x1 /* CMD CRC Fail Status */
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#define DAT_CRC_FAIL_STAT 0x2 /* Data CRC Fail Status */
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#define CMD_TIMEOUT_STAT 0x4 /* CMD Time Out Status */
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#define DAT_TIMEOUT_STAT 0x8 /* Data Time Out status */
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#define TX_UNDERRUN_STAT 0x10 /* Transmit Underrun Status */
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#define RX_OVERRUN_STAT 0x20 /* Receive Overrun Status */
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#define CMD_RESP_END_STAT 0x40 /* CMD Response End Status */
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#define CMD_SENT_STAT 0x80 /* CMD Sent Status */
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#define DAT_END_STAT 0x100 /* Data End Status */
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#define START_BIT_ERR_STAT 0x200 /* Start Bit Error Status */
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#define DAT_BLK_END_STAT 0x400 /* Data Block End Status */
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/* Bit masks for SDH_MASK0 */
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#define CMD_CRC_FAIL_MASK 0x1 /* CMD CRC Fail Mask */
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#define DAT_CRC_FAIL_MASK 0x2 /* Data CRC Fail Mask */
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#define CMD_TIMEOUT_MASK 0x4 /* CMD Time Out Mask */
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#define DAT_TIMEOUT_MASK 0x8 /* Data Time Out Mask */
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#define TX_UNDERRUN_MASK 0x10 /* Transmit Underrun Mask */
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#define RX_OVERRUN_MASK 0x20 /* Receive Overrun Mask */
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#define CMD_RESP_END_MASK 0x40 /* CMD Response End Mask */
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#define CMD_SENT_MASK 0x80 /* CMD Sent Mask */
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#define DAT_END_MASK 0x100 /* Data End Mask */
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#define START_BIT_ERR_MASK 0x200 /* Start Bit Error Mask */
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#define DAT_BLK_END_MASK 0x400 /* Data Block End Mask */
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#define CMD_ACT_MASK 0x800 /* CMD Active Mask */
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#define TX_ACT_MASK 0x1000 /* Transmit Active Mask */
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#define RX_ACT_MASK 0x2000 /* Receive Active Mask */
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#define TX_FIFO_STAT_MASK 0x4000 /* Transmit FIFO Status Mask */
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#define RX_FIFO_STAT_MASK 0x8000 /* Receive FIFO Status Mask */
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#define TX_FIFO_FULL_MASK 0x10000 /* Transmit FIFO Full Mask */
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#define RX_FIFO_FULL_MASK 0x20000 /* Receive FIFO Full Mask */
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#define TX_FIFO_ZERO_MASK 0x40000 /* Transmit FIFO Empty Mask */
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#define RX_DAT_ZERO_MASK 0x80000 /* Receive FIFO Empty Mask */
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#define TX_DAT_RDY_MASK 0x100000 /* Transmit Data Available Mask */
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#define RX_FIFO_RDY_MASK 0x200000 /* Receive Data Available Mask */
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/* Bit masks for SDH_FIFO_CNT */
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#define FIFO_COUNT 0x7fff /* FIFO Count */
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/* Bit masks for SDH_E_STATUS */
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#define SDIO_INT_DET 0x2 /* SDIO Int Detected */
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#define SD_CARD_DET 0x10 /* SD Card Detect */
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/* Bit masks for SDH_E_MASK */
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#define SDIO_MSK 0x2 /* Mask SDIO Int Detected */
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#define SCD_MSK 0x40 /* Mask Card Detect */
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/* Bit masks for SDH_CFG */
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#define CLKS_EN 0x1 /* Clocks Enable */
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#define SD4E 0x4 /* SDIO 4-Bit Enable */
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#define MWE 0x8 /* Moving Window Enable */
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#define SD_RST 0x10 /* SDMMC Reset */
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#define PUP_SDDAT 0x20 /* Pull-up SD_DAT */
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#define PUP_SDDAT3 0x40 /* Pull-up SD_DAT3 */
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#define PD_SDDAT3 0x80 /* Pull-down SD_DAT3 */
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/* Bit masks for SDH_RD_WAIT_EN */
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#define RWR 0x1 /* Read Wait Request */
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#endif
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