@ -40,7 +40,7 @@ enum clk_ids {
MOD_CLK_BASE
} ;
static const struct cpg_core_clk r8a7794_core_clks [ ] __initconst = {
static const struct cpg_core_clk r8a7794_core_clks [ ] = {
/* External Clock Inputs */
DEF_INPUT ( " extal " , CLK_EXTAL ) ,
DEF_INPUT ( " usb_extal " , CLK_USB_EXTAL ) ,
@ -85,7 +85,7 @@ static const struct cpg_core_clk r8a7794_core_clks[] __initconst = {
DEF_DIV6P1 ( " mmc0 " , R8A7794_CLK_MMC0 , CLK_PLL1_DIV2 , 0x240 ) ,
} ;
static const struct mssr_mod_clk r8a7794_mod_clks [ ] __initconst = {
static const struct mssr_mod_clk r8a7794_mod_clks [ ] = {
DEF_MOD ( " msiof0 " , 0 , R8A7794_CLK_MP ) ,
DEF_MOD ( " vcp0 " , 101 , R8A7794_CLK_ZS ) ,
DEF_MOD ( " vpc0 " , 103 , R8A7794_CLK_ZS ) ,
@ -188,10 +188,6 @@ static const struct mssr_mod_clk r8a7794_mod_clks[] __initconst = {
DEF_MOD ( " scifa5 " , 1108 , R8A7794_CLK_MP ) ,
} ;
static const unsigned int r8a7794_crit_mod_clks [ ] __initconst = {
MOD_CLK_ID ( 408 ) , /* INTC-SYS (GIC) */
} ;
/*
* CPG Clock Data
*/
@ -210,7 +206,7 @@ static const unsigned int r8a7794_crit_mod_clks[] __initconst = {
*/
# define CPG_PLL_CONFIG_INDEX(md) ((((md) & BIT(14)) >> 13) | \
( ( ( md ) & BIT ( 13 ) ) > > 13 ) )
static const struct rcar_gen2_cpg_pll_config cpg_pll_configs [ 4 ] __initconst = {
static const struct rcar_gen2_cpg_pll_config cpg_pll_configs [ 4 ] = {
{ 1 , 208 , 88 , 200 } ,
{ 1 , 156 , 66 , 150 } ,
{ 2 , 240 , 102 , 230 } ,