Consolidate ATA, ePORT, QSPI, FlexCan, PWM, RNG, MDHA, SKHA, INTC, and FlexBus structures and definitions in immap_5xxx.h to more unify modules header files. Append DSPI support for m547x_8x. SSI cleanup. Remove USB Host structure from immap_539.h. Apply changes to use FlexBus structures in mcf52x2's cpu_init.c and platform configuration files. Signed-off-by: TsiChung Liew <Tsi-Chung.Liew@freescale.com>master
TsiChung Liew
17 years ago
committed by
John Rigby
parent
ac2331aee9
commit
012522fef3
@ -0,0 +1,79 @@ |
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/*
|
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* ATA Internal Memory Map |
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* |
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* Copyright (C) 2004-2008 Freescale Semiconductor, Inc. |
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* TsiChung Liew (Tsi-Chung.Liew@freescale.com) |
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* |
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* See file CREDITS for list of people who contributed to this |
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* project. |
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* |
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* This program is free software; you can redistribute it and/or |
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* modify it under the terms of the GNU General Public License as |
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* published by the Free Software Foundation; either version 2 of |
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* the License, or (at your option) any later version. |
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* |
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* This program is distributed in the hope that it will be useful, |
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* but WITHOUT ANY WARRANTY; without even the implied warranty of |
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
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* GNU General Public License for more details. |
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* |
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* You should have received a copy of the GNU General Public License |
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* along with this program; if not, write to the Free Software |
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
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* MA 02111-1307 USA |
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*/ |
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#ifndef __ATA_H__ |
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#define __ATA_H__ |
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/* ATA */ |
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typedef struct atac { |
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/* PIO */ |
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u8 toff; /* 0x00 */ |
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u8 ton; /* 0x01 */ |
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u8 t1; /* 0x02 */ |
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u8 t2w; /* 0x03 */ |
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u8 t2r; /* 0x04 */ |
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u8 ta; /* 0x05 */ |
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u8 trd; /* 0x06 */ |
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u8 t4; /* 0x07 */ |
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u8 t9; /* 0x08 */ |
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|
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/* DMA */ |
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u8 tm; /* 0x09 */ |
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u8 tn; /* 0x0A */ |
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u8 td; /* 0x0B */ |
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u8 tk; /* 0x0C */ |
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u8 tack; /* 0x0D */ |
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u8 tenv; /* 0x0E */ |
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u8 trp; /* 0x0F */ |
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u8 tzah; /* 0x10 */ |
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u8 tmli; /* 0x11 */ |
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u8 tdvh; /* 0x12 */ |
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u8 tdzfs; /* 0x13 */ |
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u8 tdvs; /* 0x14 */ |
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u8 tcvh; /* 0x15 */ |
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u8 tss; /* 0x16 */ |
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u8 tcyc; /* 0x17 */ |
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|
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/* FIFO */ |
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u32 fifo32; /* 0x18 */ |
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u16 fifo16; /* 0x1C */ |
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u8 rsvd0[2]; |
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u8 ffill; /* 0x20 */ |
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u8 rsvd1[3]; |
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|
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/* ATA */ |
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u8 cr; /* 0x24 */ |
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u8 rsvd2[3]; |
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u8 isr; /* 0x28 */ |
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u8 rsvd3[3]; |
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u8 ier; /* 0x2C */ |
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u8 rsvd4[3]; |
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u8 icr; /* 0x30 */ |
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u8 rsvd5[3]; |
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u8 falarm; /* 0x34 */ |
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u8 rsvd6[106]; |
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} atac_t; |
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#endif /* __ATA_H__ */ |
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@ -0,0 +1,139 @@ |
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/*
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* Edge Port Memory Map |
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* |
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* Copyright (C) 2004-2008 Freescale Semiconductor, Inc. |
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* TsiChung Liew (Tsi-Chung.Liew@freescale.com) |
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* |
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* See file CREDITS for list of people who contributed to this |
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* project. |
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* |
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* This program is free software; you can redistribute it and/or |
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* modify it under the terms of the GNU General Public License as |
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* published by the Free Software Foundation; either version 2 of |
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* the License, or (at your option) any later version. |
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* |
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* This program is distributed in the hope that it will be useful, |
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* but WITHOUT ANY WARRANTY; without even the implied warranty of |
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
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* GNU General Public License for more details. |
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* |
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* You should have received a copy of the GNU General Public License |
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* along with this program; if not, write to the Free Software |
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
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* MA 02111-1307 USA |
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*/ |
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#ifndef __EPORT_H__ |
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#define __EPORT_H__ |
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/* Edge Port Module (EPORT) */ |
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typedef struct eport { |
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#ifdef CONFIG_MCF547x_8x |
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u16 par; /* 0x00 */ |
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u16 res0; /* 0x02 */ |
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u8 ddr; /* 0x04 */ |
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u8 ier; /* 0x05 */ |
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u16 res1; /* 0x06 */ |
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u8 dr; /* 0x08 */ |
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u8 pdr; /* 0x09 */ |
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u16 res2; /* 0x0A */ |
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u8 fr; /* 0x0C */ |
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u8 res3[3]; /* 0x0D */ |
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#else |
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u16 par; /* 0x00 Pin Assignment */ |
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u8 ddr; /* 0x02 Data Direction */ |
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u8 ier; /* 0x03 Interrupt Enable */ |
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u8 dr; /* 0x04 Data */ |
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u8 pdr; /* 0x05 Pin Data */ |
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u8 fr; /* 0x06 Flag */ |
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u8 res0; |
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#endif |
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} eport_t; |
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/* EPPAR */ |
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#define EPORT_PAR_EPPA1(x) (((x)&0x0003)<<2) |
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#define EPORT_PAR_EPPA2(x) (((x)&0x0003)<<4) |
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#define EPORT_PAR_EPPA3(x) (((x)&0x0003)<<6) |
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#define EPORT_PAR_EPPA4(x) (((x)&0x0003)<<8) |
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#define EPORT_PAR_EPPA5(x) (((x)&0x0003)<<10) |
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#define EPORT_PAR_EPPA6(x) (((x)&0x0003)<<12) |
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#define EPORT_PAR_EPPA7(x) (((x)&0x0003)<<14) |
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#define EPORT_PAR_LEVEL (0) |
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#define EPORT_PAR_RISING (1) |
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#define EPORT_PAR_FALLING (2) |
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#define EPORT_PAR_BOTH (3) |
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#define EPORT_PAR_EPPA7_LEVEL (0x0000) |
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#define EPORT_PAR_EPPA7_RISING (0x4000) |
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#define EPORT_PAR_EPPA7_FALLING (0x8000) |
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#define EPORT_PAR_EPPA7_BOTH (0xC000) |
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#define EPORT_PAR_EPPA6_LEVEL (0x0000) |
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#define EPORT_PAR_EPPA6_RISING (0x1000) |
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#define EPORT_PAR_EPPA6_FALLING (0x2000) |
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#define EPORT_PAR_EPPA6_BOTH (0x3000) |
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#define EPORT_PAR_EPPA5_LEVEL (0x0000) |
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#define EPORT_PAR_EPPA5_RISING (0x0400) |
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#define EPORT_PAR_EPPA5_FALLING (0x0800) |
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#define EPORT_PAR_EPPA5_BOTH (0x0C00) |
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#define EPORT_PAR_EPPA4_LEVEL (0x0000) |
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#define EPORT_PAR_EPPA4_RISING (0x0100) |
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#define EPORT_PAR_EPPA4_FALLING (0x0200) |
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#define EPORT_PAR_EPPA4_BOTH (0x0300) |
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#define EPORT_PAR_EPPA3_LEVEL (0x0000) |
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#define EPORT_PAR_EPPA3_RISING (0x0040) |
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#define EPORT_PAR_EPPA3_FALLING (0x0080) |
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#define EPORT_PAR_EPPA3_BOTH (0x00C0) |
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#define EPORT_PAR_EPPA2_LEVEL (0x0000) |
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#define EPORT_PAR_EPPA2_RISING (0x0010) |
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#define EPORT_PAR_EPPA2_FALLING (0x0020) |
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#define EPORT_PAR_EPPA2_BOTH (0x0030) |
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#define EPORT_PAR_EPPA1_LEVEL (0x0000) |
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#define EPORT_PAR_EPPA1_RISING (0x0004) |
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#define EPORT_PAR_EPPA1_FALLING (0x0008) |
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#define EPORT_PAR_EPPA1_BOTH (0x000C) |
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/* EPDDR */ |
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#define EPORT_DDR_EPDD1 (0x02) |
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#define EPORT_DDR_EPDD2 (0x04) |
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#define EPORT_DDR_EPDD3 (0x08) |
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#define EPORT_DDR_EPDD4 (0x10) |
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#define EPORT_DDR_EPDD5 (0x20) |
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#define EPORT_DDR_EPDD6 (0x40) |
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#define EPORT_DDR_EPDD7 (0x80) |
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/* EPIER */ |
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#define EPORT_IER_EPIE1 (0x02) |
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#define EPORT_IER_EPIE2 (0x04) |
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#define EPORT_IER_EPIE3 (0x08) |
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#define EPORT_IER_EPIE4 (0x10) |
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#define EPORT_IER_EPIE5 (0x20) |
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#define EPORT_IER_EPIE6 (0x40) |
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#define EPORT_IER_EPIE7 (0x80) |
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/* EPDR */ |
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#define EPORT_DR_EPD1 (0x02) |
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#define EPORT_DR_EPD2 (0x04) |
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#define EPORT_DR_EPD3 (0x08) |
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#define EPORT_DR_EPD4 (0x10) |
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#define EPORT_DR_EPD5 (0x20) |
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#define EPORT_DR_EPD6 (0x40) |
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#define EPORT_DR_EPD7 (0x80) |
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/* EPPDR */ |
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#define EPORT_PDR_EPPD1 (0x02) |
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#define EPORT_PDR_EPPD2 (0x04) |
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#define EPORT_PDR_EPPD3 (0x08) |
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#define EPORT_PDR_EPPD4 (0x10) |
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#define EPORT_PDR_EPPD5 (0x20) |
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#define EPORT_PDR_EPPD6 (0x40) |
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#define EPORT_PDR_EPPD7 (0x80) |
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/* EPFR */ |
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#define EPORT_FR_EPF1 (0x02) |
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#define EPORT_FR_EPF2 (0x04) |
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#define EPORT_FR_EPF3 (0x08) |
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#define EPORT_FR_EPF4 (0x10) |
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#define EPORT_FR_EPF5 (0x20) |
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#define EPORT_FR_EPF6 (0x40) |
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#define EPORT_FR_EPF7 (0x80) |
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#endif /* __EPORT_H__ */ |
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@ -0,0 +1,219 @@ |
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/*
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* Flex CAN Memory Map |
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* |
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* Copyright (C) 2004-2007 Freescale Semiconductor, Inc. |
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* TsiChung Liew (Tsi-Chung.Liew@freescale.com) |
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* |
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* See file CREDITS for list of people who contributed to this |
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* project. |
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* |
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* This program is free software; you can redistribute it and/or |
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* modify it under the terms of the GNU General Public License as |
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* published by the Free Software Foundation; either version 2 of |
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* the License, or (at your option) any later version. |
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* |
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* This program is distributed in the hope that it will be useful, |
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* but WITHOUT ANY WARRANTY; without even the implied warranty of |
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
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* GNU General Public License for more details. |
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* |
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* You should have received a copy of the GNU General Public License |
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* along with this program; if not, write to the Free Software |
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
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* MA 02111-1307 USA |
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*/ |
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#ifndef __FLEXCAN_H__ |
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#define __FLEXCAN_H__ |
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/* FlexCan Message Buffer */ |
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typedef struct can_msgbuf_ctrl { |
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#ifdef CONFIG_M5282 |
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u8 tmstamp; /* 0x00 Timestamp */ |
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u8 ctrl; /* 0x01 Control */ |
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u16 idh; /* 0x02 ID High */ |
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u16 idl; /* 0x04 ID High */ |
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u8 data[8]; /* 0x06 8 Byte Data Field */ |
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u16 res; /* 0x0E */ |
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#else |
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u16 ctrl; /* 0x00 Control/Status */ |
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u16 tmstamp; /* 0x02 Timestamp */ |
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u32 id; /* 0x04 Identifier */ |
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u8 data[8]; /* 0x08 8 Byte Data Field */ |
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#endif |
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} can_msg_t; |
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#ifdef CONFIG_M5282 |
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/* MSGBUF CTRL */ |
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#define CAN_MSGBUF_CTRL_CODE(x) (((x) & 0x0F) << 4) |
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#define CAN_MSGBUF_CTRL_CODE_MASK (0x0F) |
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#define CAN_MSGBUF_CTRL_LEN(x) ((x) & 0x0F) |
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#define CAN_MSGBUF_CTRL_LEN_MASK (0xF0) |
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/* MSGBUF ID */ |
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#define CAN_MSGBUF_IDH_STD(x) (((x) & 0x07FF) << 5) |
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#define CAN_MSGBUF_IDH_STD_MASK (0xE003FFFF) |
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#define CAN_MSGBUF_IDH_SRR (0x0010) |
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#define CAN_MSGBUF_IDH_IDE (0x0080) |
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#define CAN_MSGBUF_IDH_EXTH(x) ((x) & 0x07) |
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#define CAN_MSGBUF_IDH_EXTH_MASK (0xFFF8) |
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#define CAN_MSGBUF_IDL_EXTL(x) (((x) & 0x7FFF) << 1) |
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#define CAN_MSGBUF_IDL_EXTL_MASK (0xFFFE) |
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#define CAN_MSGBUF_IDL_RTR (0x0001) |
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#else |
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/* MSGBUF CTRL */ |
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#define CAN_MSGBUF_CTRL_CODE(x) (((x) & 0x000F) << 8) |
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#define CAN_MSGBUF_CTRL_CODE_MASK (0xF0FF) |
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#define CAN_MSGBUF_CTRL_SRR (0x0040) |
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#define CAN_MSGBUF_CTRL_IDE (0x0020) |
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#define CAN_MSGBUF_CTRL_RTR (0x0010) |
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#define CAN_MSGBUF_CTRL_LEN(x) ((x) & 0x000F) |
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#define CAN_MSGBUF_CTRL_LEN_MASK (0xFFF0) |
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/* MSGBUF ID */ |
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#define CAN_MSGBUF_ID_STD(x) (((x) & 0x000007FF) << 18) |
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#define CAN_MSGBUF_ID_STD_MASK (0xE003FFFF) |
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#define CAN_MSGBUF_ID_EXT(x) ((x) & 0x0003FFFF) |
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#define CAN_MSGBUF_ID_EXT_MASK (0xFFFC0000) |
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#endif |
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/* FlexCan module */ |
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typedef struct can_ctrl { |
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u32 mcr; /* 0x00 Module Configuration */ |
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u32 ctrl; /* 0x04 Control */ |
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u32 timer; /* 0x08 Free Running Timer */ |
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u32 res1; /* 0x0C */ |
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u32 rxgmsk; /* 0x10 Rx Global Mask */ |
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u32 rx14msk; /* 0x14 RxBuffer 14 Mask */ |
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u32 rx15msk; /* 0x18 RxBuffer 15 Mask */ |
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#ifdef CONFIG_M5282 |
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u32 res2; /* 0x1C */ |
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u16 errstat; /* 0x20 Error and status */ |
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u16 imsk; /* 0x22 Interrupt Mask */ |
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u16 iflag; /* 0x24 Interrupt Flag */ |
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u16 errcnt; /* 0x26 Error Counter */ |
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u32 res3[3]; /* 0x28 - 0x33 */ |
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#else |
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u16 res2; /* 0x1C */ |
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u16 errcnt; /* 0x1E Error Counter */ |
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u16 res3; /* 0x20 */ |
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u16 errstat; /* 0x22 Error and status */ |
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u32 res4; /* 0x24 */ |
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u32 imsk; /* 0x28 Interrupt Mask */ |
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u32 res5; /* 0x2C */ |
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u16 iflag; /* 0x30 Interrupt Flag */ |
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#endif |
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u32 res6[19]; /* 0x34 - 0x7F */ |
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void *msgbuf; /* 0x80 Message Buffer 0-15 */ |
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} can_t; |
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/* MCR */ |
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#define CAN_MCR_MDIS (0x80000000) |
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#define CAN_MCR_FRZ (0x40000000) |
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#define CAN_MCR_HALT (0x10000000) |
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#define CAN_MCR_NORDY (0x08000000) |
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#define CAN_MCF_WAKEMSK (0x04000000) /* 5282 */ |
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#define CAN_MCR_SOFTRST (0x02000000) |
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#define CAN_MCR_FRZACK (0x01000000) |
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#define CAN_MCR_SUPV (0x00800000) |
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#define CAN_MCR_SELFWAKE (0x00400000) /* 5282 */ |
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#define CAN_MCR_APS (0x00200000) /* 5282 */ |
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#define CAN_MCR_LPMACK (0x00100000) |
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#define CAN_MCF_BCC (0x00010000) |
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#define CAN_MCR_MAXMB(x) ((x) & 0x0F) |
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#define CAN_MCR_MAXMB_MASK (0xFFFFFFF0) |
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/* CTRL */ |
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#define CAN_CTRL_PRESDIV(x) (((x) & 0xFF) << 24) |
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#define CAN_CTRL_PRESDIV_MASK (0x00FFFFFF) |
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#define CAN_CTRL_RJW(x) (((x) & 0x03) << 22) |
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#define CAN_CTRL_RJW_MASK (0xFF3FFFFF) |
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#define CAN_CTRL_PSEG1(x) (((x) & 0x07) << 19) |
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#define CAN_CTRL_PSEG1_MASK (0xFFC7FFFF) |
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#define CAN_CTRL_PSEG2(x) (((x) & 0x07) << 16) |
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#define CAN_CTRL_PSEG2_MASK (0xFFF8FFFF) |
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#define CAN_CTRL_BOFFMSK (0x00008000) |
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#define CAN_CTRL_ERRMSK (0x00004000) |
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#define CAN_CTRL_CLKSRC (0x00002000) |
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#define CAN_CTRL_LPB (0x00001000) |
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#define CAN_CTRL_RXMODE (0x00000400) /* 5282 */ |
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#define CAN_CTRL_TXMODE(x) (((x) & 0x03) << 8) /* 5282 */ |
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#define CAN_CTRL_TXMODE_MASK (0xFFFFFCFF) /* 5282 */ |
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#define CAN_CTRL_TXMODE_CAN0 (0x00000000) /* 5282 */ |
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#define CAN_CTRL_TXMODE_CAN1 (0x00000100) /* 5282 */ |
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#define CAN_CTRL_TXMODE_OPEN (0x00000200) /* 5282 */ |
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#define CAN_CTRL_SMP (0x00000080) |
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#define CAN_CTRL_BOFFREC (0x00000040) |
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#define CAN_CTRL_TSYNC (0x00000020) |
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#define CAN_CTRL_LBUF (0x00000010) |
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#define CAN_CTRL_LOM (0x00000008) |
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#define CAN_CTRL_PROPSEG(x) ((x) & 0x07) |
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#define CAN_CTRL_PROPSEG_MASK (0xFFFFFFF8) |
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/* TIMER */ |
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/* Note: PRESDIV, RJW, PSG1, and PSG2 are part of timer in 5282 */ |
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#define CAN_TIMER(x) ((x) & 0xFFFF) |
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#define CAN_TIMER_MASK (0xFFFF0000) |
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|
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/* RXGMASK */ |
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#ifdef CONFIG_M5282 |
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#define CAN_RXGMSK_MI_STD(x) (((x) & 0x000007FF) << 21) |
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#define CAN_RXGMSK_MI_STD_MASK (0x001FFFFF) |
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#define CAN_RXGMSK_MI_EXT(x) (((x) & 0x0003FFFF) << 1) |
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#define CAN_RXGMSK_MI_EXT_MASK (0xFFF80001) |
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#else |
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#define CAN_RXGMSK_MI_STD(x) (((x) & 0x000007FF) << 18) |
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#define CAN_RXGMSK_MI_STD_MASK (0xE003FFFF) |
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#define CAN_RXGMSK_MI_EXT(x) ((x) & 0x0003FFFF) |
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#define CAN_RXGMSK_MI_EXT_MASK (0xFFFC0000) |
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#endif |
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/* ERRCNT */ |
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#define CAN_ERRCNT_RXECTR(x) (((x) & 0xFF) << 8) |
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#define CAN_ERRCNT_RXECTR_MASK (0x00FF) |
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#define CAN_ERRCNT_TXECTR(x) ((x) & 0xFF) |
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#define CAN_ERRCNT_TXECTR_MASK (0xFF00) |
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|
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/* ERRSTAT */ |
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#define CAN_ERRSTAT_BITERR1 (0x8000) |
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#define CAN_ERRSTAT_BITERR0 (0x4000) |
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#define CAN_ERRSTAT_ACKERR (0x2000) |
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#define CAN_ERRSTAT_CRCERR (0x1000) |
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#define CAN_ERRSTAT_FRMERR (0x0800) |
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#define CAN_ERRSTAT_STFERR (0x0400) |
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#define CAN_ERRSTAT_TXWRN (0x0200) |
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#define CAN_ERRSTAT_RXWRN (0x0100) |
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#define CAN_ERRSTAT_IDLE (0x0080) |
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#define CAN_ERRSTAT_TXRX (0x0040) |
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#define CAN_ERRSTAT_FLT_MASK (0xFFCF) |
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#define CAN_ERRSTAT_FLT_BUSOFF (0x0020) |
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#define CAN_ERRSTAT_FLT_PASSIVE (0x0010) |
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#define CAN_ERRSTAT_FLT_ACTIVE (0x0000) |
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#ifdef CONFIG_M5282 |
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#define CAN_ERRSTAT_BOFFINT (0x0004) |
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#define CAN_ERRSTAT_ERRINT (0x0002) |
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#else |
||||
#define CAN_ERRSTAT_ERRINT (0x0004) |
||||
#define CAN_ERRSTAT_BOFFINT (0x0002) |
||||
#define CAN_ERRSTAT_WAKEINT (0x0001) |
||||
#endif |
||||
|
||||
/* IMASK */ |
||||
#ifdef CONFIG_M5253 |
||||
#define CAN_IMASK_BUFnM(x) (1 << (x & 0xFFFFFFFF)) |
||||
#define CAN_IMASK_BUFnM_MASKBIT(x) ~CAN_IMASK_BUFnM(x) |
||||
#else |
||||
#define CAN_IMASK_BUFnM(x) (1 << (x & 0xFFFF)) |
||||
#define CAN_IMASK_BUFnM_MASKBIT(x) ~CAN_IMASK_BUFnM(x) |
||||
#endif |
||||
|
||||
/* IFLAG */ |
||||
#ifdef CONFIG_M5253 |
||||
#define CAN_IFLAG_BUFnM(x) (1 << (x & 0xFFFFFFFF)) |
||||
#define CAN_IFLAG_BUFnM_MASKBIT(x) ~CAN_IFLAG_BUFnM(x) |
||||
#else |
||||
#define CAN_IFLAG_BUFnM(x) (1 << (x & 0xFFFF)) |
||||
#define CAN_IFLAG_BUFnM_MASKBIT(x) ~CAN_IFLAG_BUFnM(x) |
||||
#endif |
||||
|
||||
#endif /* __FLEXCAN_H__ */ |
||||
@ -0,0 +1,246 @@ |
||||
/*
|
||||
* Interrupt Controller Memory Map |
||||
* |
||||
* Copyright (C) 2004-2008 Freescale Semiconductor, Inc. |
||||
* TsiChung Liew (Tsi-Chung.Liew@freescale.com) |
||||
* |
||||
* See file CREDITS for list of people who contributed to this |
||||
* project. |
||||
* |
||||
* This program is free software; you can redistribute it and/or |
||||
* modify it under the terms of the GNU General Public License as |
||||
* published by the Free Software Foundation; either version 2 of |
||||
* the License, or (at your option) any later version. |
||||
* |
||||
* This program is distributed in the hope that it will be useful, |
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of |
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
||||
* GNU General Public License for more details. |
||||
* |
||||
* You should have received a copy of the GNU General Public License |
||||
* along with this program; if not, write to the Free Software |
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
||||
* MA 02111-1307 USA |
||||
*/ |
||||
|
||||
#ifndef __INTCTRL_H__ |
||||
#define __INTCTRL_H__ |
||||
|
||||
#if defined(CONFIG_M5235) || defined(CONFIG_M5271) || \ |
||||
defined(CONFIG_M5275) || defined(CONFIG_M5282) || \
|
||||
defined(CONFIG_M547x) || defined(CONFIG_M548x) |
||||
# define CONFIG_SYS_CF_INTC_REG1 |
||||
#endif |
||||
|
||||
typedef struct int0_ctrl { |
||||
/* Interrupt Controller 0 */ |
||||
u32 iprh0; /* 0x00 Pending High */ |
||||
u32 iprl0; /* 0x04 Pending Low */ |
||||
u32 imrh0; /* 0x08 Mask High */ |
||||
u32 imrl0; /* 0x0C Mask Low */ |
||||
u32 frch0; /* 0x10 Force High */ |
||||
u32 frcl0; /* 0x14 Force Low */ |
||||
#if defined(CONFIG_SYS_CF_INTC_REG1) |
||||
u8 irlr; /* 0x18 */ |
||||
u8 iacklpr; /* 0x19 */ |
||||
u16 res1[19]; /* 0x1a - 0x3c */ |
||||
#else |
||||
u16 res1; /* 0x18 - 0x19 */ |
||||
u16 icfg0; /* 0x1A Configuration */ |
||||
u8 simr0; /* 0x1C Set Interrupt Mask */ |
||||
u8 cimr0; /* 0x1D Clear Interrupt Mask */ |
||||
u8 clmask0; /* 0x1E Current Level Mask */ |
||||
u8 slmask; /* 0x1F Saved Level Mask */ |
||||
u32 res2[8]; /* 0x20 - 0x3F */ |
||||
#endif |
||||
u8 icr0[64]; /* 0x40 - 0x7F Control registers */ |
||||
u32 res3[24]; /* 0x80 - 0xDF */ |
||||
u8 swiack0; /* 0xE0 Software Interrupt ack */ |
||||
u8 res4[3]; /* 0xE1 - 0xE3 */ |
||||
u8 L1iack0; /* 0xE4 Level n interrupt ack */ |
||||
u8 res5[3]; /* 0xE5 - 0xE7 */ |
||||
u8 L2iack0; /* 0xE8 Level n interrupt ack */ |
||||
u8 res6[3]; /* 0xE9 - 0xEB */ |
||||
u8 L3iack0; /* 0xEC Level n interrupt ack */ |
||||
u8 res7[3]; /* 0xED - 0xEF */ |
||||
u8 L4iack0; /* 0xF0 Level n interrupt ack */ |
||||
u8 res8[3]; /* 0xF1 - 0xF3 */ |
||||
u8 L5iack0; /* 0xF4 Level n interrupt ack */ |
||||
u8 res9[3]; /* 0xF5 - 0xF7 */ |
||||
u8 L6iack0; /* 0xF8 Level n interrupt ack */ |
||||
u8 resa[3]; /* 0xF9 - 0xFB */ |
||||
u8 L7iack0; /* 0xFC Level n interrupt ack */ |
||||
u8 resb[3]; /* 0xFD - 0xFF */ |
||||
} int0_t; |
||||
|
||||
typedef struct int1_ctrl { |
||||
/* Interrupt Controller 1 */ |
||||
u32 iprh1; /* 0x00 Pending High */ |
||||
u32 iprl1; /* 0x04 Pending Low */ |
||||
u32 imrh1; /* 0x08 Mask High */ |
||||
u32 imrl1; /* 0x0C Mask Low */ |
||||
u32 frch1; /* 0x10 Force High */ |
||||
u32 frcl1; /* 0x14 Force Low */ |
||||
#if defined(CONFIG_SYS_CF_INTC_REG1) |
||||
u8 irlr; /* 0x18 */ |
||||
u8 iacklpr; /* 0x19 */ |
||||
u16 res1[19]; /* 0x1a - 0x3c */ |
||||
#else |
||||
u16 res1; /* 0x18 */ |
||||
u16 icfg1; /* 0x1A Configuration */ |
||||
u8 simr1; /* 0x1C Set Interrupt Mask */ |
||||
u8 cimr1; /* 0x1D Clear Interrupt Mask */ |
||||
u16 res2; /* 0x1E - 0x1F */ |
||||
u32 res3[8]; /* 0x20 - 0x3F */ |
||||
#endif |
||||
u8 icr1[64]; /* 0x40 - 0x7F */ |
||||
u32 res4[24]; /* 0x80 - 0xDF */ |
||||
u8 swiack1; /* 0xE0 Software Interrupt ack */ |
||||
u8 res5[3]; /* 0xE1 - 0xE3 */ |
||||
u8 L1iack1; /* 0xE4 Level n interrupt ack */ |
||||
u8 res6[3]; /* 0xE5 - 0xE7 */ |
||||
u8 L2iack1; /* 0xE8 Level n interrupt ack */ |
||||
u8 res7[3]; /* 0xE9 - 0xEB */ |
||||
u8 L3iack1; /* 0xEC Level n interrupt ack */ |
||||
u8 res8[3]; /* 0xED - 0xEF */ |
||||
u8 L4iack1; /* 0xF0 Level n interrupt ack */ |
||||
u8 res9[3]; /* 0xF1 - 0xF3 */ |
||||
u8 L5iack1; /* 0xF4 Level n interrupt ack */ |
||||
u8 resa[3]; /* 0xF5 - 0xF7 */ |
||||
u8 L6iack1; /* 0xF8 Level n interrupt ack */ |
||||
u8 resb[3]; /* 0xF9 - 0xFB */ |
||||
u8 L7iack1; /* 0xFC Level n interrupt ack */ |
||||
u8 resc[3]; /* 0xFD - 0xFF */ |
||||
} int1_t; |
||||
|
||||
typedef struct intgack_ctrl1 { |
||||
/* Global IACK Registers */ |
||||
u8 swiack; /* 0x00 Global Software Interrupt ack */ |
||||
u8 res0[0x3]; |
||||
u8 gl1iack; /* 0x04 */ |
||||
u8 resv1[0x3]; |
||||
u8 gl2iack; /* 0x08 */ |
||||
u8 res2[0x3]; |
||||
u8 gl3iack; /* 0x0C */ |
||||
u8 res3[0x3]; |
||||
u8 gl4iack; /* 0x10 */ |
||||
u8 res4[0x3]; |
||||
u8 gl5iack; /* 0x14 */ |
||||
u8 res5[0x3]; |
||||
u8 gl6iack; /* 0x18 */ |
||||
u8 res6[0x3]; |
||||
u8 gl7iack; /* 0x1C */ |
||||
u8 res7[0x3]; |
||||
} intgack_t; |
||||
|
||||
#define INTC_IPRH_INT63 (0x80000000) |
||||
#define INTC_IPRH_INT62 (0x40000000) |
||||
#define INTC_IPRH_INT61 (0x20000000) |
||||
#define INTC_IPRH_INT60 (0x10000000) |
||||
#define INTC_IPRH_INT59 (0x08000000) |
||||
#define INTC_IPRH_INT58 (0x04000000) |
||||
#define INTC_IPRH_INT57 (0x02000000) |
||||
#define INTC_IPRH_INT56 (0x01000000) |
||||
#define INTC_IPRH_INT55 (0x00800000) |
||||
#define INTC_IPRH_INT54 (0x00400000) |
||||
#define INTC_IPRH_INT53 (0x00200000) |
||||
#define INTC_IPRH_INT52 (0x00100000) |
||||
#define INTC_IPRH_INT51 (0x00080000) |
||||
#define INTC_IPRH_INT50 (0x00040000) |
||||
#define INTC_IPRH_INT49 (0x00020000) |
||||
#define INTC_IPRH_INT48 (0x00010000) |
||||
#define INTC_IPRH_INT47 (0x00008000) |
||||
#define INTC_IPRH_INT46 (0x00004000) |
||||
#define INTC_IPRH_INT45 (0x00002000) |
||||
#define INTC_IPRH_INT44 (0x00001000) |
||||
#define INTC_IPRH_INT43 (0x00000800) |
||||
#define INTC_IPRH_INT42 (0x00000400) |
||||
#define INTC_IPRH_INT41 (0x00000200) |
||||
#define INTC_IPRH_INT40 (0x00000100) |
||||
#define INTC_IPRH_INT39 (0x00000080) |
||||
#define INTC_IPRH_INT38 (0x00000040) |
||||
#define INTC_IPRH_INT37 (0x00000020) |
||||
#define INTC_IPRH_INT36 (0x00000010) |
||||
#define INTC_IPRH_INT35 (0x00000008) |
||||
#define INTC_IPRH_INT34 (0x00000004) |
||||
#define INTC_IPRH_INT33 (0x00000002) |
||||
#define INTC_IPRH_INT32 (0x00000001) |
||||
|
||||
#define INTC_IPRL_INT31 (0x80000000) |
||||
#define INTC_IPRL_INT30 (0x40000000) |
||||
#define INTC_IPRL_INT29 (0x20000000) |
||||
#define INTC_IPRL_INT28 (0x10000000) |
||||
#define INTC_IPRL_INT27 (0x08000000) |
||||
#define INTC_IPRL_INT26 (0x04000000) |
||||
#define INTC_IPRL_INT25 (0x02000000) |
||||
#define INTC_IPRL_INT24 (0x01000000) |
||||
#define INTC_IPRL_INT23 (0x00800000) |
||||
#define INTC_IPRL_INT22 (0x00400000) |
||||
#define INTC_IPRL_INT21 (0x00200000) |
||||
#define INTC_IPRL_INT20 (0x00100000) |
||||
#define INTC_IPRL_INT19 (0x00080000) |
||||
#define INTC_IPRL_INT18 (0x00040000) |
||||
#define INTC_IPRL_INT17 (0x00020000) |
||||
#define INTC_IPRL_INT16 (0x00010000) |
||||
#define INTC_IPRL_INT15 (0x00008000) |
||||
#define INTC_IPRL_INT14 (0x00004000) |
||||
#define INTC_IPRL_INT13 (0x00002000) |
||||
#define INTC_IPRL_INT12 (0x00001000) |
||||
#define INTC_IPRL_INT11 (0x00000800) |
||||
#define INTC_IPRL_INT10 (0x00000400) |
||||
#define INTC_IPRL_INT9 (0x00000200) |
||||
#define INTC_IPRL_INT8 (0x00000100) |
||||
#define INTC_IPRL_INT7 (0x00000080) |
||||
#define INTC_IPRL_INT6 (0x00000040) |
||||
#define INTC_IPRL_INT5 (0x00000020) |
||||
#define INTC_IPRL_INT4 (0x00000010) |
||||
#define INTC_IPRL_INT3 (0x00000008) |
||||
#define INTC_IPRL_INT2 (0x00000004) |
||||
#define INTC_IPRL_INT1 (0x00000002) |
||||
#define INTC_IPRL_INT0 (0x00000001) |
||||
|
||||
#define INTC_IMRLn_MASKALL (0x00000001) |
||||
|
||||
#define INTC_IRLR(x) (((x) & 0x7F) << 1) |
||||
#define INTC_IRLR_MASK (0x01) |
||||
|
||||
#define INTC_IACKLPR_LVL(x) (((x) & 0x07) << 4) |
||||
#define INTC_IACKLPR_LVL_MASK (0x8F) |
||||
#define INTC_IACKLPR_PRI(x) ((x) & 0x0F) |
||||
#define INTC_IACKLPR_PRI_MASK (0xF0) |
||||
|
||||
#if defined(CONFIG_SYS_CF_INTC_REG1) |
||||
#define INTC_ICR_IL(x) (((x) & 0x07) << 3) |
||||
#define INTC_ICR_IL_MASK (0xC7) |
||||
#define INTC_ICR_IP(x) ((x) & 0x07) |
||||
#define INTC_ICR_IP_MASK (0xF8) |
||||
#else |
||||
#define INTC_ICR_IL(x) ((x) & 0x07) |
||||
#define INTC_ICR_IL_MASK (0xF8) |
||||
#endif |
||||
|
||||
#define INTC_ICONFIG_ELVLPRI_MASK (0x01FF) |
||||
#define INTC_ICONFIG_ELVLPRI7 (0x8000) |
||||
#define INTC_ICONFIG_ELVLPRI6 (0x4000) |
||||
#define INTC_ICONFIG_ELVLPRI5 (0x2000) |
||||
#define INTC_ICONFIG_ELVLPRI4 (0x1000) |
||||
#define INTC_ICONFIG_ELVLPRI3 (0x0800) |
||||
#define INTC_ICONFIG_ELVLPRI2 (0x0400) |
||||
#define INTC_ICONFIG_ELVLPRI1 (0x0200) |
||||
#define INTC_ICONFIG_EMASK (0x0020) |
||||
|
||||
#define INTC_SIMR_ALL (0x40) |
||||
#define INTC_SIMR(x) ((x) & 0x3F) |
||||
#define INTC_SIMR_MASK (0x80) |
||||
|
||||
#define INTC_CIMR_ALL (0x40) |
||||
#define INTC_CIMR(x) ((x) & 0x3F) |
||||
#define INTC_CIMR_MASK (0x80) |
||||
|
||||
#define INTC_CLMASK(x) ((x) & 0x0F) |
||||
#define INTC_CLMASK_MASK (0xF0) |
||||
|
||||
#define INTC_SLMASK(x) ((x) & 0x0F) |
||||
#define INTC_SLMASK_MASK (0xF0) |
||||
|
||||
#endif /* __INTCTRL_H__ */ |
||||
@ -0,0 +1,102 @@ |
||||
/*
|
||||
* Message Digest Hardware Accelerator Memory Map |
||||
* |
||||
* Copyright (C) 2004-2008 Freescale Semiconductor, Inc. |
||||
* TsiChung Liew (Tsi-Chung.Liew@freescale.com) |
||||
* |
||||
* See file CREDITS for list of people who contributed to this |
||||
* project. |
||||
* |
||||
* This program is free software; you can redistribute it and/or |
||||
* modify it under the terms of the GNU General Public License as |
||||
* published by the Free Software Foundation; either version 2 of |
||||
* the License, or (at your option) any later version. |
||||
* |
||||
* This program is distributed in the hope that it will be useful, |
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of |
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
||||
* GNU General Public License for more details. |
||||
* |
||||
* You should have received a copy of the GNU General Public License |
||||
* along with this program; if not, write to the Free Software |
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
||||
* MA 02111-1307 USA |
||||
*/ |
||||
|
||||
#ifndef __MDHA_H__ |
||||
#define __MDHA_H__ |
||||
|
||||
/* Message Digest Hardware Accelerator */ |
||||
typedef struct mdha_ctrl { |
||||
u32 mr; /* 0x00 MDHA Mode */ |
||||
u32 cr; /* 0x04 Control */ |
||||
u32 cmd; /* 0x08 Command */ |
||||
u32 sr; /* 0x0C Status */ |
||||
u32 isr; /* 0x10 Interrupt Status */ |
||||
u32 imr; /* 0x14 Interrupt Mask */ |
||||
u32 dsz; /* 0x1C Data Size */ |
||||
u32 inp; /* 0x20 Input FIFO */ |
||||
u32 res1[3]; /* 0x24 - 0x2F */ |
||||
u32 mda0; /* 0x30 Message Digest AO */ |
||||
u32 mdb0; /* 0x34 Message Digest BO */ |
||||
u32 mdc0; /* 0x38 Message Digest CO */ |
||||
u32 mdd0; /* 0x3C Message Digest DO */ |
||||
u32 mde0; /* 0x40 Message Digest EO */ |
||||
u32 mdsz; /* 0x44 Message Data Size */ |
||||
u32 res[10]; /* 0x48 - 0x6F */ |
||||
u32 mda1; /* 0x70 Message Digest A1 */ |
||||
u32 mdb1; /* 0x74 Message Digest B1 */ |
||||
u32 mdc1; /* 0x78 Message Digest C1 */ |
||||
u32 mdd1; /* 0x7C Message Digest D1 */ |
||||
u32 mde1; /* 0x80 Message Digest E1 */ |
||||
} mdha_t; |
||||
|
||||
#define MDHA_MR_SSL (0x00000400) |
||||
#define MDHA_MR_MACFUL (0x00000200) |
||||
#define MDHA_MR_SWAP (0x00000100) |
||||
#define MDHA_MR_OPAD (0x00000080) |
||||
#define MDHA_MR_IPAD (0x00000040) |
||||
#define MDHA_MR_INIT (0x00000020) |
||||
#define MDHA_MR_MAC(x) (((x) & 0x03) << 3) |
||||
#define MDHA_MR_MAC_MASK (0xFFFFFFE7) |
||||
#define MDHA_MR_MAC_EHMAC (0x00000010) |
||||
#define MDHA_MR_MAC_HMAC (0x00000008) |
||||
#define MDHA_MR_MAC_NONE (0x00000000) |
||||
#define MDHA_MR_PDATA (0x00000004) |
||||
#define MDHA_MR_ALG (0x00000001) |
||||
|
||||
#define MDHA_CR_DMAL(x) (((x) & 0x1F) << 16) /* 532x */ |
||||
#define MDHA_CR_DMAL_MASK (0xFFE0FFFF) /* 532x */ |
||||
#define MDHA_CR_END (0x00000004) /* 532x */ |
||||
#define MDHA_CR_DMA (0x00000002) /* 532x */ |
||||
#define MDHA_CR_IE (0x00000001) |
||||
|
||||
#define MDHA_CMD_GO (0x00000008) |
||||
#define MDHA_CMD_CI (0x00000004) |
||||
#define MDHA_CMD_RI (0x00000001) |
||||
#define MDHA_CMD_SWR (0x00000001) |
||||
|
||||
#define MDHA_SR_IFL(x) (((x) & 0xFF) << 16) |
||||
#define MDHA_SR_IFL_MASK (0xFF00FFFF) |
||||
#define MDHA_SR_APD(x) (((x) & 0x7) << 13) |
||||
#define MDHA_SR_APD_MASK (0xFFFF1FFF) |
||||
#define MDHA_SR_FS(x) (((x) & 0x7) << 8) |
||||
#define MDHA_SR_FS_MASK (0xFFFFF8FF) |
||||
#define MDHA_SR_GNW (0x00000080) |
||||
#define MDHA_SR_HSH (0x00000040) |
||||
#define MDHA_SR_BUSY (0x00000010) |
||||
#define MDHA_SR_RD (0x00000008) |
||||
#define MDHA_SR_ERR (0x00000004) |
||||
#define MDHA_SR_DONE (0x00000002) |
||||
#define MDHA_SR_INT (0x00000001) |
||||
|
||||
#define MDHA_ISR_DRL (0x00000400) /* 532x */ |
||||
#define MDHA_ISR_GTDS (0x00000200) |
||||
#define MDHA_ISR_ERE (0x00000100) |
||||
#define MDHA_ISR_RMDP (0x00000080) |
||||
#define MDHA_ISR_DSE (0x00000020) |
||||
#define MDHA_ISR_IME (0x00000010) |
||||
#define MDHA_ISR_NEIF (0x00000004) |
||||
#define MDHA_ISR_IFO (0x00000001) |
||||
|
||||
#endif /* __MDHA_H__ */ |
||||
@ -0,0 +1,115 @@ |
||||
/*
|
||||
* Pulse Width Modulation Memory Map |
||||
* |
||||
* Copyright (C) 2004-2008 Freescale Semiconductor, Inc. |
||||
* TsiChung Liew (Tsi-Chung.Liew@freescale.com) |
||||
* |
||||
* See file CREDITS for list of people who contributed to this |
||||
* project. |
||||
* |
||||
* This program is free software; you can redistribute it and/or |
||||
* modify it under the terms of the GNU General Public License as |
||||
* published by the Free Software Foundation; either version 2 of |
||||
* the License, or (at your option) any later version. |
||||
* |
||||
* This program is distributed in the hope that it will be useful, |
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of |
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
||||
* GNU General Public License for more details. |
||||
* |
||||
* You should have received a copy of the GNU General Public License |
||||
* along with this program; if not, write to the Free Software |
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
||||
* MA 02111-1307 USA |
||||
*/ |
||||
|
||||
#ifndef __ATA_H__ |
||||
#define __ATA_H__ |
||||
|
||||
/* Pulse Width Modulation (PWM) */ |
||||
typedef struct pwm_ctrl { |
||||
#ifdef CONFIG_M5272 |
||||
u8 cr0; |
||||
u8 res1[3]; |
||||
u8 cr1; |
||||
u8 res2[3]; |
||||
u8 cr2; |
||||
u8 res3[7]; |
||||
u8 pwr0; |
||||
u8 res4[3]; |
||||
u8 pwr1; |
||||
u8 res5[3]; |
||||
u8 pwr2; |
||||
u8 res6[7]; |
||||
#else |
||||
u8 en; /* 0x00 PWM Enable */ |
||||
u8 pol; /* 0x01 Polarity */ |
||||
u8 clk; /* 0x02 Clock Select */ |
||||
u8 prclk; /* 0x03 Prescale Clock Select */ |
||||
u8 cae; /* 0x04 Center Align Enable */ |
||||
u8 ctl; /* 0x05 Control */ |
||||
u16 res1; /* 0x06 - 0x07 */ |
||||
u8 scla; /* 0x08 Scale A */ |
||||
u8 sclb; /* 0x09 Scale B */ |
||||
u16 res2; /* 0x0A - 0x0B */ |
||||
#ifdef CONFIG_M5275 |
||||
u8 cnt[4]; /* 0x0C Channel n Counter */ |
||||
u16 res3; /* 0x10 - 0x11 */ |
||||
u8 per[4]; /* 0x14 Channel n Period */ |
||||
u16 res4; /* 0x16 - 0x17 */ |
||||
u8 dty[4]; /* 0x18 Channel n Duty */ |
||||
#else |
||||
u8 cnt[8]; /* 0x0C Channel n Counter */ |
||||
u8 per[8]; /* 0x14 Channel n Period */ |
||||
u8 dty[8]; /* 0x1C Channel n Duty */ |
||||
u8 sdn; /* 0x24 Shutdown */ |
||||
u8 res3[3]; /* 0x25 - 0x27 */ |
||||
#endif /* CONFIG_M5275 */ |
||||
#endif /* CONFIG_M5272 */ |
||||
} pwm_t; |
||||
|
||||
#ifdef CONFIG_M5272 |
||||
|
||||
#define PWM_CR_EN (0x80) |
||||
#define PWM_CR_FRC1 (0x40) |
||||
#define PWM_CR_LVL (0x20) |
||||
#define PWM_CR_CLKSEL(x) ((x) & 0x0F) |
||||
#define PWM_CR_CLKSEL_MASK (0xF0) |
||||
|
||||
#else |
||||
|
||||
#define PWM_EN_PWMEn(x) (1 << ((x) & 0x07)) |
||||
#define PWM_EN_PWMEn_MASK (0xF0) |
||||
|
||||
#define PWM_POL_PPOLn(x) (1 << ((x) & 0x07)) |
||||
#define PWM_POL_PPOLn_MASK (0xF0) |
||||
|
||||
#define PWM_CLK_PCLKn(x) (1 << ((x) & 0x07)) |
||||
#define PWM_CLK_PCLKn_MASK (0xF0) |
||||
|
||||
#define PWM_PRCLK_PCKB(x) (((x) & 0x07) << 4) |
||||
#define PWM_PRCLK_PCKB_MASK (0x8F) |
||||
#define PWM_PRCLK_PCKA(x) ((x) & 0x07) |
||||
#define PWM_PRCLK_PCKA_MASK (0xF8) |
||||
|
||||
#define PWM_CLK_PCLKn(x) (1 << ((x) & 0x07)) |
||||
#define PWM_CLK_PCLKn_MASK (0xF0) |
||||
|
||||
#define PWM_CTL_CON67 (0x80) |
||||
#define PWM_CTL_CON45 (0x40) |
||||
#define PWM_CTL_CON23 (0x20) |
||||
#define PWM_CTL_CON01 (0x10) |
||||
#define PWM_CTL_PSWAR (0x08) |
||||
#define PWM_CTL_PFRZ (0x04) |
||||
|
||||
#define PWM_SDN_IF (0x80) |
||||
#define PWM_SDN_IE (0x40) |
||||
#define PWM_SDN_RESTART (0x20) |
||||
#define PWM_SDN_LVL (0x10) |
||||
#define PWM_SDN_PWM7IN (0x04) |
||||
#define PWM_SDN_PWM7IL (0x02) |
||||
#define PWM_SDN_SDNEN (0x01) |
||||
|
||||
#endif /* CONFIG_M5272 */ |
||||
|
||||
#endif /* __ATA_H__ */ |
||||
@ -0,0 +1,111 @@ |
||||
/*
|
||||
* Queue Serial Peripheral Interface Memory Map |
||||
* |
||||
* Copyright (C) 2004-2007 Freescale Semiconductor, Inc. |
||||
* TsiChung Liew (Tsi-Chung.Liew@freescale.com) |
||||
* |
||||
* See file CREDITS for list of people who contributed to this |
||||
* project. |
||||
* |
||||
* This program is free software; you can redistribute it and/or |
||||
* modify it under the terms of the GNU General Public License as |
||||
* published by the Free Software Foundation; either version 2 of |
||||
* the License, or (at your option) any later version. |
||||
* |
||||
* This program is distributed in the hope that it will be useful, |
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of |
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
||||
* GNU General Public License for more details. |
||||
* |
||||
* You should have received a copy of the GNU General Public License |
||||
* along with this program; if not, write to the Free Software |
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
||||
* MA 02111-1307 USA |
||||
*/ |
||||
|
||||
#ifndef __QSPI_H__ |
||||
#define __QSPI_H__ |
||||
|
||||
/* QSPI module registers */ |
||||
typedef struct qspi_ctrl { |
||||
u16 mr; /* 0x00 Mode */ |
||||
u16 res1; |
||||
u16 dlyr; /* 0x04 Delay */ |
||||
u16 res2; |
||||
u16 wr; /* 0x08 Wrap */ |
||||
u16 res3; |
||||
u16 ir; /* 0x0C Interrupt */ |
||||
u16 res4; |
||||
u16 ar; /* 0x10 Address */ |
||||
u16 res5; |
||||
u16 dr; /* 0x14 Data */ |
||||
u16 res6; |
||||
} qspi_t; |
||||
|
||||
/* MR */ |
||||
#define QSPI_QMR_MSTR (0x8000) |
||||
#define QSPI_QMR_DOHIE (0x4000) |
||||
#define QSPI_QMR_BITS(x) (((x)&0x000F)<<10) |
||||
#define QSPI_QMR_BITS_MASK (0xC3FF) |
||||
#define QSPI_QMR_BITS_8 (0x2000) |
||||
#define QSPI_QMR_BITS_9 (0x2400) |
||||
#define QSPI_QMR_BITS_10 (0x2800) |
||||
#define QSPI_QMR_BITS_11 (0x2C00) |
||||
#define QSPI_QMR_BITS_12 (0x3000) |
||||
#define QSPI_QMR_BITS_13 (0x3400) |
||||
#define QSPI_QMR_BITS_14 (0x3800) |
||||
#define QSPI_QMR_BITS_15 (0x3C00) |
||||
#define QSPI_QMR_BITS_16 (0x0000) |
||||
#define QSPI_QMR_CPOL (0x0200) |
||||
#define QSPI_QMR_CPHA (0x0100) |
||||
#define QSPI_QMR_BAUD(x) ((x)&0x00FF) |
||||
#define QSPI_QMR_BAUD_MASK (0xFF00) |
||||
|
||||
/* DLYR */ |
||||
#define QSPI_QDLYR_SPE (0x8000) |
||||
#define QSPI_QDLYR_QCD(x) (((x)&0x007F)<<8) |
||||
#define QSPI_QDLYR_QCD_MASK (0x80FF) |
||||
#define QSPI_QDLYR_DTL(x) ((x)&0x00FF) |
||||
#define QSPI_QDLYR_DTL_MASK (0xFF00) |
||||
|
||||
/* WR */ |
||||
#define QSPI_QWR_HALT (0x8000) |
||||
#define QSPI_QWR_WREN (0x4000) |
||||
#define QSPI_QWR_WRTO (0x2000) |
||||
#define QSPI_QWR_CSIV (0x1000) |
||||
#define QSPI_QWR_ENDQP(x) (((x)&0x000F)<<8) |
||||
#define QSPI_QWR_ENDQP_MASK (0xF0FF) |
||||
#define QSPI_QWR_CPTQP(x) (((x)&0x000F)<<4) |
||||
#define QSPI_QWR_CPTQP_MASK (0xFF0F) |
||||
#define QSPI_QWR_NEWQP(x) ((x)&0x000F) |
||||
#define QSPI_QWR_NEWQP_MASK (0xFFF0) |
||||
|
||||
/* IR */ |
||||
#define QSPI_QIR_WCEFB (0x8000) |
||||
#define QSPI_QIR_ABRTB (0x4000) |
||||
#define QSPI_QIR_ABRTL (0x1000) |
||||
#define QSPI_QIR_WCEFE (0x0800) |
||||
#define QSPI_QIR_ABRTE (0x0400) |
||||
#define QSPI_QIR_SPIFE (0x0100) |
||||
#define QSPI_QIR_WCEF (0x0008) |
||||
#define QSPI_QIR_ABRT (0x0004) |
||||
#define QSPI_QIR_SPIF (0x0001) |
||||
|
||||
/* AR */ |
||||
#define QSPI_QAR_ADDR(x) ((x)&0x003F) |
||||
#define QSPI_QAR_ADDR_MASK (0xFFC0) |
||||
#define QSPI_QAR_TRANS (0x0000) |
||||
#define QSPI_QAR_RECV (0x0010) |
||||
#define QSPI_QAR_CMD (0x0020) |
||||
|
||||
/* DR */ |
||||
#define QSPI_QDR_CONT (0x8000) |
||||
#define QSPI_QDR_BITSE (0x4000) |
||||
#define QSPI_QDR_DT (0x2000) |
||||
#define QSPI_QDR_DSCK (0x1000) |
||||
#define QSPI_QDR_QSPI_CS3 (0x0800) |
||||
#define QSPI_QDR_QSPI_CS2 (0x0400) |
||||
#define QSPI_QDR_QSPI_CS1 (0x0200) |
||||
#define QSPI_QDR_QSPI_CS0 (0x0100) |
||||
|
||||
#endif /* __QSPI_H__ */ |
||||
@ -0,0 +1,52 @@ |
||||
/*
|
||||
* RNG Memory Map |
||||
* |
||||
* Copyright (C) 2004-2008 Freescale Semiconductor, Inc. |
||||
* TsiChung Liew (Tsi-Chung.Liew@freescale.com) |
||||
* |
||||
* See file CREDITS for list of people who contributed to this |
||||
* project. |
||||
* |
||||
* This program is free software; you can redistribute it and/or |
||||
* modify it under the terms of the GNU General Public License as |
||||
* published by the Free Software Foundation; either version 2 of |
||||
* the License, or (at your option) any later version. |
||||
* |
||||
* This program is distributed in the hope that it will be useful, |
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of |
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
||||
* GNU General Public License for more details. |
||||
* |
||||
* You should have received a copy of the GNU General Public License |
||||
* along with this program; if not, write to the Free Software |
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
||||
* MA 02111-1307 USA |
||||
*/ |
||||
|
||||
#ifndef __RNG_H__ |
||||
#define __RNG_H__ |
||||
|
||||
/* Random Number Generator */ |
||||
typedef struct rng_ctrl { |
||||
u32 cr; /* 0x00 Control */ |
||||
u32 sr; /* 0x04 Status */ |
||||
u32 er; /* 0x08 Entropy */ |
||||
u32 out; /* 0x0C Output FIFO */ |
||||
} rng_t; |
||||
|
||||
#define RNG_CR_SLM (0x00000010) /* Sleep mode - 5445x */ |
||||
#define RNG_CR_CI (0x00000008) /* Clear interrupt */ |
||||
#define RNG_CR_IM (0x00000004) /* Interrupt mask */ |
||||
#define RNG_CR_HA (0x00000002) /* High assurance */ |
||||
#define RNG_CR_GO (0x00000001) /* Go bit */ |
||||
|
||||
#define RNG_SR_OFS(x) (((x) & 0x000000FF) << 16) |
||||
#define RNG_SR_OFS_MASK (0xFF00FFFF) |
||||
#define RNG_SR_OFL(x) (((x) & 0x000000FF) << 8) |
||||
#define RNG_SR_OFL_MASK (0xFFFF00FF) |
||||
#define RNG_SR_EI (0x00000008) |
||||
#define RNG_SR_FUF (0x00000004) |
||||
#define RNG_SR_LRS (0x00000002) |
||||
#define RNG_SR_SV (0x00000001) |
||||
|
||||
#endif /* __RNG_H__ */ |
||||
@ -0,0 +1,121 @@ |
||||
/*
|
||||
* Symmetric Key Hardware Accelerator Memory Map |
||||
* |
||||
* Copyright (C) 2004-2008 Freescale Semiconductor, Inc. |
||||
* TsiChung Liew (Tsi-Chung.Liew@freescale.com) |
||||
* |
||||
* See file CREDITS for list of people who contributed to this |
||||
* project. |
||||
* |
||||
* This program is free software; you can redistribute it and/or |
||||
* modify it under the terms of the GNU General Public License as |
||||
* published by the Free Software Foundation; either version 2 of |
||||
* the License, or (at your option) any later version. |
||||
* |
||||
* This program is distributed in the hope that it will be useful, |
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of |
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
||||
* GNU General Public License for more details. |
||||
* |
||||
* You should have received a copy of the GNU General Public License |
||||
* along with this program; if not, write to the Free Software |
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
||||
* MA 02111-1307 USA |
||||
*/ |
||||
|
||||
#ifndef __SKHA_H__ |
||||
#define __SKHA_H__ |
||||
|
||||
typedef struct skha_ctrl { |
||||
u32 mr; /* 0x00 Mode */ |
||||
u32 cr; /* 0x04 Control */ |
||||
u32 cmr; /* 0x08 Command */ |
||||
u32 sr; /* 0x0C Status */ |
||||
u32 esr; /* 0x10 Error Status */ |
||||
u32 emr; /* 0x14 Error Status Mask Register) */ |
||||
u32 ksr; /* 0x18 Key Size */ |
||||
u32 dsr; /* 0x1C Data Size */ |
||||
u32 in; /* 0x20 Input FIFO */ |
||||
u32 out; /* 0x24 Output FIFO */ |
||||
u32 res1[2]; /* 0x28 - 0x2F */ |
||||
u32 kdr1; /* 0x30 Key Data 1 */ |
||||
u32 kdr2; /* 0x34 Key Data 2 */ |
||||
u32 kdr3; /* 0x38 Key Data 3 */ |
||||
u32 kdr4; /* 0x3C Key Data 4 */ |
||||
u32 kdr5; /* 0x40 Key Data 5 */ |
||||
u32 kdr6; /* 0x44 Key Data 6 */ |
||||
u32 res2[10]; /* 0x48 - 0x6F */ |
||||
u32 c1; /* 0x70 Context 1 */ |
||||
u32 c2; /* 0x74 Context 2 */ |
||||
u32 c3; /* 0x78 Context 3 */ |
||||
u32 c4; /* 0x7C Context 4 */ |
||||
u32 c5; /* 0x80 Context 5 */ |
||||
u32 c6; /* 0x84 Context 6 */ |
||||
u32 c7; /* 0x88 Context 7 */ |
||||
u32 c8; /* 0x8C Context 8 */ |
||||
u32 c9; /* 0x90 Context 9 */ |
||||
u32 c10; /* 0x94 Context 10 */ |
||||
u32 c11; /* 0x98 Context 11 */ |
||||
u32 c12; /* 0x9C Context 12 - 5235, 5271, 5272 */ |
||||
} skha_t; |
||||
|
||||
#ifdef CONFIG_MCF532x |
||||
#define SKHA_MODE_CTRM(x) (((x) & 0x0F) << 9) |
||||
#define SKHA_MODE_CTRM_MASK (0xFFFFE1FF) |
||||
#define SKHA_MODE_DKP (0x00000100) |
||||
#else |
||||
#define SKHA_MODE_CTRM(x) (((x) & 0x0F) << 8) |
||||
#define SKHA_MODE_CTRM_MASK (0xFFFFF0FF) |
||||
#define SKHA_MODE_DKP (0x00000080) |
||||
#endif |
||||
#define SKHA_MODE_CM(x) (((x) & 0x03) << 3) |
||||
#define SKHA_MODE_CM_MASK (0xFFFFFFE7) |
||||
#define SKHA_MODE_DIR (0x00000004) |
||||
#define SKHA_MODE_ALG(x) ((x) & 0x03) |
||||
#define SKHA_MODE_ALG_MASK (0xFFFFFFFC) |
||||
|
||||
#define SHKA_CR_ODMAL(x) (((x) & 0x3F) << 24) |
||||
#define SHKA_CR_ODMAL_MASK (0xC0FFFFFF) |
||||
#define SHKA_CR_IDMAL(x) (((x) & 0x3F) << 16) |
||||
#define SHKA_CR_IDMAL_MASK (0xFFC0FFFF) |
||||
#define SHKA_CR_END (0x00000008) |
||||
#define SHKA_CR_ODMA (0x00000004) |
||||
#define SHKA_CR_IDMA (0x00000002) |
||||
#define SKHA_CR_IE (0x00000001) |
||||
|
||||
#define SKHA_CMR_GO (0x00000008) |
||||
#define SKHA_CMR_CI (0x00000004) |
||||
#define SKHA_CMR_RI (0x00000002) |
||||
#define SKHA_CMR_SWR (0x00000001) |
||||
|
||||
#define SKHA_SR_OFL(x) (((x) & 0xFF) << 24) |
||||
#define SKHA_SR_OFL_MASK (0x00FFFFFF) |
||||
#define SKHA_SR_IFL(x) (((x) & 0xFF) << 16) |
||||
#define SKHA_SR_IFL_MASK (0xFF00FFFF) |
||||
#define SKHA_SR_AESES(x) (((x) & 0x1F) << 11) |
||||
#define SKHA_SR_AESES_MASK (0xFFFF07FF) |
||||
#define SKHA_SR_DESES(x) (((x) & 0x7) << 8) |
||||
#define SKHA_SR_DESES_MASK (0xFFFFF8FF) |
||||
#define SKHA_SR_BUSY (0x00000010) |
||||
#define SKHA_SR_RD (0x00000008) |
||||
#define SKHA_SR_ERR (0x00000004) |
||||
#define SKHA_SR_DONE (0x00000002) |
||||
#define SKHA_SR_INT (0x00000001) |
||||
|
||||
#define SHKA_ESE_DRL (0x00000800) |
||||
#define SKHA_ESR_KRE (0x00000400) |
||||
#define SKHA_ESR_KPE (0x00000200) |
||||
#define SKHA_ESR_ERE (0x00000100) |
||||
#define SKHA_ESR_RMDP (0x00000080) |
||||
#define SKHA_ESR_KSE (0x00000040) |
||||
#define SKHA_ESR_DSE (0x00000020) |
||||
#define SKHA_ESR_IME (0x00000010) |
||||
#define SKHA_ESR_NEOF (0x00000008) |
||||
#define SKHA_ESR_NEIF (0x00000004) |
||||
#define SKHA_ESR_OFU (0x00000002) |
||||
#define SKHA_ESR_IFO (0x00000001) |
||||
|
||||
#define SKHA_KSR_SZ(x) ((x) & 0x3F) |
||||
#define SKHA_KSR_SZ_MASK (0xFFFFFFC0) |
||||
|
||||
#endif /* __SKHA_H__ */ |
||||
Loading…
Reference in new issue