FTPCI100 is a SoC PCI componenet of Faraday company. Which is usually built into SoC chips for providing embedded PCI functions. Signed-off-by: Gavin Guo <gavinguo@andestech.com> Signed-off-by: Macpaul Lin <macpaul@andestech.com>master
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/*
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* Faraday FTPCI100 PCI Bridge Controller Device Driver Implementation |
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* |
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* Copyright (C) 2011 Andes Technology Corporation |
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* Gavin Guo, Andes Technology Corporation <gavinguo@andestech.com> |
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* Macpaul Lin, Andes Technology Corporation <macpaul@andestech.com> |
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* |
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* This program is free software; you can redistribute it and/or modify |
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* it under the terms of the GNU General Public License as published by |
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* the Free Software Foundation; either version 2 of the License, or |
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* (at your option) any later version. |
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* |
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* This program is distributed in the hope that it will be useful, |
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* but WITHOUT ANY WARRANTY; without even the implied warranty of |
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
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* GNU General Public License for more details. |
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* |
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* You should have received a copy of the GNU General Public License |
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* along with this program; if not, write to the Free Software |
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA |
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*/ |
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#include <common.h> |
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#include <malloc.h> |
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#include <pci.h> |
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#include <asm/io.h> |
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#include <asm/types.h> /* u32, u16.... used by pci.h */ |
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#include "pci_ftpci100.h" |
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struct ftpci100_data { |
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unsigned int reg_base; |
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unsigned int io_base; |
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unsigned int mem_base; |
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unsigned int mmio_base; |
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unsigned int ndevs; |
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}; |
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static struct pci_config devs[FTPCI100_MAX_FUNCTIONS]; |
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static struct pci_controller local_hose; |
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static void setup_pci_bar(unsigned int bus, unsigned int dev, unsigned func, |
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unsigned char header, struct ftpci100_data *priv) |
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{ |
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struct pci_controller *hose = (struct pci_controller *)&local_hose; |
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unsigned int i, tmp32, bar_no, iovsmem = 1; |
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pci_dev_t dev_nu; |
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/* A device is present, add an entry to the array */ |
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devs[priv->ndevs].bus = bus; |
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devs[priv->ndevs].dev = dev; |
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devs[priv->ndevs].func = func; |
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dev_nu = PCI_BDF(bus, dev, func); |
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if ((header & 0x7f) == 0x01) |
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/* PCI-PCI Bridge */ |
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bar_no = 2; |
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else |
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bar_no = 6; |
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/* Allocate address spaces by configuring BARs */ |
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for (i = 0; i < bar_no; i++) { |
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pci_hose_write_config_dword(hose, dev_nu, |
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PCI_BASE_ADDRESS_0 + i * 4, 0xffffffff); |
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pci_hose_read_config_dword(hose, dev_nu, |
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PCI_BASE_ADDRESS_0 + i * 4, &tmp32); |
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if (tmp32 == 0x0) |
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continue; |
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/* IO space */ |
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if (tmp32 & 0x1) { |
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iovsmem = 0; |
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unsigned int size_mask = ~(tmp32 & 0xfffffffc); |
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if (priv->io_base & size_mask) |
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priv->io_base = (priv->io_base & ~size_mask) + \
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size_mask + 1; |
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devs[priv->ndevs].bar[i].addr = priv->io_base; |
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devs[priv->ndevs].bar[i].size = size_mask + 1; |
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pci_hose_write_config_dword(hose, dev_nu, |
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PCI_BASE_ADDRESS_0 + i * 4, |
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priv->io_base); |
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debug("Allocated IO address 0x%X-" \
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"0x%X for Bus %d, Device %d, Function %d\n", |
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priv->io_base, |
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priv->io_base + size_mask, bus, dev, func); |
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priv->io_base += size_mask + 1; |
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} else { |
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/* Memory space */ |
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unsigned int is_64bit = ((tmp32 & 0x6) == 0x4); |
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unsigned int is_pref = tmp32 & 0x8; |
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unsigned int size_mask = ~(tmp32 & 0xfffffff0); |
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unsigned int alloc_base; |
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unsigned int *addr_mem_base; |
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if (is_pref) |
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addr_mem_base = &priv->mem_base; |
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else |
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addr_mem_base = &priv->mmio_base; |
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alloc_base = *addr_mem_base; |
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if (alloc_base & size_mask) |
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alloc_base = (alloc_base & ~size_mask) \
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+ size_mask + 1; |
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pci_hose_write_config_dword(hose, dev_nu, |
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PCI_BASE_ADDRESS_0 + i * 4, alloc_base); |
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debug("Allocated %s address 0x%X-" \
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"0x%X for Bus %d, Device %d, Function %d\n", |
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is_pref ? "MEM" : "MMIO", alloc_base, |
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alloc_base + size_mask, bus, dev, func); |
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devs[priv->ndevs].bar[i].addr = alloc_base; |
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devs[priv->ndevs].bar[i].size = size_mask + 1; |
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debug("BAR address BAR size\n"); |
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debug("%010x %08d\n", |
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devs[priv->ndevs].bar[0].addr, |
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devs[priv->ndevs].bar[0].size); |
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alloc_base += size_mask + 1; |
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*addr_mem_base = alloc_base; |
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if (is_64bit) { |
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i++; |
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pci_hose_write_config_dword(hose, dev_nu, |
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PCI_BASE_ADDRESS_0 + i * 4, 0x0); |
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} |
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} |
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} |
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/* Enable Bus Master, Memory Space, and IO Space */ |
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pci_hose_read_config_dword(hose, dev_nu, PCI_CACHE_LINE_SIZE, &tmp32); |
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pci_hose_write_config_dword(hose, dev_nu, PCI_CACHE_LINE_SIZE, 0x08); |
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pci_hose_read_config_dword(hose, dev_nu, PCI_CACHE_LINE_SIZE, &tmp32); |
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pci_hose_read_config_dword(hose, dev_nu, PCI_COMMAND, &tmp32); |
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tmp32 &= 0xffff; |
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if (iovsmem == 0) |
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tmp32 |= 0x5; |
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else |
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tmp32 |= 0x6; |
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pci_hose_write_config_dword(hose, dev_nu, PCI_COMMAND, tmp32); |
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} |
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static void pci_bus_scan(struct ftpci100_data *priv) |
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{ |
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struct pci_controller *hose = (struct pci_controller *)&local_hose; |
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unsigned int bus, dev, func; |
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pci_dev_t dev_nu; |
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unsigned int data32; |
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unsigned int tmp; |
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unsigned char header; |
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unsigned char int_pin; |
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unsigned int niobars; |
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unsigned int nmbars; |
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priv->ndevs = 1; |
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nmbars = 0; |
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niobars = 0; |
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for (bus = 0; bus < MAX_BUS_NUM; bus++) |
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for (dev = 0; dev < MAX_DEV_NUM; dev++) |
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for (func = 0; func < MAX_FUN_NUM; func++) { |
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dev_nu = PCI_BDF(bus, dev, func); |
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pci_hose_read_config_dword(hose, dev_nu, |
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PCI_VENDOR_ID, &data32); |
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/*
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* some broken boards return 0 or ~0, |
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* if a slot is empty. |
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*/ |
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if (data32 == 0xffffffff || |
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data32 == 0x00000000 || |
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data32 == 0x0000ffff || |
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data32 == 0xffff0000) |
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continue; |
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pci_hose_read_config_dword(hose, dev_nu, |
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PCI_HEADER_TYPE, &tmp); |
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header = (unsigned char)tmp; |
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setup_pci_bar(bus, dev, func, header, priv); |
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devs[priv->ndevs].v_id = (u16)(data32 & \
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0x0000ffff); |
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devs[priv->ndevs].d_id = (u16)((data32 & \
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0xffff0000) >> 16); |
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/* Figure out what INTX# line the card uses */ |
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pci_hose_read_config_byte(hose, dev_nu, |
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PCI_INTERRUPT_PIN, &int_pin); |
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/* assign the appropriate irq line */ |
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if (int_pin > PCI_IRQ_LINES) { |
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printf("more irq lines than expect\n"); |
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} else if (int_pin != 0) { |
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/* This device uses an interrupt line */ |
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devs[priv->ndevs].pin = int_pin; |
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} |
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pci_hose_read_config_dword(hose, dev_nu, |
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PCI_CLASS_DEVICE, &data32); |
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debug("%06d %03d %03d " \
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"%04d %08x %08x " \
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"%03d %08x %06d %08x\n", |
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priv->ndevs, devs[priv->ndevs].bus, |
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devs[priv->ndevs].dev, |
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devs[priv->ndevs].func, |
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devs[priv->ndevs].d_id, |
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devs[priv->ndevs].v_id, |
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devs[priv->ndevs].pin, |
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devs[priv->ndevs].bar[0].addr, |
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devs[priv->ndevs].bar[0].size, |
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data32 >> 8); |
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priv->ndevs++; |
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} |
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} |
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static void ftpci_preinit(struct ftpci100_data *priv) |
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{ |
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struct ftpci100_ahbc *ftpci100; |
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struct pci_controller *hose = (struct pci_controller *)&local_hose; |
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u32 pci_config_addr; |
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u32 pci_config_data; |
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priv->reg_base = CONFIG_FTPCI100_BASE; |
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priv->io_base = CONFIG_FTPCI100_BASE + CONFIG_FTPCI100_IO_SIZE; |
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priv->mmio_base = CONFIG_FTPCI100_MEM_BASE; |
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priv->mem_base = CONFIG_FTPCI100_MEM_BASE + CONFIG_FTPCI100_MEM_SIZE; |
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ftpci100 = (struct ftpci100_ahbc *)priv->reg_base; |
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pci_config_addr = (u32) &ftpci100->conf; |
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pci_config_data = (u32) &ftpci100->data; |
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/* print device name */ |
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printf("FTPCI100\n"); |
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/* dump basic configuration */ |
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debug("%s: Config addr is %08X, data port is %08X\n", |
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__func__, pci_config_addr, pci_config_data); |
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/* PCI memory space */ |
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pci_set_region(hose->regions + 0, |
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CONFIG_PCI_MEM_BUS, |
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CONFIG_PCI_MEM_PHYS, |
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CONFIG_PCI_MEM_SIZE, |
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PCI_REGION_MEM); |
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hose->region_count++; |
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/* PCI IO space */ |
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pci_set_region(hose->regions + 1, |
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CONFIG_PCI_IO_BUS, |
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CONFIG_PCI_IO_PHYS, |
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CONFIG_PCI_IO_SIZE, |
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PCI_REGION_IO); |
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hose->region_count++; |
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#if defined(CONFIG_PCI_SYS_BUS) |
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/* PCI System Memory space */ |
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pci_set_region(hose->regions + 2, |
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CONFIG_PCI_SYS_BUS, |
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CONFIG_PCI_SYS_PHYS, |
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CONFIG_PCI_SYS_SIZE, |
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PCI_REGION_MEM | PCI_REGION_SYS_MEMORY); |
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hose->region_count++; |
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#endif |
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/* setup indirect read/write function */ |
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pci_setup_indirect(hose, pci_config_addr, pci_config_data); |
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/* register hose */ |
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pci_register_hose(hose); |
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} |
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void pci_ftpci_init(void) |
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{ |
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struct ftpci100_data *priv = NULL; |
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struct pci_controller *hose = (struct pci_controller *)&local_hose; |
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pci_dev_t bridge_num; |
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struct pci_device_id bridge_ids[] = { |
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{FTPCI100_BRIDGE_VENDORID, FTPCI100_BRIDGE_DEVICEID}, |
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{0, 0} |
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}; |
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priv = malloc(sizeof(struct ftpci100_data)); |
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if (!priv) { |
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printf("%s(): failed to malloc priv\n", __func__); |
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return; |
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} |
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memset(priv, 0, sizeof(struct ftpci100_data)); |
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ftpci_preinit(priv); |
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debug("Device bus dev func deviceID vendorID pin address" \
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" size class\n"); |
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pci_bus_scan(priv); |
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/*
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* Setup the PCI Bridge Window to 1GB, |
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* it will cause USB OHCI Host controller Unrecoverable Error |
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* if it is not set. |
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*/ |
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bridge_num = pci_find_devices(bridge_ids, 0); |
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if (bridge_num == -1) { |
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printf("PCI Bridge not found\n"); |
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return; |
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} |
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pci_hose_write_config_dword(hose, bridge_num, PCI_MEM_BASE_SIZE1, |
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FTPCI100_BASE_ADR_SIZE(1024)); |
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} |
@ -0,0 +1,94 @@ |
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/*
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* Faraday FTPCI100 PCI Bridge Controller Device Driver Implementation |
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* |
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* Copyright (C) 2010 Andes Technology Corporation |
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* Gavin Guo, Andes Technology Corporation <gavinguo@andestech.com> |
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* Macpaul Lin, Andes Technology Corporation <macpaul@andestech.com> |
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* |
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* This program is free software; you can redistribute it and/or modify |
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* it under the terms of the GNU General Public License as published by |
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* the Free Software Foundation; either version 2 of the License, or |
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* (at your option) any later version. |
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* |
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* This program is distributed in the hope that it will be useful, |
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* but WITHOUT ANY WARRANTY; without even the implied warranty of |
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
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* GNU General Public License for more details. |
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* |
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* You should have received a copy of the GNU General Public License |
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* along with this program; if not, write to the Free Software |
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA |
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*/ |
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#ifndef __FTPCI100_H |
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#define __FTPCI100_H |
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/* AHB Control Registers */ |
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struct ftpci100_ahbc { |
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unsigned int iosize; /* 0x00 - I/O Space Size Signal */ |
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unsigned int prot; /* 0x04 - AHB Protection */ |
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unsigned int rsved[8]; /* 0x08-0x24 - Reserved */ |
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unsigned int conf; /* 0x28 - PCI Configuration */ |
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unsigned int data; /* 0x2c - PCI Configuration DATA */ |
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}; |
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/*
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* FTPCI100_IOSIZE_REG's constant definitions |
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*/ |
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#define FTPCI100_BASE_IO_SIZE(x) (ffs(x) - 1) /* 1M - 2048M */ |
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/*
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* PCI Configuration Register |
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*/ |
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#define PCI_INT_MASK 0x4c |
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#define PCI_MEM_BASE_SIZE1 0x50 |
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#define PCI_MEM_BASE_SIZE2 0x54 |
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#define PCI_MEM_BASE_SIZE3 0x58 |
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/*
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* PCI_INT_MASK's bit definitions |
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*/ |
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#define PCI_INTA_ENABLE (1 << 22) |
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#define PCI_INTB_ENABLE (1 << 23) |
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#define PCI_INTC_ENABLE (1 << 24) |
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#define PCI_INTD_ENABLE (1 << 25) |
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/*
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* PCI_MEM_BASE_SIZE1's constant definitions |
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*/ |
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#define FTPCI100_BASE_ADR_SIZE(x) ((ffs(x) - 1) << 16) /* 1M - 2048M */ |
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#define FTPCI100_MAX_FUNCTIONS 20 |
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#define PCI_IRQ_LINES 4 |
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#define MAX_BUS_NUM 256 |
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#define MAX_DEV_NUM 32 |
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#define MAX_FUN_NUM 8 |
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#define PCI_MAX_BAR_PER_FUNC 6 |
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/*
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* PCI_MEM_SIZE |
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*/ |
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#define FTPCI100_MEM_SIZE(x) (ffs(x) << 24) |
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/* This definition is used by pci_ftpci_init() */ |
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#define FTPCI100_BRIDGE_VENDORID 0x159b |
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#define FTPCI100_BRIDGE_DEVICEID 0x4321 |
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struct pcibar { |
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unsigned int size; |
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unsigned int addr; |
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}; |
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struct pci_config { |
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unsigned int bus; |
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unsigned int dev; /* device */ |
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unsigned int func; |
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unsigned int pin; |
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unsigned short v_id; /* vendor id */ |
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unsigned short d_id; /* device id */ |
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struct pcibar bar[PCI_MAX_BAR_PER_FUNC + 1]; |
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}; |
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#endif |
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Reference in new issue