i2c: sh_i2c.c: support I2C2, I2C3 and I2C4

sh_i2c.c support I2C0 and I2C1. This patch extends it to I2C4.

Acked-by: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
Signed-off-by: Tetsuyuki Kobayashi <koba@kmckk.co.jp>

drivers/i2c/sh_i2c.c

@@ -184,6 +184,21 @@ int i2c_set_bus_num(unsigned int bus)
 	case 1:
 		base = (void *)CONFIG_SH_I2C_BASE1;
 		break;
+#ifdef CONFIG_SH_I2C_BASE2
+	case 2:
+		base = (void *)CONFIG_SH_I2C_BASE2;
+		break;
+#endif
+#ifdef CONFIG_SH_I2C_BASE3
+	case 3:
+		base = (void *)CONFIG_SH_I2C_BASE3;
+		break;
+#endif
+#ifdef CONFIG_SH_I2C_BASE4
+	case 4:
+		base = (void *)CONFIG_SH_I2C_BASE4;
+		break;
+#endif
 	default:
 		return -1;
 	}

include/configs/kzm9g.h

@@ -157,7 +157,7 @@
 #define CONFIG_SH_I2C_8BIT
 #define CONFIG_HARD_I2C
 #define CONFIG_I2C_MULTI_BUS
-#define CONFIG_SYS_MAX_I2C_BUS  (2)
+#define CONFIG_SYS_MAX_I2C_BUS  (5)
 #define CONFIG_SYS_I2C_MODULE
 #define CONFIG_SYS_I2C_SPEED    (100000) /* 100 kHz */
 #define CONFIG_SYS_I2C_SLAVE    (0x7F)
@@ -166,5 +166,8 @@
 #define CONFIG_SH_I2C_CLOCK     (104000000) /* 104 MHz */
 #define CONFIG_SH_I2C_BASE0     (0xE6820000)
 #define CONFIG_SH_I2C_BASE1     (0xE6822000)
+#define CONFIG_SH_I2C_BASE2     (0xE6824000)
+#define CONFIG_SH_I2C_BASE3     (0xE6826000)
+#define CONFIG_SH_I2C_BASE4     (0xE6828000)
 
 #endif /* __KZM9G_H */