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@ -38,63 +38,13 @@ |
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#endif |
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#include <asm/io.h> |
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#include <asm/mmu.h> |
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#include <spd.h> |
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#include <spd_sdram.h> |
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#include <i2c.h> |
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#include <netdev.h> |
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void ddr_enable_ecc(unsigned int dram_size); |
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int fixed_sdram(void) |
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{ |
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volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR; |
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u32 msize = 0; |
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u32 ddr_size; |
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u32 ddr_size_log2; |
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msize = CONFIG_SYS_DDR_SIZE; |
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for (ddr_size = msize << 20, ddr_size_log2 = 0; |
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(ddr_size > 1); |
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ddr_size = ddr_size>>1, ddr_size_log2++) { |
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if (ddr_size & 1) |
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return -1; |
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} |
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im->sysconf.ddrlaw[0].bar = CONFIG_SYS_DDR_SDRAM_BASE & 0xfffff000; |
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im->sysconf.ddrlaw[0].ar = LAWAR_EN | ((ddr_size_log2 - 1) & |
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LAWAR_SIZE); |
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#if (CONFIG_SYS_DDR_SIZE == 512) |
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im->ddr.csbnds[0].csbnds = 0x0000001f; |
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#else |
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#warning Currently any DDR size other than 512MiB is not supported |
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#endif |
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im->ddr.cs_config[0] = CONFIG_SYS_DDR_CONFIG | 0x00330000; |
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/* currently we use only one CS, so disable the other banks */ |
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im->ddr.csbnds[1].csbnds = 0x00000000; |
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im->ddr.csbnds[2].csbnds = 0x00000000; |
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im->ddr.csbnds[3].csbnds = 0x00000000; |
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im->ddr.cs_config[1] = 0; |
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im->ddr.cs_config[2] = 0; |
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im->ddr.cs_config[3] = 0; |
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im->ddr.timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0; |
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im->ddr.timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1; |
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im->ddr.timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2; |
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im->ddr.timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3; |
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im->ddr.sdram_cfg = CONFIG_SYS_DDR_SDRAM_CFG; |
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im->ddr.sdram_cfg2 = CONFIG_SYS_DDR_SDRAM_CFG2; |
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im->ddr.sdram_mode = CONFIG_SYS_DDR_MODE; |
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im->ddr.sdram_mode2 = CONFIG_SYS_DDR_MODE2; |
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im->ddr.sdram_interval = CONFIG_SYS_DDR_INTERVAL; |
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sync(); |
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udelay(200); |
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/* enable DDR controller */ |
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im->ddr.sdram_cfg |= SDRAM_CFG_MEM_EN; |
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return msize; |
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} |
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phys_size_t initdram(int board_type) |
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{ |
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volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR; |
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@ -103,10 +53,10 @@ phys_size_t initdram(int board_type) |
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if ((im->sysconf.immrbar & IMMRBAR_BASE_ADDR) != (u32)im) |
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return -1; |
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/* DDR SDRAM - Main SODIMM */ |
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/* DDR SDRAM - Main memory */ |
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im->sysconf.ddrlaw[0].bar = CONFIG_SYS_DDR_BASE & LAWBAR_BAR; |
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msize = fixed_sdram(); |
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msize = spd_sdram(); |
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#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER) |
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/*
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@ -124,17 +74,148 @@ phys_size_t initdram(int board_type) |
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int checkboard(void) |
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{ |
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puts("Board: esd VME8349\n"); |
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#ifdef VME_CADDY2 |
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puts("Board: esd VME-CADDY/2\n"); |
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#else |
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puts("Board: esd VME-CPU/8349\n"); |
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#endif |
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return 0; |
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} |
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#ifdef VME_CADDY2 |
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int board_eth_init(bd_t *bis) |
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{ |
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return pci_eth_init(bis); |
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} |
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#endif |
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#if defined(CONFIG_OF_BOARD_SETUP) |
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void ft_board_setup(void *blob, bd_t *bd) |
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{ |
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ft_cpu_setup(blob, bd); |
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#ifdef CONFIG_PCI |
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ft_pci_setup(blob, bd); |
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#endif |
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} |
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#endif |
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int misc_init_r() |
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{ |
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immap_t *im = (immap_t *)CONFIG_SYS_IMMR; |
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clrsetbits_be32(&im->lbus.lcrr, LBCR_LDIS, 0); |
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return 0; |
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} |
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/*
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* Provide SPD values for spd_sdram(). Both boards (VME-CADDY/2 |
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* and VME-CADDY/2) have different SDRAM configurations. |
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*/ |
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#ifdef VME_CADDY2 |
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#define SMALL_RAM 0xff |
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#define LARGE_RAM 0x00 |
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#else |
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#define SMALL_RAM 0x00 |
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#define LARGE_RAM 0xff |
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#endif |
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#define SPD_VAL(a, b) (((a) & SMALL_RAM) | ((b) & LARGE_RAM)) |
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static spd_eeprom_t default_spd_eeprom = { |
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SPD_VAL(0x80, 0x80), /* 00 use 128 Bytes */ |
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SPD_VAL(0x07, 0x07), /* 01 use 128 Bytes */ |
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SPD_MEMTYPE_DDR2, /* 02 type is DDR2 */ |
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SPD_VAL(0x0d, 0x0d), /* 03 rows: 13 */ |
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SPD_VAL(0x09, 0x0a), /* 04 cols: 9 / 10 */ |
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SPD_VAL(0x00, 0x00), /* 05 */ |
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SPD_VAL(0x40, 0x40), /* 06 */ |
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SPD_VAL(0x00, 0x00), /* 07 */ |
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SPD_VAL(0x05, 0x05), /* 08 */ |
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SPD_VAL(0x30, 0x30), /* 09 */ |
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SPD_VAL(0x45, 0x45), /* 10 */ |
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SPD_VAL(0x02, 0x02), /* 11 ecc used */ |
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SPD_VAL(0x82, 0x82), /* 12 */ |
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SPD_VAL(0x10, 0x10), /* 13 */ |
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SPD_VAL(0x08, 0x08), /* 14 */ |
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SPD_VAL(0x00, 0x00), /* 15 */ |
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SPD_VAL(0x0c, 0x0c), /* 16 */ |
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SPD_VAL(0x04, 0x08), /* 17 banks: 4 / 8 */ |
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SPD_VAL(0x38, 0x38), /* 18 */ |
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SPD_VAL(0x00, 0x00), /* 19 */ |
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SPD_VAL(0x02, 0x02), /* 20 */ |
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SPD_VAL(0x00, 0x00), /* 21 */ |
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SPD_VAL(0x03, 0x03), /* 22 */ |
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SPD_VAL(0x3d, 0x3d), /* 23 */ |
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SPD_VAL(0x45, 0x45), /* 24 */ |
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SPD_VAL(0x50, 0x50), /* 25 */ |
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SPD_VAL(0x45, 0x45), /* 26 */ |
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SPD_VAL(0x3c, 0x3c), /* 27 */ |
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SPD_VAL(0x28, 0x28), /* 28 */ |
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SPD_VAL(0x3c, 0x3c), /* 29 */ |
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SPD_VAL(0x2d, 0x2d), /* 30 */ |
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SPD_VAL(0x20, 0x80), /* 31 */ |
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SPD_VAL(0x20, 0x20), /* 32 */ |
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SPD_VAL(0x27, 0x27), /* 33 */ |
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SPD_VAL(0x10, 0x10), /* 34 */ |
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SPD_VAL(0x17, 0x17), /* 35 */ |
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SPD_VAL(0x3c, 0x3c), /* 36 */ |
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SPD_VAL(0x1e, 0x1e), /* 37 */ |
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SPD_VAL(0x1e, 0x1e), /* 38 */ |
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SPD_VAL(0x00, 0x00), /* 39 */ |
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SPD_VAL(0x00, 0x06), /* 40 */ |
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SPD_VAL(0x37, 0x37), /* 41 */ |
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SPD_VAL(0x4b, 0x7f), /* 42 */ |
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SPD_VAL(0x80, 0x80), /* 43 */ |
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SPD_VAL(0x18, 0x18), /* 44 */ |
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SPD_VAL(0x22, 0x22), /* 45 */ |
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SPD_VAL(0x00, 0x00), /* 46 */ |
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{ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, |
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SPD_VAL(0x10, 0x10), /* 62 */ |
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SPD_VAL(0x7e, 0x1d), /* 63 */ |
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{ 'e', 's', 'd', '-', 'g', 'm', 'b', 'h' }, |
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SPD_VAL(0x00, 0x00), /* 72 */ |
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#ifdef VME_CADDY2 |
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{ "vme-caddy/2 ram " } |
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#else |
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{ "vme-cpu/2 ram " } |
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#endif |
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}; |
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int vme8349_read_spd(uchar chip, uint addr, int alen, uchar *buffer, int len) |
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{ |
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int old_bus = I2C_GET_BUS(); |
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unsigned int l, sum; |
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int valid = 0; |
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I2C_SET_BUS(0); |
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if (i2c_read(chip, addr, alen, buffer, len) == 0) |
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if (memcmp(&buffer[64], &default_spd_eeprom.mid[0], 8) == 0) { |
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sum = 0; |
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for (l = 0; l < 63; l++) |
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sum = (sum + buffer[l]) & 0xff; |
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if (sum == buffer[63]) |
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valid = 1; |
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else |
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printf("Invalid checksum in EEPROM %02x %02x\n", |
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sum, buffer[63]); |
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} |
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if (valid == 0) { |
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memcpy(buffer, (void *)&default_spd_eeprom, len); |
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sum = 0; |
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for (l = 0; l < 63; l++) |
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sum = (sum + buffer[l]) & 0xff; |
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if (sum != buffer[63]) |
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printf("Invalid checksum in FLASH %02x %02x\n", |
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sum, buffer[63]); |
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buffer[63] = sum; |
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} |
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I2C_SET_BUS(old_bus); |
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return 0; |
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} |
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Wolfgang Denk
15 years ago