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mpc83xx: Add the support of MPC837x SoC

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The MPC837x SoC including e300c4 core and new IP blocks,
such as SDHC, PCI Express and SATA controller.

Signed-off-by: Dave Liu <daveliu@freescale.com>
master
Dave Liu 18 years ago committed by Kim Phillips
parent 651d96f7e4
commit 03051c3d35
5 changed files with 406 additions and 53 deletions
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  1. 24
      cpu/mpc83xx/cpu.c
  2. 167
      cpu/mpc83xx/speed.c
  3. 10
      include/asm-ppc/global_data.h
  4. 84
      include/asm-ppc/immap_83xx.h
  5. 174
      include/mpc83xx.h

24
cpu/mpc83xx/cpu.c
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@ -1,5 +1,5 @@
/*
* Copyright (C) 2004-2006 Freescale Semiconductor, Inc.
* Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
*
* See file CREDITS for list of people who contributed to this
* project.
@ -65,6 +65,10 @@ int checkcpu(void)
printf("e300c3, ");
break;
case PVR_E300C4:
printf("e300c4, ");
break;
default:
printf("Unknown core, ");
}
@ -149,6 +153,24 @@ int checkcpu(void)
case SPR_8313E_REV10:
puts("MPC8313E, ");
break;
case SPR_8379E_REV10:
puts("MPC8379E, ");
break;
case SPR_8379_REV10:
puts("MPC8379, ");
break;
case SPR_8378E_REV10:
puts("MPC8378E, ");
break;
case SPR_8378_REV10:
puts("MPC8378, ");
break;
case SPR_8377E_REV10:
puts("MPC8377E, ");
break;
case SPR_8377_REV10:
puts("MPC8377, ");
break;
default:
printf("Rev: Unknown revision number:%08x\n"
"Warning: Unsupported cpu revision!\n",spridr);

167
cpu/mpc83xx/speed.c
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@ -2,7 +2,7 @@
* (C) Copyright 2000-2002
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* Copyright (C) 2004-2006 Freescale Semiconductor, Inc.
* Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
*
* See file CREDITS for list of people who contributed to this
* project.
@ -100,7 +100,7 @@ int get_clocks(void)
u32 lcrr;
u32 csb_clk;
#if defined(CONFIG_MPC834X) || defined(CONFIG_MPC831X)
#if defined(CONFIG_MPC834X) || defined(CONFIG_MPC831X) || defined(CONFIG_MPC837X)
u32 tsec1_clk;
u32 tsec2_clk;
u32 usbdr_clk;
@ -113,6 +113,9 @@ int get_clocks(void)
#if !defined(CONFIG_MPC832X)
u32 i2c2_clk;
#endif
#if defined(CONFIG_MPC837X)
u32 sdhc_clk;
#endif
u32 enc_clk;
u32 lbiu_clk;
u32 lclk_clk;
@ -126,6 +129,11 @@ int get_clocks(void)
u32 qe_clk;
u32 brg_clk;
#endif
#if defined(CONFIG_MPC837X)
u32 pciexp1_clk;
u32 pciexp2_clk;
u32 sata_clk;
#endif
if ((im->sysconf.immrbar & IMMRBAR_BASE_ADDR) != (u32) im)
return -1;
@ -151,7 +159,7 @@ int get_clocks(void)
sccr = im->clk.sccr;
#if defined(CONFIG_MPC834X) || defined(CONFIG_MPC831X)
#if defined(CONFIG_MPC834X) || defined(CONFIG_MPC831X) || defined(CONFIG_MPC837X)
switch ((sccr & SCCR_TSEC1CM) >> SCCR_TSEC1CM_SHIFT) {
case 0:
tsec1_clk = 0;
@ -167,7 +175,7 @@ int get_clocks(void)
break;
default:
/* unkown SCCR_TSEC1CM value */
return -4;
return -2;
}
switch ((sccr & SCCR_USBDRCM) >> SCCR_USBDRCM_SHIFT) {
@ -185,11 +193,11 @@ int get_clocks(void)
break;
default:
/* unkown SCCR_USBDRCM value */
return -8;
return -3;
}
#endif
#if defined(CONFIG_MPC834X)
#if defined(CONFIG_MPC834X) || defined(CONFIG_MPC837X)
switch ((sccr & SCCR_TSEC2CM) >> SCCR_TSEC2CM_SHIFT) {
case 0:
tsec2_clk = 0;
@ -205,11 +213,18 @@ int get_clocks(void)
break;
default:
/* unkown SCCR_TSEC2CM value */
return -5;
return -4;
}
#elif defined(CONFIG_MPC831X)
tsec2_clk = tsec1_clk;
i2c1_clk = tsec2_clk;
if (!(sccr & SCCR_TSEC1ON))
tsec1_clk = 0;
if (!(sccr & SCCR_TSEC2ON))
tsec2_clk = 0;
#endif
#if defined(CONFIG_MPC834X)
switch ((sccr & SCCR_USBMPHCM) >> SCCR_USBMPHCM_SHIFT) {
case 0:
usbmph_clk = 0;
@ -225,7 +240,7 @@ int get_clocks(void)
break;
default:
/* unkown SCCR_USBMPHCM value */
return -7;
return -5;
}
if (usbmph_clk != 0 && usbdr_clk != 0 && usbmph_clk != usbdr_clk) {
@ -233,42 +248,120 @@ int get_clocks(void)
* USB DR clock is not disabled then
* USB MPH & USB DR must have the same rate
*/
return -9;
return -6;
}
#endif
switch ((sccr & SCCR_ENCCM) >> SCCR_ENCCM_SHIFT) {
case 0:
enc_clk = 0;
break;
case 1:
enc_clk = csb_clk;
break;
case 2:
enc_clk = csb_clk / 2;
break;
case 3:
enc_clk = csb_clk / 3;
break;
default:
/* unkown SCCR_ENCCM value */
return -7;
}
#elif defined(CONFIG_MPC831X)
tsec2_clk = tsec1_clk;
if (!(sccr & SCCR_TSEC1ON))
tsec1_clk = 0;
if (!(sccr & SCCR_TSEC2ON))
tsec2_clk = 0;
#if defined(CONFIG_MPC837X)
switch ((sccr & SCCR_SDHCCM) >> SCCR_SDHCCM_SHIFT) {
case 0:
sdhc_clk = 0;
break;
case 1:
sdhc_clk = csb_clk;
break;
case 2:
sdhc_clk = csb_clk / 2;
break;
case 3:
sdhc_clk = csb_clk / 3;
break;
default:
/* unkown SCCR_SDHCCM value */
return -8;
}
#endif
#if !defined(CONFIG_MPC834X)
#if defined(CONFIG_MPC834X)
i2c1_clk = tsec2_clk;
#elif defined(CONFIG_MPC8360)
i2c1_clk = csb_clk;
#elif defined(CONFIG_MPC832X)
i2c1_clk = enc_clk;
#elif defined(CONFIG_MPC831X)
i2c1_clk = enc_clk;
#elif defined(CONFIG_MPC837X)
i2c1_clk = sdhc_clk;
#endif
#if !defined(CONFIG_MPC832X)
i2c2_clk = csb_clk; /* i2c-2 clk is equal to csb clk */
i2c2_clk = csb_clk; /* i2c-2 clk is equal to csb clk */
#endif
switch ((sccr & SCCR_ENCCM) >> SCCR_ENCCM_SHIFT) {
#if defined(CONFIG_MPC837X)
switch ((sccr & SCCR_PCIEXP1CM) >> SCCR_PCIEXP1CM_SHIFT) {
case 0:
enc_clk = 0;
pciexp1_clk = 0;
break;
case 1:
enc_clk = csb_clk;
pciexp1_clk = csb_clk;
break;
case 2:
enc_clk = csb_clk / 2;
pciexp1_clk = csb_clk / 2;
break;
case 3:
enc_clk = csb_clk / 3;
pciexp1_clk = csb_clk / 3;
break;
default:
/* unkown SCCR_ENCCM value */
return -6;
/* unkown SCCR_PCIEXP1CM value */
return -9;
}
switch ((sccr & SCCR_PCIEXP2CM) >> SCCR_PCIEXP2CM_SHIFT) {
case 0:
pciexp2_clk = 0;
break;
case 1:
pciexp2_clk = csb_clk;
break;
case 2:
pciexp2_clk = csb_clk / 2;
break;
case 3:
pciexp2_clk = csb_clk / 3;
break;
default:
/* unkown SCCR_PCIEXP2CM value */
return -10;
}
#endif
#if defined(CONFIG_MPC837X)
switch ((sccr & SCCR_SATA1CM) >> SCCR_SATA1CM_SHIFT) {
case 0:
sata_clk = 0;
break;
case 1:
sata_clk = csb_clk;
break;
case 2:
sata_clk = csb_clk / 2;
break;
case 3:
sata_clk = csb_clk / 3;
break;
default:
/* unkown SCCR_SATA1CM value */
return -11;
}
#endif
lbiu_clk = csb_clk *
(1 + ((im->reset.rcwl & HRCWL_LBIUCM) >> HRCWL_LBIUCM_SHIFT));
lcrr = (im->lbus.lcrr & LCRR_CLKDIV) >> LCRR_CLKDIV_SHIFT;
@ -280,7 +373,7 @@ int get_clocks(void)
break;
default:
/* unknown lcrr */
return -10;
return -12;
}
ddr_clk = csb_clk *
@ -316,7 +409,7 @@ int get_clocks(void)
break;
default:
/* unkown core to csb ratio */
return -12;
return -13;
}
#if defined(CONFIG_MPC8360) || defined(CONFIG_MPC832X)
@ -327,7 +420,7 @@ int get_clocks(void)
#endif
gd->csb_clk = csb_clk;
#if defined(CONFIG_MPC834X) || defined(CONFIG_MPC831X)
#if defined(CONFIG_MPC834X) || defined(CONFIG_MPC831X) || defined(CONFIG_MPC837X)
gd->tsec1_clk = tsec1_clk;
gd->tsec2_clk = tsec2_clk;
gd->usbdr_clk = usbdr_clk;
@ -335,6 +428,9 @@ int get_clocks(void)
#if defined(CONFIG_MPC834X)
gd->usbmph_clk = usbmph_clk;
#endif
#if defined(CONFIG_MPC837X)
gd->sdhc_clk = sdhc_clk;
#endif
gd->core_clk = core_clk;
gd->i2c1_clk = i2c1_clk;
#if !defined(CONFIG_MPC832X)
@ -351,6 +447,11 @@ int get_clocks(void)
gd->qe_clk = qe_clk;
gd->brg_clk = brg_clk;
#endif
#if defined(CONFIG_MPC837X)
gd->pciexp1_clk = pciexp1_clk;
gd->pciexp2_clk = pciexp2_clk;
gd->sata_clk = sata_clk;
#endif
gd->pci_clk = pci_sync_in;
gd->cpu_clk = gd->core_clk;
gd->bus_clk = gd->csb_clk;
@ -387,7 +488,10 @@ int do_clocks (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[])
#if !defined(CONFIG_MPC832X)
printf(" I2C2: %4d MHz\n", gd->i2c2_clk / 1000000);
#endif
#if defined(CONFIG_MPC834X) || defined(CONFIG_MPC831X)
#if defined(CONFIG_MPC837X)
printf(" SDHC: %4d MHz\n", gd->sdhc_clk / 1000000);
#endif
#if defined(CONFIG_MPC834X) || defined(CONFIG_MPC831X) || defined(CONFIG_MPC837X)
printf(" TSEC1: %4d MHz\n", gd->tsec1_clk / 1000000);
printf(" TSEC2: %4d MHz\n", gd->tsec2_clk / 1000000);
printf(" USB DR: %4d MHz\n", gd->usbdr_clk / 1000000);
@ -395,6 +499,11 @@ int do_clocks (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[])
#if defined(CONFIG_MPC834X)
printf(" USB MPH: %4d MHz\n", gd->usbmph_clk / 1000000);
#endif
#if defined(CONFIG_MPC837X)
printf(" PCIEXP1: %4d MHz\n", gd->pciexp1_clk / 1000000);
printf(" PCIEXP2: %4d MHz\n", gd->pciexp2_clk / 1000000);
printf(" SATA: %4d MHz\n", gd->sata_clk / 1000000);
#endif
return 0;
}

10
include/asm-ppc/global_data.h
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@ -55,7 +55,7 @@ typedef struct global_data {
#if defined(CONFIG_MPC83XX)
/* There are other clocks in the MPC83XX */
u32 csb_clk;
#if defined (CONFIG_MPC834X) || defined(CONFIG_MPC831X)
#if defined(CONFIG_MPC834X) || defined(CONFIG_MPC831X) || defined(CONFIG_MPC837X)
u32 tsec1_clk;
u32 tsec2_clk;
u32 usbdr_clk;
@ -63,6 +63,9 @@ typedef struct global_data {
#if defined (CONFIG_MPC834X)
u32 usbmph_clk;
#endif /* CONFIG_MPC834X */
#if defined(CONFIG_MPC837X)
u32 sdhc_clk;
#endif
u32 core_clk;
u32 i2c1_clk;
u32 i2c2_clk;
@ -71,6 +74,11 @@ typedef struct global_data {
u32 lclk_clk;
u32 ddr_clk;
u32 pci_clk;
#if defined(CONFIG_MPC837X)
u32 pciexp1_clk;
u32 pciexp2_clk;
u32 sata_clk;
#endif
#if defined(CONFIG_MPC8360)
u32 ddr_sec_clk;
#endif /* CONFIG_MPC8360 */

84
include/asm-ppc/immap_83xx.h
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@ -1,5 +1,5 @@
/*
* (C) Copyright 2004-2006 Freescale Semiconductor, Inc.
* (C) Copyright 2004-2007 Freescale Semiconductor, Inc.
*
* MPC83xx Internal Memory Map
*
@ -63,7 +63,8 @@ typedef struct sysconf83xx {
u8 res6[0x0C];
u32 ddrcdr; /* DDR Control Driver Register */
u32 ddrdsr; /* DDR Debug Status Register */
u8 res7[0xD0];
u32 obir; /* Output Buffer Impedance Register */
u8 res7[0xCC];
} sysconf83xx_t;
/*
@ -553,6 +554,41 @@ typedef struct security83xx {
u8 fixme[0x10000];
} security83xx_t;
/*
* PCI Express
*/
typedef struct pex83xx {
u8 fixme[0x1000];
} pex83xx_t;
/*
* SATA
*/
typedef struct sata83xx {
u8 fixme[0x1000];
} sata83xx_t;
/*
* eSDHC
*/
typedef struct sdhc83xx {
u8 fixme[0x1000];
} sdhc83xx_t;
/*
* SerDes
*/
typedef struct serdes83xx {
u8 fixme[0x100];
} serdes83xx_t;
/*
* On Chip ROM
*/
typedef struct rom83xx {
u8 mem[0x10000];
} rom83xx_t;
#if defined(CONFIG_MPC834X)
typedef struct immap {
sysconf83xx_t sysconf; /* System configuration */
@ -625,6 +661,50 @@ typedef struct immap {
u8 res7[0xC0000];
} immap_t;
#elif defined(CONFIG_MPC837X)
typedef struct immap {
sysconf83xx_t sysconf; /* System configuration */
wdt83xx_t wdt; /* Watch Dog Timer (WDT) Registers */
rtclk83xx_t rtc; /* Real Time Clock Module Registers */
rtclk83xx_t pit; /* Periodic Interval Timer */
gtm83xx_t gtm[2]; /* Global Timers Module */
ipic83xx_t ipic; /* Integrated Programmable Interrupt Controller */
arbiter83xx_t arbiter; /* System Arbiter Registers */
reset83xx_t reset; /* Reset Module */
clk83xx_t clk; /* System Clock Module */
pmc83xx_t pmc; /* Power Management Control Module */
gpio83xx_t gpio[2]; /* General purpose I/O module */
u8 res0[0x1200];
ddr83xx_t ddr; /* DDR Memory Controller Memory */
fsl_i2c_t i2c[2]; /* I2C Controllers */
u8 res1[0x1300];
duart83xx_t duart[2]; /* DUART */
u8 res2[0x900];
lbus83xx_t lbus; /* Local Bus Controller Registers */
u8 res3[0x1000];
spi83xx_t spi; /* Serial Peripheral Interface */
dma83xx_t dma; /* DMA */
pciconf83xx_t pci_conf[1]; /* PCI Software Configuration Registers */
u8 res4[0x80];
ios83xx_t ios; /* Sequencer */
pcictrl83xx_t pci_ctrl[1]; /* PCI Controller Control and Status Registers */
u8 res5[0xa00];
pex83xx_t pciexp[2]; /* PCI Express Controller */
u8 res6[0xd000];
sata83xx_t sata[4]; /* SATA Controller */
u8 res7[0x7000];
usb83xx_t usb[1]; /* USB DR Controller */
tsec83xx_t tsec[2];
u8 res8[0x8000];
sdhc83xx_t sdhc; /* SDHC Controller */
u8 res9[0x1000];
security83xx_t security;
u8 res10[0xA3000];
serdes83xx_t serdes[2]; /* SerDes Registers */
u8 res11[0xCE00];
rom83xx_t rom; /* On Chip ROM */
} immap_t;
#elif defined(CONFIG_MPC8360)
typedef struct immap {
sysconf83xx_t sysconf; /* System configuration */

174
include/mpc83xx.h
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@ -1,5 +1,5 @@
/*
* Copyright (C) 2004-2006 Freescale Semiconductor, Inc.
* Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
*
* See file CREDITS for list of people who contributed to this
* project.
@ -98,10 +98,17 @@
#define SPR_8321E_REV11 0x80660011
#define SPR_8321_REV11 0x80670011
#define SPR_8311_REV10 0x80B30010
#define SPR_8311E_REV10 0x80B20010
#define SPR_8313_REV10 0x80B10010
#define SPR_8313E_REV10 0x80B00010
#define SPR_8313_REV10 0x80B10010
#define SPR_8311E_REV10 0x80B20010
#define SPR_8311_REV10 0x80B30010
#define SPR_8379E_REV10 0x80C20010
#define SPR_8379_REV10 0x80C30010
#define SPR_8378E_REV10 0x80C40010
#define SPR_8378_REV10 0x80C50010
#define SPR_8377E_REV10 0x80C60010
#define SPR_8377_REV10 0x80C70010
/* SPCR - System Priority Configuration Register
*/
@ -130,8 +137,8 @@
#define SPCR_TSEC2EP 0x00000003 /* TSEC2 emergency priority */
#define SPCR_TSEC2EP_SHIFT (31-31)
#elif defined(CONFIG_MPC831X)
/* SPCR bits - MPC831x specific */
#elif defined(CONFIG_MPC831X) || defined(CONFIG_MPC837X)
/* SPCR bits - MPC831x and MPC837x specific */
#define SPCR_TSECDP 0x00003000 /* TSEC data priority */
#define SPCR_TSECDP_SHIFT (31-19)
#define SPCR_TSECEP 0x00000C00 /* TSEC emergency priority */
@ -242,6 +249,55 @@
#define SICRH_TSOBI1 0x00000002
#define SICRH_TSOBI2 0x00000001
#elif defined(CONFIG_MPC837X)
/* SICRL bits - MPC837x specific */
#define SICRL_USB_A 0xC0000000
#define SICRL_USB_B 0x30000000
#define SICRL_UART 0x0C000000
#define SICRL_GPIO_A 0x02000000
#define SICRL_GPIO_B 0x01000000
#define SICRL_GPIO_C 0x00800000
#define SICRL_GPIO_D 0x00400000
#define SICRL_GPIO_E 0x00200000
#define SICRL_GPIO_F 0x00180000
#define SICRL_GPIO_G 0x00040000
#define SICRL_GPIO_H 0x00020000
#define SICRL_GPIO_I 0x00010000
#define SICRL_GPIO_J 0x00008000
#define SICRL_GPIO_K 0x00004000
#define SICRL_GPIO_L 0x00003000
#define SICRL_DMA_A 0x00000800
#define SICRL_DMA_B 0x00000400
#define SICRL_DMA_C 0x00000200
#define SICRL_DMA_D 0x00000100
#define SICRL_DMA_E 0x00000080
#define SICRL_DMA_F 0x00000040
#define SICRL_DMA_G 0x00000020
#define SICRL_DMA_H 0x00000010
#define SICRL_DMA_I 0x00000008
#define SICRL_DMA_J 0x00000004
#define SICRL_LDP_A 0x00000002
#define SICRL_LDP_B 0x00000001
/* SICRH bits - MPC837x specific */
#define SICRH_DDR 0x80000000
#define SICRH_TSEC1_A 0x10000000
#define SICRH_TSEC1_B 0x08000000
#define SICRH_TSEC2_A 0x00400000
#define SICRH_TSEC2_B 0x00200000
#define SICRH_TSEC2_C 0x00100000
#define SICRH_TSEC2_D 0x00080000
#define SICRH_TSEC2_E 0x00040000
#define SICRH_TMR 0x00010000
#define SICRH_GPIO2_A 0x00008000
#define SICRH_GPIO2_B 0x00004000
#define SICRH_GPIO2_C 0x00002000
#define SICRH_GPIO2_D 0x00001000
#define SICRH_GPIO2_E 0x00000C00
#define SICRH_GPIO2_F 0x00000300
#define SICRH_GPIO2_G 0x000000C0
#define SICRH_GPIO2_H 0x00000030
#define SICRH_SPI 0x00000003
#endif
/* SWCRR - System Watchdog Control Register
@ -390,6 +446,14 @@
#define HRCWL_CE_TO_PLL_1X29 0x0000001D
#define HRCWL_CE_TO_PLL_1X30 0x0000001E
#define HRCWL_CE_TO_PLL_1X31 0x0000001F
#elif defined(CONFIG_MPC837X)
#define HRCWL_SVCOD 0x30000000
#define HRCWL_SVCOD_SHIFT 28
#define HRCWL_SVCOD_DIV_4 0x00000000
#define HRCWL_SVCOD_DIV_8 0x10000000
#define HRCWL_SVCOD_DIV_2 0x20000000
#define HRCWL_SVCOD_DIV_1 0x30000000
#endif
/* HRCWH - Hardware Reset Configuration Word High
@ -436,11 +500,14 @@
#if defined(CONFIG_MPC834X)
#define HRCWH_ROM_LOC_PCI2 0x00200000
#endif
#if defined(CONIFG_MPC837X)
#define HRCWH_ROM_LOC_ON_CHIP_ROM 0x00300000
#endif
#define HRCWH_ROM_LOC_LOCAL_8BIT 0x00500000
#define HRCWH_ROM_LOC_LOCAL_16BIT 0x00600000
#define HRCWH_ROM_LOC_LOCAL_32BIT 0x00700000
#if defined(CONFIG_MPC831X)
#if defined(CONFIG_MPC831X) || defined(CONFIG_MPC837X)
#define HRCWH_ROM_LOC_NAND_SP_8BIT 0x00100000
#define HRCWH_ROM_LOC_NAND_SP_16BIT 0x00200000
#define HRCWH_ROM_LOC_NAND_LP_8BIT 0x00500000
@ -489,8 +556,13 @@
/* RSR - Reset Status Register
*/
#if defined(CONFIG_MPC837X)
#define RSR_RSTSRC 0xF0000000 /* Reset source */
#define RSR_RSTSRC_SHIFT 28
#else
#define RSR_RSTSRC 0xE0000000 /* Reset source */
#define RSR_RSTSRC_SHIFT 29
#endif
#define RSR_BSF 0x00010000 /* Boot seq. fail */
#define RSR_BSF_SHIFT 16
#define RSR_SWSR 0x00002000 /* software soft reset */
@ -577,8 +649,8 @@
#define SCCR_PCICM 0x00010000
#define SCCR_PCICM_SHIFT 16
/* SCCR bits - MPC8349 specific */
#ifdef CONFIG_MPC834X
#if defined(CONFIG_MPC834X)
/* SCCR bits - MPC834x specific */
#define SCCR_TSEC1CM 0xc0000000
#define SCCR_TSEC1CM_SHIFT 30
#define SCCR_TSEC1CM_0 0x00000000
@ -593,6 +665,18 @@
#define SCCR_TSEC2CM_2 0x20000000
#define SCCR_TSEC2CM_3 0x30000000
/* The MPH must have the same clock ratio as DR, unless its clock disabled */
#define SCCR_USBMPHCM 0x00c00000
#define SCCR_USBMPHCM_SHIFT 22
#define SCCR_USBDRCM 0x00300000
#define SCCR_USBDRCM_SHIFT 20
#define SCCR_USBCM 0x00f00000
#define SCCR_USBCM_SHIFT 20
#define SCCR_USBCM_0 0x00000000
#define SCCR_USBCM_1 0x00500000
#define SCCR_USBCM_2 0x00A00000
#define SCCR_USBCM_3 0x00F00000
#elif defined(CONFIG_MPC831X)
/* TSEC1 bits are for TSEC2 as well */
#define SCCR_TSEC1CM 0xc0000000
@ -606,17 +690,67 @@
#define SCCR_TSEC2ON 0x10000000
#define SCCR_TSEC2ON_SHIFT 28
#endif
#define SCCR_USBMPHCM 0x00c00000
#define SCCR_USBMPHCM_SHIFT 22
#define SCCR_USBDRCM 0x00300000
#define SCCR_USBDRCM_SHIFT 20
#define SCCR_USBDRCM_0 0x00000000
#define SCCR_USBDRCM_1 0x00100000
#define SCCR_USBDRCM_2 0x00200000
#define SCCR_USBDRCM_3 0x00300000
#define SCCR_USBCM_0 0x00000000
#define SCCR_USBCM_1 0x00500000
#define SCCR_USBCM_2 0x00A00000
#define SCCR_USBCM_3 0x00F00000
#elif defined(CONFIG_MPC837X)
/* SCCR bits - MPC837x specific */
#define SCCR_TSEC1CM 0xc0000000
#define SCCR_TSEC1CM_SHIFT 30
#define SCCR_TSEC1CM_0 0x00000000
#define SCCR_TSEC1CM_1 0x40000000
#define SCCR_TSEC1CM_2 0x80000000
#define SCCR_TSEC1CM_3 0xC0000000
#define SCCR_TSEC2CM 0x30000000
#define SCCR_TSEC2CM_SHIFT 28
#define SCCR_TSEC2CM_0 0x00000000
#define SCCR_TSEC2CM_1 0x10000000
#define SCCR_TSEC2CM_2 0x20000000
#define SCCR_TSEC2CM_3 0x30000000
#define SCCR_SDHCCM 0x0c000000
#define SCCR_SDHCCM_SHIFT 26
#define SCCR_SDHCCM_0 0x00000000
#define SCCR_SDHCCM_1 0x04000000
#define SCCR_SDHCCM_2 0x08000000
#define SCCR_SDHCCM_3 0x0c000000
#define SCCR_USBDRCM 0x00c00000
#define SCCR_USBDRCM_SHIFT 22
#define SCCR_USBDRCM_0 0x00000000
#define SCCR_USBDRCM_1 0x00400000
#define SCCR_USBDRCM_2 0x00800000
#define SCCR_USBDRCM_3 0x00c00000
#define SCCR_PCIEXP1CM 0x00300000
#define SCCR_PCIEXP1CM_SHIFT 20
#define SCCR_PCIEXP1CM_0 0x00000000
#define SCCR_PCIEXP1CM_1 0x00100000
#define SCCR_PCIEXP1CM_2 0x00200000
#define SCCR_PCIEXP1CM_3 0x00300000
#define SCCR_PCIEXP2CM 0x000c0000
#define SCCR_PCIEXP2CM_SHIFT 18
#define SCCR_PCIEXP2CM_0 0x00000000
#define SCCR_PCIEXP2CM_1 0x00040000
#define SCCR_PCIEXP2CM_2 0x00080000
#define SCCR_PCIEXP2CM_3 0x000c0000
/* All of the four SATA controllers must have the same clock ratio */
#define SCCR_SATA1CM 0x000000c0
#define SCCR_SATA1CM_SHIFT 6
#define SCCR_SATACM 0x000000ff
#define SCCR_SATACM_SHIFT 0
#define SCCR_SATACM_0 0x00000000
#define SCCR_SATACM_1 0x00000055
#define SCCR_SATACM_2 0x000000aa
#define SCCR_SATACM_3 0x000000ff
#endif
/* CSn_BDNS - Chip Select memory Bounds Register
*/
@ -860,7 +994,7 @@
#define BR_MS_UPMA 0x00000080 /* UPMA */
#define BR_MS_UPMB 0x000000A0 /* UPMB */
#define BR_MS_UPMC 0x000000C0 /* UPMC */
#if defined(CONFIG_MPC8360) || defined(CONFIG_MPC832X)
#if !defined(CONFIG_MPC834X)
#define BR_ATOM 0x0000000C
#define BR_ATOM_SHIFT 2
#endif
@ -869,7 +1003,7 @@
#if defined(CONFIG_MPC834X)
#define BR_RES ~(BR_BA | BR_PS | BR_DECC | BR_WP | BR_MSEL | BR_V)
#elif defined(CONFIG_MPC8360)
#else
#define BR_RES ~(BR_BA | BR_PS | BR_DECC | BR_WP | BR_MSEL | BR_ATOM | BR_V)
#endif
@ -1255,7 +1389,7 @@
#define LTESR_CS 0x00080000
#define LTESR_CC 0x00000001
/* DDR Control Driver Register
/* DDRCDR - DDR Control Driver Register
*/
#define DDRCDR_EN 0x40000000
#define DDRCDR_PZ 0x3C000000

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