Tom Rini
10 years ago
commit
03a3536c7b
@ -0,0 +1,304 @@ |
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/dts-v1/; |
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|
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#include "tegra30.dtsi" |
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|
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/ { |
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model = "Toradex Apalis T30"; |
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compatible = "toradex,apalis_t30", "nvidia,tegra30"; |
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|
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chosen { |
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stdout-path = &uarta; |
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}; |
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|
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aliases { |
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i2c0 = "/i2c@7000d000"; |
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i2c1 = "/i2c@7000c000"; |
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i2c2 = "/i2c@7000c500"; |
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i2c3 = "/i2c@7000c700"; |
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sdhci0 = "/sdhci@78000600"; |
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sdhci1 = "/sdhci@78000400"; |
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sdhci2 = "/sdhci@78000000"; |
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usb0 = "/usb@7d000000"; |
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usb1 = "/usb@7d004000"; |
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usb2 = "/usb@7d008000"; |
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}; |
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|
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memory { |
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device_type = "memory"; |
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reg = <0x80000000 0x40000000>; |
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}; |
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|
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pcie-controller@00003000 { |
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status = "okay"; |
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avdd-pexa-supply = <&vdd2_reg>; |
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vdd-pexa-supply = <&vdd2_reg>; |
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avdd-pexb-supply = <&vdd2_reg>; |
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vdd-pexb-supply = <&vdd2_reg>; |
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avdd-pex-pll-supply = <&vdd2_reg>; |
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avdd-plle-supply = <&ldo6_reg>; |
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vddio-pex-ctl-supply = <&sys_3v3_reg>; |
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hvdd-pex-supply = <&sys_3v3_reg>; |
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|
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pci@1,0 { |
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nvidia,num-lanes = <4>; |
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}; |
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|
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pci@2,0 { |
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nvidia,num-lanes = <1>; |
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}; |
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|
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pci@3,0 { |
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status = "okay"; |
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nvidia,num-lanes = <1>; |
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}; |
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}; |
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|
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/* |
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* GEN1_I2C: I2C1_SDA/SCL on MXM3 pin 209/211 (e.g. RTC on carrier |
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* board) |
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*/ |
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i2c@7000c000 { |
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status = "okay"; |
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clock-frequency = <100000>; |
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}; |
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|
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/* GEN2_I2C: unused */ |
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/* |
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* CAM_I2C: I2C3_SDA/SCL on MXM3 pin 201/203 (e.g. camera sensor on |
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* carrier board) |
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*/ |
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i2c@7000c500 { |
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status = "okay"; |
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clock-frequency = <100000>; |
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}; |
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|
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/* DDC: I2C2_SDA/SCL on MXM3 pin 205/207 (e.g. display EDID) */ |
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i2c@7000c700 { |
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status = "okay"; |
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clock-frequency = <100000>; |
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}; |
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|
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/* |
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* PWR_I2C: power I2C to audio codec, PMIC, temperature sensor and |
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* touch screen controller |
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*/ |
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i2c@7000d000 { |
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status = "okay"; |
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clock-frequency = <100000>; |
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pmic: tps65911@2d { |
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compatible = "ti,tps65911"; |
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reg = <0x2d>; |
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|
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interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>; |
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#interrupt-cells = <2>; |
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interrupt-controller; |
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ti,system-power-controller; |
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|
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#gpio-cells = <2>; |
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gpio-controller; |
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vcc1-supply = <&sys_3v3_reg>; |
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vcc2-supply = <&sys_3v3_reg>; |
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vcc3-supply = <&vio_reg>; |
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vcc4-supply = <&sys_3v3_reg>; |
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vcc5-supply = <&sys_3v3_reg>; |
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vcc6-supply = <&vio_reg>; |
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vcc7-supply = <&charge_pump_5v0_reg>; |
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vccio-supply = <&sys_3v3_reg>; |
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regulators { |
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#address-cells = <1>; |
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#size-cells = <0>; |
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/* SW1: +V1.35_VDDIO_DDR */ |
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vdd1_reg: vdd1 { |
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regulator-name = "vddio_ddr_1v35"; |
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regulator-min-microvolt = <1350000>; |
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regulator-max-microvolt = <1350000>; |
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regulator-always-on; |
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}; |
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|
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/* SW2: +V1.05 */ |
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vdd2_reg: vdd2 { |
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regulator-name = |
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"vdd_pexa,vdd_pexb,vdd_sata"; |
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regulator-min-microvolt = <1050000>; |
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regulator-max-microvolt = <1050000>; |
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}; |
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|
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/* SW CTRL: +V1.0_VDD_CPU */ |
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vddctrl_reg: vddctrl { |
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regulator-name = "vdd_cpu,vdd_sys"; |
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regulator-min-microvolt = <1150000>; |
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regulator-max-microvolt = <1150000>; |
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regulator-always-on; |
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}; |
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/* SWIO: +V1.8 */ |
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vio_reg: vio { |
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regulator-name = "vdd_1v8_gen"; |
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regulator-min-microvolt = <1800000>; |
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regulator-max-microvolt = <1800000>; |
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regulator-always-on; |
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}; |
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/* LDO1: unused */ |
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/* |
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* EN_+V3.3 switching via FET: |
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* +V3.3_AUDIO_AVDD_S, +V3.3 and +V1.8_VDD_LAN |
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* see also v3_3 fixed supply |
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*/ |
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ldo2_reg: ldo2 { |
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regulator-name = "en_3v3"; |
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regulator-min-microvolt = <3300000>; |
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regulator-max-microvolt = <3300000>; |
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regulator-always-on; |
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}; |
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|
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/* +V1.2_CSI */ |
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ldo3_reg: ldo3 { |
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regulator-name = |
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"avdd_dsi_csi,pwrdet_mipi"; |
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regulator-min-microvolt = <1200000>; |
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regulator-max-microvolt = <1200000>; |
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}; |
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/* +V1.2_VDD_RTC */ |
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ldo4_reg: ldo4 { |
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regulator-name = "vdd_rtc"; |
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regulator-min-microvolt = <1200000>; |
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regulator-max-microvolt = <1200000>; |
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regulator-always-on; |
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}; |
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|
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/* |
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* +V2.8_AVDD_VDAC: |
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* only required for analog RGB |
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*/ |
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ldo5_reg: ldo5 { |
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regulator-name = "avdd_vdac"; |
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regulator-min-microvolt = <2800000>; |
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regulator-max-microvolt = <2800000>; |
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regulator-always-on; |
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}; |
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/* |
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* +V1.05_AVDD_PLLE: avdd_plle should be 1.05V |
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* but LDO6 can't set voltage in 50mV |
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* granularity |
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*/ |
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ldo6_reg: ldo6 { |
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regulator-name = "avdd_plle"; |
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regulator-min-microvolt = <1100000>; |
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regulator-max-microvolt = <1100000>; |
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}; |
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|
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/* +V1.2_AVDD_PLL */ |
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ldo7_reg: ldo7 { |
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regulator-name = "avdd_pll"; |
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regulator-min-microvolt = <1200000>; |
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regulator-max-microvolt = <1200000>; |
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regulator-always-on; |
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}; |
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/* +V1.0_VDD_DDR_HS */ |
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ldo8_reg: ldo8 { |
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regulator-name = "vdd_ddr_hs"; |
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regulator-min-microvolt = <1000000>; |
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regulator-max-microvolt = <1000000>; |
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regulator-always-on; |
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}; |
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}; |
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}; |
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}; |
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/* SPI1: Apalis SPI1 */ |
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spi@7000d400 { |
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status = "okay"; |
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spi-max-frequency = <25000000>; |
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}; |
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|
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/* SPI4: CAN2 */ |
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spi@7000da00 { |
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status = "okay"; |
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spi-max-frequency = <25000000>; |
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}; |
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|
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/* SPI5: Apalis SPI2 */ |
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spi@7000dc00 { |
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status = "okay"; |
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spi-max-frequency = <25000000>; |
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}; |
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|
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/* SPI6: CAN1 */ |
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spi@7000de00 { |
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status = "okay"; |
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spi-max-frequency = <25000000>; |
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}; |
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sdhci@78000000 { |
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status = "okay"; |
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bus-width = <4>; |
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cd-gpios = <&gpio 229 1>; /* PCC5, SD1_CD# */ |
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}; |
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sdhci@78000400 { |
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status = "okay"; |
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bus-width = <8>; |
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cd-gpios = <&gpio 171 1>; /* PV3, MMC1_CD# */ |
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}; |
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sdhci@78000600 { |
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status = "okay"; |
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bus-width = <8>; |
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non-removable; |
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}; |
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/* EHCI instance 0: USB1_DP/N -> USBO1_DP/N */ |
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usb@7d000000 { |
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status = "okay"; |
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dr_mode = "peripheral"; |
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nvidia,vbus-gpio = <&gpio 157 0>; /* PT5, USBO1_EN */ |
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}; |
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/* EHCI instance 1: USB2_DP/N -> USBH2_DP/N */ |
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usb@7d004000 { |
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status = "okay"; |
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nvidia,vbus-gpio = <&gpio 233 0>; /* PDD1, USBH_EN */ |
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phy_type = "utmi"; |
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}; |
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/* EHCI instance 2: USB3_DP/N -> USBH3_DP/N */ |
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usb@7d008000 { |
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status = "okay"; |
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nvidia,vbus-gpio = <&gpio 233 0>; /* PDD1, USBH_EN */ |
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}; |
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regulators { |
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compatible = "simple-bus"; |
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#address-cells = <1>; |
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#size-cells = <0>; |
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sys_3v3_reg: regulator@100 { |
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compatible = "regulator-fixed"; |
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reg = <100>; |
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regulator-name = "3v3"; |
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regulator-min-microvolt = <3300000>; |
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regulator-max-microvolt = <3300000>; |
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regulator-always-on; |
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}; |
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charge_pump_5v0_reg: regulator@101 { |
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compatible = "regulator-fixed"; |
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reg = <101>; |
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regulator-name = "5v0"; |
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regulator-min-microvolt = <5000000>; |
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regulator-max-microvolt = <5000000>; |
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regulator-always-on; |
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}; |
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}; |
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}; |
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@ -0,0 +1,37 @@ |
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/*
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* (C) Copyright 2014 |
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* NVIDIA Corporation <www.nvidia.com> |
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* |
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* SPDX-License-Identifier: GPL-2.0+ |
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*/ |
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#ifndef _TEGRA114_MC_H_ |
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#define _TEGRA114_MC_H_ |
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/**
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* Defines the memory controller registers we need/care about |
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*/ |
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struct mc_ctlr { |
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u32 reserved0[4]; /* offset 0x00 - 0x0C */ |
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u32 mc_smmu_config; /* offset 0x10 */ |
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u32 mc_smmu_tlb_config; /* offset 0x14 */ |
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u32 mc_smmu_ptc_config; /* offset 0x18 */ |
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u32 mc_smmu_ptb_asid; /* offset 0x1C */ |
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u32 mc_smmu_ptb_data; /* offset 0x20 */ |
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u32 reserved1[3]; /* offset 0x24 - 0x2C */ |
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u32 mc_smmu_tlb_flush; /* offset 0x30 */ |
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u32 mc_smmu_ptc_flush; /* offset 0x34 */ |
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u32 reserved2[6]; /* offset 0x38 - 0x4C */ |
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u32 mc_emem_cfg; /* offset 0x50 */ |
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u32 mc_emem_adr_cfg; /* offset 0x54 */ |
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u32 mc_emem_adr_cfg_dev0; /* offset 0x58 */ |
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u32 mc_emem_adr_cfg_dev1; /* offset 0x5C */ |
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u32 reserved3[12]; /* offset 0x60 - 0x8C */ |
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u32 mc_emem_arb_reserved[28]; /* offset 0x90 - 0xFC */ |
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u32 reserved4[338]; /* offset 0x100 - 0x644 */ |
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u32 mc_video_protect_bom; /* offset 0x648 */ |
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u32 mc_video_protect_size_mb; /* offset 0x64c */ |
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u32 mc_video_protect_reg_ctrl; /* offset 0x650 */ |
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}; |
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#endif /* _TEGRA114_MC_H_ */ |
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@ -0,0 +1,36 @@ |
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/*
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* (C) Copyright 2014 |
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* NVIDIA Corporation <www.nvidia.com> |
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* |
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* SPDX-License-Identifier: GPL-2.0+ |
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*/ |
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#ifndef _TEGRA20_MC_H_ |
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#define _TEGRA20_MC_H_ |
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/**
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* Defines the memory controller registers we need/care about |
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*/ |
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struct mc_ctlr { |
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u32 reserved0[3]; /* offset 0x00 - 0x08 */ |
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u32 mc_emem_cfg; /* offset 0x0C */ |
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u32 mc_emem_adr_cfg; /* offset 0x10 */ |
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u32 mc_emem_arb_cfg0; /* offset 0x14 */ |
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u32 mc_emem_arb_cfg1; /* offset 0x18 */ |
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u32 mc_emem_arb_cfg2; /* offset 0x1C */ |
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u32 reserved1; /* offset 0x20 */ |
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u32 mc_gart_cfg; /* offset 0x24 */ |
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u32 mc_gart_entry_addr; /* offset 0x28 */ |
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u32 mc_gart_entry_data; /* offset 0x2C */ |
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u32 mc_gart_error_req; /* offset 0x30 */ |
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u32 mc_gart_error_addr; /* offset 0x34 */ |
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u32 reserved2; /* offset 0x38 */ |
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u32 mc_timeout_ctrl; /* offset 0x3C */ |
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u32 reserved3[6]; /* offset 0x40 - 0x54 */ |
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u32 mc_decerr_emem_others_status; /* offset 0x58 */ |
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u32 mc_decerr_emem_others_adr; /* offset 0x5C */ |
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u32 reserved4[40]; /* offset 0x60 - 0xFC */ |
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u32 reserved5[93]; /* offset 0x100 - 0x270 */ |
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}; |
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#endif /* _TEGRA20_MC_H_ */ |
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@ -0,0 +1,38 @@ |
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/*
|
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* (C) Copyright 2014 |
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* NVIDIA Corporation <www.nvidia.com> |
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* |
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* SPDX-License-Identifier: GPL-2.0+ |
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*/ |
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|
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#ifndef _TEGRA30_MC_H_ |
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#define _TEGRA30_MC_H_ |
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|
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/**
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* Defines the memory controller registers we need/care about |
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*/ |
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struct mc_ctlr { |
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u32 reserved0[4]; /* offset 0x00 - 0x0C */ |
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u32 mc_smmu_config; /* offset 0x10 */ |
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u32 mc_smmu_tlb_config; /* offset 0x14 */ |
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u32 mc_smmu_ptc_config; /* offset 0x18 */ |
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u32 mc_smmu_ptb_asid; /* offset 0x1C */ |
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u32 mc_smmu_ptb_data; /* offset 0x20 */ |
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u32 reserved1[3]; /* offset 0x24 - 0x2C */ |
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u32 mc_smmu_tlb_flush; /* offset 0x30 */ |
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u32 mc_smmu_ptc_flush; /* offset 0x34 */ |
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u32 mc_smmu_asid_security; /* offset 0x38 */ |
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u32 reserved2[5]; /* offset 0x3C - 0x4C */ |
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u32 mc_emem_cfg; /* offset 0x50 */ |
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u32 mc_emem_adr_cfg; /* offset 0x54 */ |
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u32 mc_emem_adr_cfg_dev0; /* offset 0x58 */ |
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u32 mc_emem_adr_cfg_dev1; /* offset 0x5C */ |
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u32 reserved3[12]; /* offset 0x60 - 0x8C */ |
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u32 mc_emem_arb_reserved[28]; /* offset 0x90 - 0xFC */ |
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u32 reserved4[338]; /* offset 0x100 - 0x644 */ |
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u32 mc_video_protect_bom; /* offset 0x648 */ |
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u32 mc_video_protect_size_mb; /* offset 0x64c */ |
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u32 mc_video_protect_reg_ctrl; /* offset 0x650 */ |
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}; |
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#endif /* _TEGRA30_MC_H_ */ |
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@ -0,0 +1,12 @@ |
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if TARGET_APALIS_T30 |
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|
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config SYS_BOARD |
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default "apalis_t30" |
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|
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config SYS_VENDOR |
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default "toradex" |
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|
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config SYS_CONFIG_NAME |
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default "apalis_t30" |
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|
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endif |
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@ -0,0 +1,7 @@ |
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Apalis T30 |
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M: Marcel Ziswiler <marcel.ziswiler@toradex.com> |
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S: Maintained |
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F: board/toradex/apalis_t30/ |
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F: include/configs/apalis_t30.h |
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F: configs/apalis_t30_defconfig |
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F: arch/arm/dts/tegra30-apalis.dtb |
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@ -0,0 +1,6 @@ |
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# Copyright (c) 2014 Marcel Ziswiler
|
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# SPDX-License-Identifier: GPL-2.0+
|
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|
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include $(srctree)/board/nvidia/common/common.mk |
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|
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obj-y += apalis_t30.o
|
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@ -0,0 +1,92 @@ |
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/*
|
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* (C) Copyright 2014 |
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* Marcel Ziswiler <marcel@ziswiler.com> |
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* |
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* SPDX-License-Identifier: GPL-2.0+ |
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*/ |
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|
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#include <common.h> |
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|
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#include <asm/arch/gp_padctrl.h> |
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#include <asm/arch/pinmux.h> |
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#include <asm/gpio.h> |
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#include <i2c.h> |
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#include <netdev.h> |
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|
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#include "pinmux-config-apalis_t30.h" |
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|
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#define PMU_I2C_ADDRESS 0x2D |
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#define MAX_I2C_RETRY 3 |
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|
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/*
|
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* Routine: pinmux_init |
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* Description: Do individual peripheral pinmux configs |
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*/ |
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void pinmux_init(void) |
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{ |
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pinmux_config_pingrp_table(tegra3_pinmux_common, |
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ARRAY_SIZE(tegra3_pinmux_common)); |
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|
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pinmux_config_pingrp_table(unused_pins_lowpower, |
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ARRAY_SIZE(unused_pins_lowpower)); |
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|
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/* Initialize any non-default pad configs (APB_MISC_GP regs) */ |
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pinmux_config_drvgrp_table(apalis_t30_padctrl, |
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ARRAY_SIZE(apalis_t30_padctrl)); |
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} |
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|
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#ifdef CONFIG_PCI_TEGRA |
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int tegra_pcie_board_init(void) |
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{ |
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unsigned int old_bus; |
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u8 addr, data[1]; |
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int err; |
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|
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old_bus = i2c_get_bus_num(); |
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|
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err = i2c_set_bus_num(0); |
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if (err) { |
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debug("failed to set I2C bus\n"); |
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return err; |
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} |
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|
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/* TPS659110: VDD2_OP_REG = 1.05V */ |
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data[0] = 0x27; |
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addr = 0x25; |
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|
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err = i2c_write(PMU_I2C_ADDRESS, addr, 1, data, 1); |
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if (err) { |
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debug("failed to set VDD supply\n"); |
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return err; |
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} |
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|
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/* TPS659110: VDD2_REG 7.5 mV/us, ACTIVE */ |
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data[0] = 0x0D; |
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addr = 0x24; |
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|
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err = i2c_write(PMU_I2C_ADDRESS, addr, 1, data, 1); |
||||
if (err) { |
||||
debug("failed to enable VDD supply\n"); |
||||
return err; |
||||
} |
||||
|
||||
/* TPS659110: LDO6_REG = 1.1V, ACTIVE */ |
||||
data[0] = 0x0D; |
||||
addr = 0x35; |
||||
|
||||
err = i2c_write(PMU_I2C_ADDRESS, addr, 1, data, 1); |
||||
if (err) { |
||||
debug("failed to set AVDD supply\n"); |
||||
return err; |
||||
} |
||||
|
||||
i2c_set_bus_num(old_bus); |
||||
|
||||
return 0; |
||||
} |
||||
|
||||
int board_eth_init(bd_t *bis) |
||||
{ |
||||
return pci_eth_init(bis); |
||||
} |
||||
#endif /* CONFIG_PCI_TEGRA */ |
||||
@ -0,0 +1,347 @@ |
||||
/*
|
||||
* Copyright (c) 2014, Marcel Ziswiler |
||||
* |
||||
* This program is free software; you can redistribute it and/or modify it |
||||
* under the terms and conditions of the GNU General Public License, |
||||
* version 2, as published by the Free Software Foundation. |
||||
* |
||||
* This program is distributed in the hope it will be useful, but WITHOUT |
||||
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or |
||||
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for |
||||
* more details. |
||||
* |
||||
* You should have received a copy of the GNU General Public License |
||||
* along with this program. If not, see <http://www.gnu.org/licenses/>.
|
||||
*/ |
||||
|
||||
#ifndef _PINMUX_CONFIG_APALIS_T30_H_ |
||||
#define _PINMUX_CONFIG_APALIS_T30_H_ |
||||
|
||||
#define DEFAULT_PINMUX(_pingrp, _mux, _pull, _tri, _io) \ |
||||
{ \
|
||||
.pingrp = PMUX_PINGRP_##_pingrp, \
|
||||
.func = PMUX_FUNC_##_mux, \
|
||||
.pull = PMUX_PULL_##_pull, \
|
||||
.tristate = PMUX_TRI_##_tri, \
|
||||
.io = PMUX_PIN_##_io, \
|
||||
.lock = PMUX_PIN_LOCK_DEFAULT, \
|
||||
.od = PMUX_PIN_OD_DEFAULT, \
|
||||
.ioreset = PMUX_PIN_IO_RESET_DEFAULT, \
|
||||
} |
||||
|
||||
#define I2C_PINMUX(_pingrp, _mux, _pull, _tri, _io, _lock, _od) \ |
||||
{ \
|
||||
.pingrp = PMUX_PINGRP_##_pingrp, \
|
||||
.func = PMUX_FUNC_##_mux, \
|
||||
.pull = PMUX_PULL_##_pull, \
|
||||
.tristate = PMUX_TRI_##_tri, \
|
||||
.io = PMUX_PIN_##_io, \
|
||||
.lock = PMUX_PIN_LOCK_##_lock, \
|
||||
.od = PMUX_PIN_OD_##_od, \
|
||||
.ioreset = PMUX_PIN_IO_RESET_DEFAULT, \
|
||||
} |
||||
|
||||
#define LV_PINMUX(_pingrp, _mux, _pull, _tri, _io, _lock, _ioreset) \ |
||||
{ \
|
||||
.pingrp = PMUX_PINGRP_##_pingrp, \
|
||||
.func = PMUX_FUNC_##_mux, \
|
||||
.pull = PMUX_PULL_##_pull, \
|
||||
.tristate = PMUX_TRI_##_tri, \
|
||||
.io = PMUX_PIN_##_io, \
|
||||
.lock = PMUX_PIN_LOCK_##_lock, \
|
||||
.od = PMUX_PIN_OD_DEFAULT, \
|
||||
.ioreset = PMUX_PIN_IO_RESET_##_ioreset \
|
||||
} |
||||
|
||||
#define DEFAULT_PADCFG(_drvgrp, _slwf, _slwr, _drvup, _drvdn, _lpmd, _schmt, _hsm) \ |
||||
{ \
|
||||
.drvgrp = PMUX_DRVGRP_##_drvgrp, \
|
||||
.slwf = _slwf, \
|
||||
.slwr = _slwr, \
|
||||
.drvup = _drvup, \
|
||||
.drvdn = _drvdn, \
|
||||
.lpmd = PMUX_LPMD_##_lpmd, \
|
||||
.schmt = PMUX_SCHMT_##_schmt, \
|
||||
.hsm = PMUX_HSM_##_hsm, \
|
||||
} |
||||
|
||||
static struct pmux_pingrp_config tegra3_pinmux_common[] = { |
||||
/* SDMMC1 pinmux */ |
||||
DEFAULT_PINMUX(SDMMC1_CLK_PZ0, SDMMC1, NORMAL, NORMAL, INPUT), |
||||
DEFAULT_PINMUX(SDMMC1_CMD_PZ1, SDMMC1, NORMAL, NORMAL, INPUT), |
||||
DEFAULT_PINMUX(SDMMC1_DAT3_PY4, SDMMC1, NORMAL, NORMAL, INPUT), |
||||
DEFAULT_PINMUX(SDMMC1_DAT2_PY5, SDMMC1, NORMAL, NORMAL, INPUT), |
||||
DEFAULT_PINMUX(SDMMC1_DAT1_PY6, SDMMC1, NORMAL, NORMAL, INPUT), |
||||
DEFAULT_PINMUX(SDMMC1_DAT0_PY7, SDMMC1, NORMAL, NORMAL, INPUT), |
||||
|
||||
/* SDMMC3 pinmux */ |
||||
DEFAULT_PINMUX(SDMMC3_CLK_PA6, SDMMC3, NORMAL, NORMAL, INPUT), |
||||
DEFAULT_PINMUX(SDMMC3_CMD_PA7, SDMMC3, NORMAL, NORMAL, INPUT), |
||||
DEFAULT_PINMUX(SDMMC3_DAT0_PB7, SDMMC3, NORMAL, NORMAL, INPUT), |
||||
DEFAULT_PINMUX(SDMMC3_DAT1_PB6, SDMMC3, NORMAL, NORMAL, INPUT), |
||||
DEFAULT_PINMUX(SDMMC3_DAT2_PB5, SDMMC3, NORMAL, NORMAL, INPUT), |
||||
DEFAULT_PINMUX(SDMMC3_DAT3_PB4, SDMMC3, NORMAL, NORMAL, INPUT), |
||||
DEFAULT_PINMUX(SDMMC3_DAT4_PD1, SDMMC3, NORMAL, NORMAL, INPUT), |
||||
DEFAULT_PINMUX(SDMMC3_DAT5_PD0, SDMMC3, NORMAL, NORMAL, INPUT), |
||||
DEFAULT_PINMUX(SDMMC3_DAT6_PD3, SDMMC3, NORMAL, NORMAL, INPUT), |
||||
DEFAULT_PINMUX(SDMMC3_DAT7_PD4, SDMMC3, NORMAL, NORMAL, INPUT), |
||||
|
||||
/* SDMMC4 pinmux (eMMC) */ |
||||
LV_PINMUX(SDMMC4_CLK_PCC4, SDMMC4, NORMAL, NORMAL, INPUT, DISABLE, DISABLE), |
||||
LV_PINMUX(SDMMC4_CMD_PT7, SDMMC4, UP, NORMAL, INPUT, DISABLE, DISABLE), |
||||
LV_PINMUX(SDMMC4_DAT0_PAA0, SDMMC4, UP, NORMAL, INPUT, DISABLE, DISABLE), |
||||
LV_PINMUX(SDMMC4_DAT1_PAA1, SDMMC4, UP, NORMAL, INPUT, DISABLE, DISABLE), |
||||
LV_PINMUX(SDMMC4_DAT2_PAA2, SDMMC4, UP, NORMAL, INPUT, DISABLE, DISABLE), |
||||
LV_PINMUX(SDMMC4_DAT3_PAA3, SDMMC4, UP, NORMAL, INPUT, DISABLE, DISABLE), |
||||
LV_PINMUX(SDMMC4_DAT4_PAA4, SDMMC4, UP, NORMAL, INPUT, DISABLE, DISABLE), |
||||
LV_PINMUX(SDMMC4_DAT5_PAA5, SDMMC4, UP, NORMAL, INPUT, DISABLE, DISABLE), |
||||
LV_PINMUX(SDMMC4_DAT6_PAA6, SDMMC4, UP, NORMAL, INPUT, DISABLE, DISABLE), |
||||
LV_PINMUX(SDMMC4_DAT7_PAA7, SDMMC4, UP, NORMAL, INPUT, DISABLE, DISABLE), |
||||
LV_PINMUX(SDMMC4_RST_N_PCC3, RSVD1, DOWN, NORMAL, INPUT, DISABLE, DISABLE), |
||||
|
||||
/* I2C1 pinmux */ |
||||
I2C_PINMUX(GEN1_I2C_SCL_PC4, I2C1, NORMAL, NORMAL, INPUT, DISABLE, ENABLE), |
||||
I2C_PINMUX(GEN1_I2C_SDA_PC5, I2C1, NORMAL, NORMAL, INPUT, DISABLE, ENABLE), |
||||
|
||||
/* I2C2 pinmux */ |
||||
I2C_PINMUX(GEN2_I2C_SCL_PT5, I2C2, NORMAL, NORMAL, INPUT, DISABLE, ENABLE), |
||||
I2C_PINMUX(GEN2_I2C_SDA_PT6, I2C2, NORMAL, NORMAL, INPUT, DISABLE, ENABLE), |
||||
|
||||
/* I2C3 pinmux */ |
||||
I2C_PINMUX(CAM_I2C_SCL_PBB1, I2C3, NORMAL, TRISTATE, INPUT, DISABLE, ENABLE), |
||||
I2C_PINMUX(CAM_I2C_SDA_PBB2, I2C3, NORMAL, TRISTATE, INPUT, DISABLE, ENABLE), |
||||
|
||||
/* I2C4 pinmux */ |
||||
I2C_PINMUX(DDC_SCL_PV4, I2C4, NORMAL, NORMAL, INPUT, DISABLE, ENABLE), |
||||
I2C_PINMUX(DDC_SDA_PV5, I2C4, NORMAL, NORMAL, INPUT, DISABLE, ENABLE), |
||||
|
||||
/* Power I2C pinmux */ |
||||
I2C_PINMUX(PWR_I2C_SCL_PZ6, I2CPWR, NORMAL, NORMAL, INPUT, DISABLE, ENABLE), |
||||
I2C_PINMUX(PWR_I2C_SDA_PZ7, I2CPWR, NORMAL, NORMAL, INPUT, DISABLE, ENABLE), |
||||
|
||||
DEFAULT_PINMUX(ULPI_DATA0_PO1, UARTA, NORMAL, NORMAL, OUTPUT), |
||||
/* UARTA RX, make sure we don't get input form a floating Pin */ |
||||
DEFAULT_PINMUX(ULPI_DATA1_PO2, UARTA, UP, NORMAL, INPUT), |
||||
DEFAULT_PINMUX(ULPI_DATA2_PO3, UARTA, NORMAL, NORMAL, INPUT), |
||||
DEFAULT_PINMUX(ULPI_DATA3_PO4, RSVD1, NORMAL, NORMAL, INPUT), |
||||
DEFAULT_PINMUX(ULPI_DATA4_PO5, UARTA, NORMAL, NORMAL, INPUT), |
||||
DEFAULT_PINMUX(ULPI_DATA5_PO6, UARTA, NORMAL, NORMAL, INPUT), |
||||
DEFAULT_PINMUX(ULPI_DATA6_PO7, UARTA, NORMAL, NORMAL, INPUT), |
||||
DEFAULT_PINMUX(ULPI_DATA7_PO0, UARTA, NORMAL, NORMAL, OUTPUT), |
||||
DEFAULT_PINMUX(ULPI_CLK_PY0, UARTD, NORMAL, NORMAL, OUTPUT), |
||||
DEFAULT_PINMUX(ULPI_DIR_PY1, UARTD, NORMAL, NORMAL, INPUT), |
||||
DEFAULT_PINMUX(ULPI_NXT_PY2, UARTD, NORMAL, NORMAL, INPUT), |
||||
DEFAULT_PINMUX(ULPI_STP_PY3, UARTD, NORMAL, NORMAL, OUTPUT), |
||||
DEFAULT_PINMUX(DAP3_FS_PP0, I2S2, NORMAL, NORMAL, INPUT), |
||||
DEFAULT_PINMUX(DAP3_DIN_PP1, I2S2, NORMAL, NORMAL, INPUT), |
||||
DEFAULT_PINMUX(DAP3_DOUT_PP2, I2S2, NORMAL, NORMAL, INPUT), |
||||
DEFAULT_PINMUX(DAP3_SCLK_PP3, I2S2, NORMAL, NORMAL, INPUT), |
||||
DEFAULT_PINMUX(PV2, OWR, NORMAL, NORMAL, INPUT), |
||||
DEFAULT_PINMUX(PV3, RSVD1, NORMAL, NORMAL, INPUT), |
||||
DEFAULT_PINMUX(CLK2_OUT_PW5, EXTPERIPH2, NORMAL, NORMAL, INPUT), |
||||
DEFAULT_PINMUX(CLK2_REQ_PCC5, DAP, NORMAL, NORMAL, INPUT), |
||||
DEFAULT_PINMUX(LCD_PWR1_PC1, DISPLAYA, DOWN, TRISTATE, OUTPUT), /* NC */ |
||||
DEFAULT_PINMUX(LCD_PWR2_PC6, DISPLAYA, DOWN, TRISTATE, OUTPUT), /* NC */ |
||||
DEFAULT_PINMUX(LCD_SDIN_PZ2, SPI5, NORMAL, NORMAL, INPUT), |
||||
DEFAULT_PINMUX(LCD_SDOUT_PN5, SPI5, NORMAL, NORMAL, INPUT), |
||||
DEFAULT_PINMUX(LCD_WR_N_PZ3, DISPLAYA, DOWN, TRISTATE, OUTPUT), /* NC */ |
||||
DEFAULT_PINMUX(LCD_CS0_N_PN4, SPI5, NORMAL, NORMAL, INPUT), |
||||
DEFAULT_PINMUX(LCD_DC0_PN6, DISPLAYA, DOWN, TRISTATE, OUTPUT), /* NC */ |
||||
DEFAULT_PINMUX(LCD_SCK_PZ4, SPI5, NORMAL, NORMAL, INPUT), |
||||
DEFAULT_PINMUX(LCD_PWR0_PB2, DISPLAYA, DOWN, TRISTATE, OUTPUT), /* NC */ |
||||
DEFAULT_PINMUX(LCD_PCLK_PB3, DISPLAYA, NORMAL, NORMAL, INPUT), |
||||
DEFAULT_PINMUX(LCD_DE_PJ1, DISPLAYA, NORMAL, NORMAL, INPUT), |
||||
DEFAULT_PINMUX(LCD_HSYNC_PJ3, DISPLAYA, NORMAL, NORMAL, INPUT), |
||||
DEFAULT_PINMUX(LCD_VSYNC_PJ4, DISPLAYA, NORMAL, NORMAL, INPUT), |
||||
DEFAULT_PINMUX(LCD_D0_PE0, DISPLAYA, NORMAL, NORMAL, INPUT), |
||||
DEFAULT_PINMUX(LCD_D1_PE1, DISPLAYA, NORMAL, NORMAL, INPUT), |
||||
DEFAULT_PINMUX(LCD_D2_PE2, DISPLAYA, NORMAL, NORMAL, INPUT), |
||||
DEFAULT_PINMUX(LCD_D3_PE3, DISPLAYA, NORMAL, NORMAL, INPUT), |
||||
DEFAULT_PINMUX(LCD_D4_PE4, DISPLAYA, NORMAL, NORMAL, INPUT), |
||||
DEFAULT_PINMUX(LCD_D5_PE5, DISPLAYA, NORMAL, NORMAL, INPUT), |
||||
DEFAULT_PINMUX(LCD_D6_PE6, DISPLAYA, NORMAL, NORMAL, INPUT), |
||||
DEFAULT_PINMUX(LCD_D7_PE7, DISPLAYA, NORMAL, NORMAL, INPUT), |
||||
DEFAULT_PINMUX(LCD_D8_PF0, DISPLAYA, NORMAL, NORMAL, INPUT), |
||||
DEFAULT_PINMUX(LCD_D9_PF1, DISPLAYA, NORMAL, NORMAL, INPUT), |
||||
DEFAULT_PINMUX(LCD_D10_PF2, DISPLAYA, NORMAL, NORMAL, INPUT), |
||||
DEFAULT_PINMUX(LCD_D11_PF3, DISPLAYA, NORMAL, NORMAL, INPUT), |
||||
DEFAULT_PINMUX(LCD_D12_PF4, DISPLAYA, NORMAL, NORMAL, INPUT), |
||||
DEFAULT_PINMUX(LCD_D13_PF5, DISPLAYA, NORMAL, NORMAL, INPUT), |
||||
DEFAULT_PINMUX(LCD_D14_PF6, DISPLAYA, NORMAL, NORMAL, INPUT), |
||||
DEFAULT_PINMUX(LCD_D15_PF7, DISPLAYA, NORMAL, NORMAL, INPUT), |
||||
DEFAULT_PINMUX(LCD_D16_PM0, DISPLAYA, NORMAL, NORMAL, INPUT), |
||||
DEFAULT_PINMUX(LCD_D17_PM1, DISPLAYA, NORMAL, NORMAL, INPUT), |
||||
DEFAULT_PINMUX(LCD_D18_PM2, DISPLAYA, NORMAL, NORMAL, INPUT), |
||||
DEFAULT_PINMUX(LCD_D19_PM3, DISPLAYA, NORMAL, NORMAL, INPUT), |
||||
DEFAULT_PINMUX(LCD_D20_PM4, DISPLAYA, NORMAL, NORMAL, INPUT), |
||||
DEFAULT_PINMUX(LCD_D21_PM5, DISPLAYA, NORMAL, NORMAL, INPUT), |
||||
DEFAULT_PINMUX(LCD_D22_PM6, DISPLAYA, NORMAL, NORMAL, INPUT), |
||||
DEFAULT_PINMUX(LCD_D23_PM7, DISPLAYA, NORMAL, NORMAL, INPUT), |
||||
DEFAULT_PINMUX(LCD_CS1_N_PW0, DISPLAYA, DOWN, TRISTATE, OUTPUT), /* NC */ |
||||
DEFAULT_PINMUX(LCD_M1_PW1, DISPLAYA, DOWN, TRISTATE, OUTPUT), /* NC */ |
||||
DEFAULT_PINMUX(LCD_DC1_PD2, DISPLAYA, NORMAL, NORMAL, INPUT), |
||||
DEFAULT_PINMUX(CRT_HSYNC_PV6, CRT, NORMAL, NORMAL, OUTPUT), |
||||
DEFAULT_PINMUX(CRT_VSYNC_PV7, CRT, NORMAL, NORMAL, OUTPUT), |
||||
LV_PINMUX(VI_D0_PT4, VI, NORMAL, NORMAL, INPUT, DISABLE, DISABLE), |
||||
LV_PINMUX(VI_D1_PD5, VI, NORMAL, NORMAL, INPUT, DISABLE, DISABLE), |
||||
LV_PINMUX(VI_D2_PL0, VI, NORMAL, NORMAL, INPUT, DISABLE, DISABLE), |
||||
LV_PINMUX(VI_D3_PL1, VI, NORMAL, NORMAL, INPUT, DISABLE, DISABLE), |
||||
LV_PINMUX(VI_D4_PL2, VI, NORMAL, NORMAL, INPUT, DISABLE, DISABLE), |
||||
LV_PINMUX(VI_D5_PL3, VI, NORMAL, NORMAL, INPUT, DISABLE, DISABLE), |
||||
LV_PINMUX(VI_D6_PL4, VI, NORMAL, NORMAL, INPUT, DISABLE, DISABLE), |
||||
LV_PINMUX(VI_D7_PL5, VI, NORMAL, NORMAL, INPUT, DISABLE, DISABLE), |
||||
LV_PINMUX(VI_D8_PL6, VI, NORMAL, NORMAL, INPUT, DISABLE, DISABLE), |
||||
LV_PINMUX(VI_D9_PL7, VI, NORMAL, NORMAL, INPUT, DISABLE, DISABLE), |
||||
LV_PINMUX(VI_D10_PT2, VI, NORMAL, NORMAL, INPUT, DISABLE, DISABLE), |
||||
LV_PINMUX(VI_D11_PT3, VI, NORMAL, NORMAL, INPUT, DISABLE, DISABLE), |
||||
LV_PINMUX(VI_HSYNC_PD7, VI, NORMAL, NORMAL, INPUT, DISABLE, DISABLE), |
||||
LV_PINMUX(VI_MCLK_PT1, VI, NORMAL, NORMAL, OUTPUT, DISABLE, DISABLE), |
||||
LV_PINMUX(VI_PCLK_PT0, VI, NORMAL, NORMAL, INPUT, DISABLE, DISABLE), |
||||
LV_PINMUX(VI_VSYNC_PD6, VI, NORMAL, NORMAL, INPUT, DISABLE, DISABLE), |
||||
DEFAULT_PINMUX(UART2_RXD_PC3, UARTB, NORMAL, NORMAL, INPUT), |
||||
DEFAULT_PINMUX(UART2_TXD_PC2, UARTB, NORMAL, NORMAL, OUTPUT), |
||||
DEFAULT_PINMUX(UART2_RTS_N_PJ6, UARTB, DOWN, TRISTATE, OUTPUT), /* NC */ |
||||
DEFAULT_PINMUX(UART2_CTS_N_PJ5, UARTB, DOWN, TRISTATE, OUTPUT), /* NC */ |
||||
DEFAULT_PINMUX(UART3_TXD_PW6, UARTC, NORMAL, NORMAL, OUTPUT), |
||||
DEFAULT_PINMUX(UART3_RXD_PW7, UARTC, NORMAL, NORMAL, INPUT), |
||||
DEFAULT_PINMUX(UART3_CTS_N_PA1, UARTC, NORMAL, NORMAL, INPUT), |
||||
DEFAULT_PINMUX(UART3_RTS_N_PC0, PWM0, NORMAL, NORMAL, OUTPUT), |
||||
DEFAULT_PINMUX(PU0, RSVD1, DOWN, TRISTATE, OUTPUT), |
||||
DEFAULT_PINMUX(PU1, RSVD1, DOWN, TRISTATE, OUTPUT), |
||||
DEFAULT_PINMUX(PU2, RSVD1, DOWN, TRISTATE, OUTPUT), |
||||
DEFAULT_PINMUX(PU3, PWM0, NORMAL, NORMAL, OUTPUT), |
||||
DEFAULT_PINMUX(PU4, PWM1, NORMAL, NORMAL, OUTPUT), |
||||
DEFAULT_PINMUX(PU5, PWM2, NORMAL, NORMAL, OUTPUT), |
||||
DEFAULT_PINMUX(PU6, PWM3, NORMAL, NORMAL, OUTPUT), |
||||
DEFAULT_PINMUX(DAP4_FS_PP4, I2S3, DOWN, TRISTATE, OUTPUT), /* NC */ |
||||
DEFAULT_PINMUX(DAP4_DIN_PP5, I2S3, DOWN, TRISTATE, OUTPUT), /* NC */ |
||||
DEFAULT_PINMUX(DAP4_DOUT_PP6, I2S3, DOWN, TRISTATE, OUTPUT), /* NC */ |
||||
DEFAULT_PINMUX(DAP4_SCLK_PP7, I2S3, DOWN, TRISTATE, OUTPUT), /* NC */ |
||||
DEFAULT_PINMUX(CLK3_OUT_PEE0, EXTPERIPH3, DOWN, TRISTATE, OUTPUT), /* NC */ |
||||
DEFAULT_PINMUX(CLK3_REQ_PEE1, DEV3, DOWN, TRISTATE, OUTPUT), /* NC */ |
||||
DEFAULT_PINMUX(GMI_WP_N_PC7, GMI, DOWN, TRISTATE, OUTPUT), /* NC */ |
||||
DEFAULT_PINMUX(GMI_CS2_N_PK3, RSVD1, DOWN, TRISTATE, OUTPUT), /* NC */ |
||||
DEFAULT_PINMUX(GMI_AD8_PH0, PWM0, DOWN, TRISTATE, OUTPUT), /* NC */ |
||||
DEFAULT_PINMUX(GMI_AD10_PH2, NAND, DOWN, TRISTATE, OUTPUT), /* NC */ |
||||
DEFAULT_PINMUX(GMI_A16_PJ7, UARTD, DOWN, TRISTATE, OUTPUT), /* NC */ |
||||
DEFAULT_PINMUX(GMI_A17_PB0, UARTD, DOWN, TRISTATE, OUTPUT), /* NC */ |
||||
DEFAULT_PINMUX(GMI_A18_PB1, UARTD, DOWN, TRISTATE, OUTPUT), /* NC */ |
||||
DEFAULT_PINMUX(GMI_A19_PK7, UARTD, DOWN, TRISTATE, OUTPUT), /* NC */ |
||||
|
||||
DEFAULT_PINMUX(CAM_MCLK_PCC0, VI_ALT2, NORMAL, NORMAL, OUTPUT), |
||||
DEFAULT_PINMUX(PBB0, RSVD1, NORMAL, NORMAL, OUTPUT), |
||||
DEFAULT_PINMUX(PBB3, VGP3, NORMAL, NORMAL, OUTPUT), |
||||
DEFAULT_PINMUX(PBB4, VGP4, NORMAL, NORMAL, OUTPUT), |
||||
DEFAULT_PINMUX(PBB5, VGP5, NORMAL, NORMAL, OUTPUT), |
||||
DEFAULT_PINMUX(PBB6, VGP6, NORMAL, NORMAL, OUTPUT), |
||||
DEFAULT_PINMUX(PBB7, I2S4, NORMAL, NORMAL, OUTPUT), |
||||
DEFAULT_PINMUX(PCC1, RSVD1, NORMAL, NORMAL, OUTPUT), |
||||
DEFAULT_PINMUX(PCC2, I2S4, NORMAL, NORMAL, OUTPUT), |
||||
|
||||
DEFAULT_PINMUX(JTAG_RTCK_PU7, RTCK, NORMAL, NORMAL, OUTPUT), |
||||
|
||||
/* multiplexed VI_D2, VI_D3, VI_D4, VI_D5, VI_D6, VI_D7, VI_D8 and VI_D9
|
||||
*/ |
||||
DEFAULT_PINMUX(KB_ROW0_PR0, RSVD2, NORMAL, TRISTATE, INPUT), |
||||
DEFAULT_PINMUX(KB_ROW1_PR1, RSVD2, NORMAL, TRISTATE, INPUT), |
||||
DEFAULT_PINMUX(KB_ROW2_PR2, RSVD2, NORMAL, TRISTATE, INPUT), |
||||
DEFAULT_PINMUX(KB_ROW3_PR3, RSVD2, NORMAL, TRISTATE, INPUT), |
||||
DEFAULT_PINMUX(KB_ROW4_PR4, RSVD3, NORMAL, TRISTATE, INPUT), |
||||
DEFAULT_PINMUX(KB_ROW5_PR5, KBC, NORMAL, TRISTATE, INPUT), |
||||
DEFAULT_PINMUX(KB_ROW6_PR6, KBC, NORMAL, TRISTATE, INPUT), |
||||
DEFAULT_PINMUX(KB_ROW7_PR7, KBC, NORMAL, TRISTATE, INPUT), |
||||
DEFAULT_PINMUX(KB_ROW8_PS0, KBC, NORMAL, TRISTATE, INPUT), |
||||
DEFAULT_PINMUX(KB_ROW9_PS1, KBC, NORMAL, TRISTATE, INPUT), |
||||
|
||||
/* GPIOs */ |
||||
DEFAULT_PINMUX(KB_ROW10_PS2, SDMMC2, NORMAL, NORMAL, INPUT), |
||||
DEFAULT_PINMUX(KB_ROW11_PS3, SDMMC2, NORMAL, NORMAL, INPUT), |
||||
DEFAULT_PINMUX(KB_ROW12_PS4, SDMMC2, NORMAL, NORMAL, INPUT), |
||||
DEFAULT_PINMUX(KB_ROW13_PS5, SDMMC2, NORMAL, NORMAL, INPUT), |
||||
DEFAULT_PINMUX(KB_ROW14_PS6, SDMMC2, NORMAL, NORMAL, INPUT), |
||||
DEFAULT_PINMUX(KB_ROW15_PS7, SDMMC2, NORMAL, NORMAL, INPUT), |
||||
|
||||
DEFAULT_PINMUX(KB_COL0_PQ0, KBC, NORMAL, NORMAL, INPUT), |
||||
DEFAULT_PINMUX(KB_COL1_PQ1, KBC, NORMAL, NORMAL, INPUT), |
||||
DEFAULT_PINMUX(KB_COL2_PQ2, KBC, NORMAL, NORMAL, INPUT), |
||||
DEFAULT_PINMUX(KB_COL3_PQ3, KBC, NORMAL, NORMAL, INPUT), |
||||
DEFAULT_PINMUX(KB_COL4_PQ4, KBC, NORMAL, NORMAL, INPUT), |
||||
DEFAULT_PINMUX(KB_COL5_PQ5, KBC, NORMAL, NORMAL, INPUT), |
||||
DEFAULT_PINMUX(KB_COL6_PQ6, KBC, NORMAL, NORMAL, INPUT), |
||||
DEFAULT_PINMUX(KB_COL7_PQ7, KBC, NORMAL, NORMAL, INPUT), |
||||
|
||||
DEFAULT_PINMUX(PV0, RSVD1, NORMAL, NORMAL, INPUT), |
||||
|
||||
DEFAULT_PINMUX(CLK_32K_OUT_PA0, BLINK, DOWN, TRISTATE, OUTPUT), /* NC */ |
||||
DEFAULT_PINMUX(SYS_CLK_REQ_PZ5, SYSCLK, NORMAL, NORMAL, INPUT), |
||||
/* multiplexed KB_COL0 */ |
||||
DEFAULT_PINMUX(OWR, OWR, NORMAL, NORMAL, INPUT), |
||||
DEFAULT_PINMUX(DAP1_FS_PN0, I2S0, NORMAL, NORMAL, INPUT), |
||||
DEFAULT_PINMUX(DAP1_DIN_PN1, I2S0, NORMAL, NORMAL, INPUT), |
||||
DEFAULT_PINMUX(DAP1_DOUT_PN2, I2S0, NORMAL, NORMAL, INPUT), |
||||
DEFAULT_PINMUX(DAP1_SCLK_PN3, I2S0, NORMAL, NORMAL, INPUT), |
||||
DEFAULT_PINMUX(CLK1_REQ_PEE2, DAP, NORMAL, NORMAL, OUTPUT), |
||||
DEFAULT_PINMUX(CLK1_OUT_PW4, EXTPERIPH1, NORMAL, NORMAL, OUTPUT), |
||||
DEFAULT_PINMUX(SPDIF_IN_PK6, SPDIF, NORMAL, NORMAL, INPUT), |
||||
DEFAULT_PINMUX(SPDIF_OUT_PK5, SPDIF, NORMAL, NORMAL, OUTPUT), |
||||
DEFAULT_PINMUX(DAP2_FS_PA2, I2S1, NORMAL, TRISTATE, OUTPUT), |
||||
DEFAULT_PINMUX(DAP2_DIN_PA4, I2S1, NORMAL, TRISTATE, OUTPUT), |
||||
DEFAULT_PINMUX(DAP2_DOUT_PA5, I2S1, NORMAL, TRISTATE, OUTPUT), |
||||
DEFAULT_PINMUX(DAP2_SCLK_PA3, I2S1, NORMAL, TRISTATE, OUTPUT), |
||||
|
||||
DEFAULT_PINMUX(SPI2_CS1_N_PW2, SPI2, NORMAL, NORMAL, INPUT), |
||||
DEFAULT_PINMUX(SPI1_MOSI_PX4, SPI1, NORMAL, NORMAL, INPUT), |
||||
DEFAULT_PINMUX(SPI1_SCK_PX5, SPI1, NORMAL, NORMAL, INPUT), |
||||
DEFAULT_PINMUX(SPI1_CS0_N_PX6, SPI1, NORMAL, NORMAL, INPUT), |
||||
DEFAULT_PINMUX(SPI1_MISO_PX7, SPI1, NORMAL, NORMAL, INPUT), |
||||
|
||||
DEFAULT_PINMUX(PEX_L0_PRSNT_N_PDD0, PCIE, NORMAL, NORMAL, INPUT), |
||||
DEFAULT_PINMUX(PEX_L0_RST_N_PDD1, PCIE, NORMAL, NORMAL, OUTPUT), |
||||
DEFAULT_PINMUX(PEX_L0_CLKREQ_N_PDD2, PCIE, NORMAL, NORMAL, INPUT), |
||||
DEFAULT_PINMUX(PEX_WAKE_N_PDD3, PCIE, NORMAL, NORMAL, INPUT), |
||||
|
||||
DEFAULT_PINMUX(PEX_L1_PRSNT_N_PDD4, PCIE, DOWN, TRISTATE, OUTPUT), /* NC */ |
||||
DEFAULT_PINMUX(PEX_L1_RST_N_PDD5, PCIE, DOWN, TRISTATE, OUTPUT), /* NC */ |
||||
DEFAULT_PINMUX(PEX_L1_CLKREQ_N_PDD6, PCIE, DOWN, TRISTATE, OUTPUT), /* NC */ |
||||
DEFAULT_PINMUX(PEX_L2_PRSNT_N_PDD7, PCIE, NORMAL, NORMAL, INPUT), |
||||
DEFAULT_PINMUX(PEX_L2_RST_N_PCC6, PCIE, NORMAL, NORMAL, OUTPUT), |
||||
DEFAULT_PINMUX(PEX_L2_CLKREQ_N_PCC7, PCIE, NORMAL, NORMAL, INPUT), |
||||
DEFAULT_PINMUX(HDMI_CEC_PEE3, CEC, NORMAL, NORMAL, INPUT), |
||||
DEFAULT_PINMUX(HDMI_INT_PN7, RSVD1, NORMAL, NORMAL, INPUT), |
||||
|
||||
DEFAULT_PINMUX(GMI_IORDY_PI5, RSVD1, DOWN, TRISTATE, OUTPUT), /* NC */ |
||||
DEFAULT_PINMUX(GMI_AD12_PH4, NAND, DOWN, TRISTATE, OUTPUT), /* NC */ |
||||
DEFAULT_PINMUX(GMI_AD14_PH6, NAND, DOWN, TRISTATE, OUTPUT), /* NC */ |
||||
|
||||
DEFAULT_PINMUX(SPI2_SCK_PX2, GMI, NORMAL, NORMAL, INPUT), |
||||
DEFAULT_PINMUX(KB_ROW8_PS0, KBC, NORMAL, NORMAL, INPUT), |
||||
}; |
||||
|
||||
static struct pmux_pingrp_config unused_pins_lowpower[] = { |
||||
DEFAULT_PINMUX(GMI_WAIT_PI7, NAND, DOWN, TRISTATE, OUTPUT), |
||||
DEFAULT_PINMUX(GMI_ADV_N_PK0, NAND, DOWN, TRISTATE, OUTPUT), |
||||
DEFAULT_PINMUX(GMI_CLK_PK1, NAND, DOWN, TRISTATE, OUTPUT), |
||||
DEFAULT_PINMUX(GMI_CS3_N_PK4, NAND, DOWN, TRISTATE, OUTPUT), |
||||
DEFAULT_PINMUX(GMI_CS7_N_PI6, NAND, DOWN, TRISTATE, OUTPUT), |
||||
DEFAULT_PINMUX(GMI_AD0_PG0, NAND, DOWN, TRISTATE, OUTPUT), |
||||
DEFAULT_PINMUX(GMI_AD1_PG1, NAND, DOWN, TRISTATE, OUTPUT), |
||||
DEFAULT_PINMUX(GMI_AD2_PG2, NAND, DOWN, TRISTATE, OUTPUT), |
||||
DEFAULT_PINMUX(GMI_AD3_PG3, NAND, DOWN, TRISTATE, OUTPUT), |
||||
DEFAULT_PINMUX(GMI_AD4_PG4, NAND, DOWN, TRISTATE, OUTPUT), |
||||
DEFAULT_PINMUX(GMI_AD5_PG5, NAND, DOWN, TRISTATE, OUTPUT), |
||||
DEFAULT_PINMUX(GMI_AD6_PG6, NAND, DOWN, TRISTATE, OUTPUT), |
||||
DEFAULT_PINMUX(GMI_AD7_PG7, NAND, DOWN, TRISTATE, OUTPUT), |
||||
DEFAULT_PINMUX(GMI_AD9_PH1, PWM1, DOWN, TRISTATE, OUTPUT), |
||||
DEFAULT_PINMUX(GMI_AD11_PH3, NAND, DOWN, TRISTATE, OUTPUT), |
||||
DEFAULT_PINMUX(GMI_AD13_PH5, NAND, DOWN, TRISTATE, OUTPUT), |
||||
DEFAULT_PINMUX(GMI_WR_N_PI0, NAND, DOWN, TRISTATE, OUTPUT), |
||||
DEFAULT_PINMUX(GMI_OE_N_PI1, NAND, NORMAL, NORMAL, INPUT), |
||||
DEFAULT_PINMUX(GMI_DQS_PI2, NAND, DOWN, TRISTATE, OUTPUT), |
||||
}; |
||||
|
||||
static struct pmux_drvgrp_config apalis_t30_padctrl[] = { |
||||
/* (_drvgrp, _slwf, _slwr, _drvup, _drvdn, _lpmd, _schmt, _hsm) */ |
||||
DEFAULT_PADCFG(SDIO1, SDIOCFG_DRVUP_SLWF, SDIOCFG_DRVDN_SLWR, \
|
||||
SDIOCFG_DRVUP, SDIOCFG_DRVDN, NONE, DISABLE, DISABLE), |
||||
}; |
||||
#endif /* _PINMUX_CONFIG_APALIS_T30_H_ */ |
||||
@ -0,0 +1,5 @@ |
||||
+S:CONFIG_ARM=y |
||||
+S:CONFIG_TEGRA=y |
||||
+S:CONFIG_TEGRA30=y |
||||
+S:CONFIG_TARGET_APALIS_T30=y |
||||
CONFIG_DEFAULT_DEVICE_TREE="tegra30-apalis" |
||||
@ -0,0 +1,75 @@ |
||||
/*
|
||||
* Copyright (c) 2014 Marcel Ziswiler |
||||
* |
||||
* SPDX-License-Identifier: GPL-2.0+ |
||||
*/ |
||||
|
||||
#ifndef __CONFIG_H |
||||
#define __CONFIG_H |
||||
|
||||
#include <linux/sizes.h> |
||||
|
||||
#include "tegra30-common.h" |
||||
|
||||
/* High-level configuration options */ |
||||
#define V_PROMPT "Apalis T30 # " |
||||
#define CONFIG_TEGRA_BOARD_STRING "Toradex Apalis T30" |
||||
|
||||
/* Board-specific serial config */ |
||||
#define CONFIG_SERIAL_MULTI |
||||
#define CONFIG_TEGRA_ENABLE_UARTA |
||||
#define CONFIG_SYS_NS16550_COM1 NV_PA_APB_UARTA_BASE |
||||
|
||||
#define CONFIG_MACH_TYPE MACH_TYPE_APALIS_T30 |
||||
|
||||
#define CONFIG_BOARD_EARLY_INIT_F |
||||
|
||||
/* I2C */ |
||||
#define CONFIG_SYS_I2C_TEGRA |
||||
#define CONFIG_SYS_I2C_INIT_BOARD |
||||
#define CONFIG_SYS_I2C_SPEED 100000 |
||||
#define CONFIG_CMD_I2C |
||||
#define CONFIG_SYS_I2C |
||||
|
||||
/* SD/MMC */ |
||||
#define CONFIG_MMC |
||||
#define CONFIG_GENERIC_MMC |
||||
#define CONFIG_TEGRA_MMC |
||||
#define CONFIG_CMD_MMC |
||||
|
||||
/* Environment in eMMC, at the end of 2nd "boot sector" */ |
||||
#define CONFIG_ENV_IS_IN_MMC |
||||
#define CONFIG_ENV_OFFSET (-CONFIG_ENV_SIZE) |
||||
#define CONFIG_SYS_MMC_ENV_DEV 0 |
||||
#define CONFIG_SYS_MMC_ENV_PART 2 |
||||
|
||||
/* USB Host support */ |
||||
#define CONFIG_USB_EHCI |
||||
#define CONFIG_USB_EHCI_TEGRA |
||||
#define CONFIG_USB_MAX_CONTROLLER_COUNT 3 |
||||
#define CONFIG_USB_STORAGE |
||||
#define CONFIG_CMD_USB |
||||
|
||||
/* USB networking support */ |
||||
#define CONFIG_USB_HOST_ETHER |
||||
#define CONFIG_USB_ETHER_ASIX |
||||
|
||||
/* PCI host support */ |
||||
#undef CONFIG_PCI /* just define once Tegra PCIe support got merged */ |
||||
#define CONFIG_PCI_TEGRA |
||||
#define CONFIG_PCI_PNP |
||||
#define CONFIG_CMD_PCI |
||||
#define CONFIG_CMD_PCI_ENUM |
||||
|
||||
/* PCI networking support */ |
||||
#define CONFIG_E1000 |
||||
#undef CONFIG_E1000_NO_NVM /* just define once E1000 driver got fixed */ |
||||
|
||||
/* General networking support */ |
||||
#define CONFIG_CMD_NET |
||||
#define CONFIG_CMD_DHCP |
||||
|
||||
#include "tegra-common-usb-gadget.h" |
||||
#include "tegra-common-post.h" |
||||
|
||||
#endif /* __CONFIG_H */ |
||||
Loading…
Reference in new issue