add the am1808 based ipam390 board from Barix. - 128MByte, DDR2, synchronous RAM 16bit databus to SDRAM interface - 128MByte, NAND Flash, 8bit databus to the NANDFlash Interface - Ethernet PHY Micrel KSZ8051R via RMII - Console on UART 0 - booting fron nand flash - spl falcon bootmode Signed-off-by: Heiko Schocher <hs@denx.de> Cc: Tom Rini <trini@ti.com>master
Heiko Schocher
11 years ago
committed by
Tom Rini
parent
9c8deaeeb7
commit
03efcb0505
@ -0,0 +1,29 @@ |
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#
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# (C) Copyright 2000, 2001, 2002
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# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
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#
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# Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net>
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#
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# SPDX-License-Identifier: GPL-2.0+
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#
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include $(TOPDIR)/config.mk |
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LIB = $(obj)lib$(BOARD).o
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COBJS += ipam390.o
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SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
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OBJS := $(addprefix $(obj),$(COBJS))
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SOBJS := $(addprefix $(obj),$(SOBJS))
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$(LIB): $(obj).depend $(OBJS) $(SOBJS) |
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$(call cmd_link_o_target, $(OBJS) $(SOBJS))
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#########################################################################
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# This is for $(obj).depend target
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include $(SRCTREE)/rules.mk |
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sinclude $(obj).depend |
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#########################################################################
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@ -0,0 +1,229 @@ |
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Summary |
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======= |
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The README is for the boot procedure on the ipam390 board |
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In the context of U-Boot, the board is booted in three stages. The initial |
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bootloader which executes upon reset is the ROM Boot Loader (RBL) and sits |
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in the internal ROM. The RBL initializes the internal memory and then |
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depending on the exact board and pin configurations will initialize another |
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controller (such as NAND) to continue the boot process by loading |
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the secondary program loader (SPL). The SPL will initialize the system |
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further (some clocks, SDRAM). As on this board is used the falcon boot |
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mode, now 2 ways are possible depending on the GPIO 7_14 input pin, |
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connected with the "soft reset switch" |
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If this pin is logical 1 (high level): |
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spl code starts the kernel image without delay |
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If this pin is logical 0 (low level): |
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spl code starts the u-boot image |
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AIS is an image format defined by TI for the images that are to be loaded |
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to memory by the RBL. The image is divided into a series of sections and |
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the image's entry point is specified. Each section comes with meta data |
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like the target address the section is to be copied to and the size of the |
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section, which is used by the RBL to load the image. At the end of the |
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image the RBL jumps to the image entry point. The AIS format allows for |
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other things such as programming the clocks and SDRAM if the header is |
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programmed for it. We do not take advantage of this and instead use SPL as |
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it allows for additional flexibility (run-time detect of board revision, |
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loading the next image from a different media, etc). |
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Compilation |
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=========== |
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run "./MAKEALL ipam390" in the u-boot source tree. |
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Once this build completes you will have a u-boot.ais file that needs to |
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be written to the nand flash. |
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|
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Flashing the images to NAND |
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========================== |
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The AIS image can be written to NAND flash using the following commands. |
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Assuming that the network is configured and enabled and the u-boot.ais file |
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is tftp'able. |
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U-Boot > print upd_uboot |
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upd_uboot=tftp c0000000 ${u-boot};nand erase.part u-boot;nand write c0000000 20000 ${filesize} |
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U-Boot > |
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U-Boot > run upd_uboot |
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Using DaVinci-EMAC device |
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TFTP from server 192.168.1.1; our IP address is 192.168.20.71 |
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Filename '/tftpboot/ipam390/u-boot.ais'. |
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Load address: 0xc0000000 |
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Loading: ################################## |
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1.5 MiB/s |
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done |
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Bytes transferred = 493716 (78894 hex) |
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NAND erase.part: device 0 offset 0x20000, size 0x160000 |
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Erasing at 0x160000 -- 100% complete. |
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OK |
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NAND write: device 0 offset 0x20000, size 0x78894 |
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493716 bytes written: OK |
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U-Boot > |
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Recovery |
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======== |
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In the case of a "bricked" board, you need to use the TI tools found |
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here[1] to create an uboot-uart-ais.bin file |
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- cd to the u-boot source tree |
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- compile the u-boot for the ipam390 board: |
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$ ./MAKEALL ipam390 |
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-> Now we shall have u-boot.bin |
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- Create u-boot-uart-ais.bin |
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$ mono HexAIS_OMAP-L138.exe -entrypoint 0xC1080000 -ini |
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ipam390-ais-uart.cfg -o ./uboot-uart-ais.bin ./u-boot.bin@0xC1080000; |
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Note: The ipam390-ais-uart.cfg is found in the board directory |
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for the ipam390 board, u-boot:/board/Barix/ipam390/ipam390-ais-uart.cfg |
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- We can now run bootloader on IPAM390 via UART using the command below: |
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$ mono ./slh_OMAP-L138.exe -waitForDevice -v -p /dev/tty.UC-232AC uboot-uart-ais.bin |
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NOTE: Do not cancel the command execution! The command takes 20+ seconds |
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to upload u-boot over serial and run it! |
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Outcome: |
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Waiting for the OMAP-L138... |
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(AIS Parse): Read magic word 0x41504954. |
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(AIS Parse): Waiting for BOOTME... (power on or reset target now) |
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(AIS Parse): BOOTME received! |
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(AIS Parse): Performing Start-Word Sync... |
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(AIS Parse): Performing Ping Opcode Sync... |
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(AIS Parse): Processing command 0: 0x5853590D. |
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(AIS Parse): Performing Opcode Sync... |
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(AIS Parse): Executing function... |
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(AIS Parse): Processing command 1: 0x5853590D. |
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(AIS Parse): Performing Opcode Sync... |
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(AIS Parse): Executing function... |
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(AIS Parse): Processing command 2: 0x5853590D. |
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(AIS Parse): Performing Opcode Sync... |
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(AIS Parse): Executing function... |
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(AIS Parse): Processing command 3: 0x5853590D. |
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(AIS Parse): Performing Opcode Sync... |
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(AIS Parse): Executing function... |
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(AIS Parse): Processing command 4: 0x5853590D. |
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(AIS Parse): Performing Opcode Sync... |
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(AIS Parse): Executing function... |
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(AIS Parse): Processing command 5: 0x58535901. |
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(AIS Parse): Performing Opcode Sync... |
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(AIS Parse): Loading section... |
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(AIS Parse): Loaded 326516-Byte section to address 0xC1080000. |
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(AIS Parse): Processing command 6: 0x58535906. |
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(AIS Parse): Performing Opcode Sync... |
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(AIS Parse): Performing jump and close... |
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(AIS Parse): AIS complete. Jump to address 0xC1080000. |
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(AIS Parse): Waiting for DONE... |
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(AIS Parse): Boot completed successfully. |
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Operation completed successfully. |
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Falcon Bootmode (boot linux without booting U-Boot) |
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=================================================== |
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The Falcon Mode extends this way allowing to start the Linux kernel directly |
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from SPL. A new command is added to U-Boot to prepare the parameters that SPL |
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must pass to the kernel, using ATAGS or Device Tree. |
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In normal mode, these parameters are generated each time before |
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loading the kernel, passing to Linux the address in memory where |
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the parameters can be read. |
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With Falcon Mode, this snapshot can be saved into persistent storage and SPL is |
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informed to load it before running the kernel. |
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To boot the kernel, these steps under a Falcon-aware U-Boot are required: |
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1. Boot the board into U-Boot. |
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Use the "spl export" command to generate the kernel parameters area or the DT. |
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U-Boot runs as when it boots the kernel, but stops before passing the control |
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to the kernel. |
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Here the command sequence for the ipam390 board: |
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- load the linux kernel image into ram: |
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U-Boot > nand read c0100000 2 200000 400000 |
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NAND read: device 0 offset 0x200000, size 0x400000 |
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4194304 bytes read: OK |
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- generate the bootparms image: |
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U-Boot > spl export atags c0100000 |
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## Booting kernel from Legacy Image at c0100000 ... |
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Image Name: Linux-3.5.1 |
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Image Type: ARM Linux Kernel Image (uncompressed) |
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Data Size: 2504280 Bytes = 2.4 MiB |
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Load Address: c0008000 |
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Entry Point: c0008000 |
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Verifying Checksum ... OK |
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Loading Kernel Image ... OK |
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subcommand not supported |
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subcommand not supported |
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Argument image is now in RAM at: 0xc0000100 |
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- copy the bootparms image into nand: |
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U-Boot > mtdparts |
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device nand0 <davinci_nand.0>, # parts = 6 |
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#: name size offset mask_flags |
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0: u-boot-env 0x00020000 0x00000000 0 |
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1: u-boot 0x00160000 0x00020000 0 |
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2: bootparms 0x00020000 0x00180000 0 |
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3: factory-info 0x00060000 0x001a0000 0 |
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4: kernel 0x00400000 0x00200000 0 |
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5: rootfs 0x07a00000 0x00600000 0 |
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active partition: nand0,0 - (u-boot-env) 0x00020000 @ 0x00000000 |
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defaults: |
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mtdids : nand0=davinci_nand.0 |
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mtdparts: mtdparts=davinci_nand.0:128k(u-boot-env),1408k(u-boot),128k(bootparms),384k(factory-info),4M(kernel),-(rootfs) |
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U-Boot > nand erase.part bootparms |
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NAND erase.part: device 0 offset 0x180000, size 0x20000 |
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Erasing at 0x180000 -- 100% complete. |
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OK |
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U-Boot > nand write c0000100 180000 20000 |
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NAND write: device 0 offset 0x180000, size 0x20000 |
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131072 bytes written: OK |
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U-Boot > |
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You can use also the predefined U-Boot Environment variable "setbootparms", |
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which will do all the above steps in one command: |
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U-Boot > print setbootparms |
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setbootparms=nand read c0100000 200000 400000;spl export atags c0100000;nand erase.part bootparms;nand write c0000100 180000 20000 |
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U-Boot > run setbootparms |
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NAND read: device 0 offset 0x200000, size 0x400000 |
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4194304 bytes read: OK |
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## Booting kernel from Legacy Image at c0100000 ... |
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Image Name: Linux-3.5.1 |
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Image Type: ARM Linux Kernel Image (uncompressed) |
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Data Size: 2504280 Bytes = 2.4 MiB |
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Load Address: c0008000 |
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Entry Point: c0008000 |
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Verifying Checksum ... OK |
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Loading Kernel Image ... OK |
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subcommand not supported |
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subcommand not supported |
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Argument image is now in RAM at: 0xc0000100 |
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NAND erase.part: device 0 offset 0x180000, size 0x20000 |
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Erasing at 0x180000 -- 100% complete. |
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OK |
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NAND write: device 0 offset 0x180000, size 0x20000 |
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131072 bytes written: OK |
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U-Boot > |
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Links |
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===== |
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[1] |
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http://sourceforge.net/projects/dvflashutils/files/OMAP-L138/ |
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@ -0,0 +1,202 @@ |
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; General settings that can be overwritten in the host code |
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; that calls the AISGen library. |
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[General] |
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; Can be 8 or 16 - used in emifa |
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busWidth=8 |
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; SPIMASTER,I2CMASTER,EMIFA,NAND,EMAC,UART,PCI,HPI,USB,MMC_SD,VLYNQ,RAW |
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BootMode=UART |
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; 8,16,24 - used for SPI,I2C |
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;AddrWidth=8 |
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; NO_CRC,SECTION_CRC,SINGLE_CRC |
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crcCheckType=NO_CRC |
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; This section allows setting the PLL0 system clock with a |
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; specified multiplier and divider as shown. The clock source |
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; can also be chosen for internal or external. |
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; |------24|------16|-------8|-------0| |
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; PLL0CFG0: | CLKMODE| PLLM | PREDIV | POSTDIV| |
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; PLL0CFG1: | RSVD | PLLDIV1| PLLDIV3| PLLDIV7| |
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;[PLL0CONFIG] |
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;PLL0CFG0 = 0x00180001 |
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;PLL0CFG1 = 0x00000205 |
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[PLLANDCLOCKCONFIG] |
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PLL0CFG0 = 0x00180001 |
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PLL0CFG1 = 0x00000205 |
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PERIPHCLKCFG = 0x00000051 |
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; This section allows setting up the PLL1. Usually this will |
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; take place as part of the EMIF3a DDR setup. The format of |
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; the input args is as follows: |
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; |------24|------16|-------8|-------0| |
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; PLL1CFG0: | PLLM| POSTDIV| PLLDIV1| PLLDIV2| |
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; PLL1CFG1: | RSVD | PLLDIV3| |
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[PLL1CONFIG] |
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PLL1CFG0 = 0x18010001 |
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PLL1CFG1 = 0x00000002 |
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; This section lets us configure the peripheral interface |
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; of the current booting peripheral (I2C, SPI, or UART). |
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; Use with caution. The format of the PERIPHCLKCFG field |
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; is as follows: |
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; SPI: |------24|------16|-------8|-------0| |
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; | RSVD |PRESCALE| |
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; |
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; I2C: |------24|------16|-------8|-------0| |
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; | RSVD |PRESCALE| CLKL | CLKH | |
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; |
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; UART: |------24|------16|-------8|-------0| |
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; | RSVD | OSR | DLH | DLL | |
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[PERIPHCLKCFG] |
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PERIPHCLKCFG = 0x00000051 |
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; This section can be used to configure the PLL1 and the EMIF3a registers |
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; for starting the DDR2 interface. |
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; See PLL1CONFIG section for the format of the PLL1CFG fields. |
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; |------24|------16|-------8|-------0| |
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; PLL1CFG0: | PLL1CFG | |
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; PLL1CFG1: | PLL1CFG | |
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; DDRPHYC1R: | DDRPHYC1R | |
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; SDCR: | SDCR | |
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; SDTIMR: | SDTIMR | |
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; SDTIMR2: | SDTIMR2 | |
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; SDRCR: | SDRCR | |
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; CLK2XSRC: | CLK2XSRC | |
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[EMIF3DDR] |
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PLL1CFG0 = 0x18010001 |
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PLL1CFG1 = 0x00000002 |
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DDRPHYC1R = 0x000000C2 |
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SDCR = 0x0017C432 |
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SDTIMR = 0x26922A09 |
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SDTIMR2 = 0x4414C722 |
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SDRCR = 0x00000498 |
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CLK2XSRC = 0x00000000 |
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; This section can be used to configure the EMIFA to use |
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; CS0 as an SDRAM interface. The fields required to do this |
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; are given below. |
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; |------24|------16|-------8|-------0| |
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; SDBCR: | SDBCR | |
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; SDTIMR: | SDTIMR | |
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; SDRSRPDEXIT: | SDRSRPDEXIT | |
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; SDRCR: | SDRCR | |
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; DIV4p5_CLK_ENABLE: | DIV4p5_CLK_ENABLE | |
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;[EMIF25SDRAM] |
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;SDBCR = 0x00004421 |
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;SDTIMR = 0x42215810 |
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;SDRSRPDEXIT = 0x00000009 |
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;SDRCR = 0x00000410 |
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;DIV4p5_CLK_ENABLE = 0x00000001 |
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; This section can be used to configure the async chip selects |
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; of the EMIFA (CS2-CS5). The fields required to do this |
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; are given below. |
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; |------24|------16|-------8|-------0| |
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; A1CR: | A1CR | |
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; A2CR: | A2CR | |
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; A3CR: | A3CR | |
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; A4CR: | A4CR | |
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; NANDFCR: | NANDFCR | |
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;[EMIF25ASYNC] |
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;A1CR = 0x00000000 |
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;A2CR = 0x00000000 |
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;A3CR = 0x00000000 |
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;A4CR = 0x00000000 |
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;NANDFCR = 0x00000000 |
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[EMIF25ASYNC] |
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A1CR = 0x00000000 |
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A2CR = 0x3FFFFFFE |
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A3CR = 0x00000000 |
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A4CR = 0x00000000 |
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NANDFCR = 0x00000012 |
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; This section should be used in place of PLL0CONFIG when |
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; the I2C, SPI, or UART modes are being used. This ensures that |
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; the system PLL and the peripheral's clocks are changed together. |
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; See PLL0CONFIG section for the format of the PLL0CFG fields. |
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; See PERIPHCLKCFG section for the format of the CLKCFG field. |
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; |------24|------16|-------8|-------0| |
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; PLL0CFG0: | PLL0CFG | |
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; PLL0CFG1: | PLL0CFG | |
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; PERIPHCLKCFG: | CLKCFG | |
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;[PLLANDCLOCKCONFIG] |
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;PLL0CFG0 = 0x00180001 |
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;PLL0CFG1 = 0x00000205 |
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;PERIPHCLKCFG = 0x00010032 |
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; This section should be used to setup the power state of modules |
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; of the two PSCs. This section can be included multiple times to |
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; allow the configuration of any or all of the device modules. |
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; |------24|------16|-------8|-------0| |
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; LPSCCFG: | PSCNUM | MODULE | PD | STATE | |
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;[PSCCONFIG] |
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;LPSCCFG= |
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; This section allows setting of a single PINMUX register. |
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; This section can be included multiple times to allow setting |
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; as many PINMUX registers as needed. |
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; |------24|------16|-------8|-------0| |
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; REGNUM: | regNum | |
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; MASK: | mask | |
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; VALUE: | value | |
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;[PINMUX] |
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;REGNUM = 5 |
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;MASK = 0x00FF0000 |
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;VALUE = 0x00880000 |
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|
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; No Params required - simply include this section for the fast boot |
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; function to be called |
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;[FASTBOOT] |
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; This section allows setting up the PLL1. Usually this will |
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; take place as part of the EMIF3a DDR setup. The format of |
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; the input args is as follows: |
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; |------24|------16|-------8|-------0| |
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; PLL1CFG0: | PLLM| POSTDIV| PLLDIV1| PLLDIV2| |
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; PLL1CFG1: | RSVD | PLLDIV3| |
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;[PLL1CONFIG] |
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;PLL1CFG0 = 0x15010001 |
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;PLL1CFG1 = 0x00000002 |
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|
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; This section can be used to configure the PLL1 and the EMIF3a registers |
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; for starting the DDR2 interface on ARM-boot D800K002 devices. |
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; |------24|------16|-------8|-------0| |
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; DDRPHYC1R: | DDRPHYC1R | |
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; SDCR: | SDCR | |
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; SDTIMR: | SDTIMR | |
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; SDTIMR2: | SDTIMR2 | |
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; SDRCR: | SDRCR | |
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; CLK2XSRC: | CLK2XSRC | |
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;[ARM_EMIF3DDR_PATCHFXN] |
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;DDRPHYC1R = 0x000000C2 |
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;SDCR = 0x0017C432 |
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;SDTIMR = 0x26922A09 |
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;SDTIMR2 = 0x4414C722 |
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;SDRCR = 0x00000498 |
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;CLK2XSRC = 0x00000000 |
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|
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; This section can be used to configure the PLL1 and the EMIF3a registers |
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; for starting the DDR2 interface on DSP-boot D800K002 devices. |
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; |------24|------16|-------8|-------0| |
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; DDRPHYC1R: | DDRPHYC1R | |
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; SDCR: | SDCR | |
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; SDTIMR: | SDTIMR | |
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; SDTIMR2: | SDTIMR2 | |
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; SDRCR: | SDRCR | |
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; CLK2XSRC: | CLK2XSRC | |
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;[DSP_EMIF3DDR_PATCHFXN] |
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;DDRPHYC1R = 0x000000C4 |
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;SDCR = 0x08134632 |
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;SDTIMR = 0x26922A09 |
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;SDTIMR2 = 0x0014C722 |
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;SDRCR = 0x00000492 |
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;CLK2XSRC = 0x00000000 |
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;[INPUTFILE] |
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;FILENAME=u-boot.bin |
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;LOADADDRESS=0xC1080000 |
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;ENTRYPOINTADDRESS=0xC1080000 |
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@ -0,0 +1,348 @@ |
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/*
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* (C) Heiko Schocher, DENX Software Engineering, hs@denx.de. |
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* Based on: |
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* U-Boot:board/davinci/da8xxevm/da850evm.c |
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* |
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* Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/
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* |
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* Based on da830evm.c. Original Copyrights follow: |
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* |
||||
* Copyright (C) 2009 Nick Thompson, GE Fanuc, Ltd. <nick.thompson@gefanuc.com> |
||||
* Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net> |
||||
* |
||||
* SPDX-License-Identifier: GPL-2.0+ |
||||
*/ |
||||
|
||||
#include <common.h> |
||||
#include <i2c.h> |
||||
#include <net.h> |
||||
#include <netdev.h> |
||||
#include <spi.h> |
||||
#include <spi_flash.h> |
||||
#include <asm/arch/hardware.h> |
||||
#include <asm/arch/emif_defs.h> |
||||
#include <asm/arch/emac_defs.h> |
||||
#include <asm/arch/pinmux_defs.h> |
||||
#include <asm/io.h> |
||||
#include <asm/arch/davinci_misc.h> |
||||
#include <asm/errno.h> |
||||
#include <asm/gpio.h> |
||||
#include <hwconfig.h> |
||||
#include <bootstage.h> |
||||
|
||||
DECLARE_GLOBAL_DATA_PTR; |
||||
|
||||
#ifdef CONFIG_DRIVER_TI_EMAC |
||||
#ifdef CONFIG_DRIVER_TI_EMAC_USE_RMII |
||||
#define HAS_RMII 1 |
||||
#else |
||||
#define HAS_RMII 0 |
||||
#endif |
||||
#endif /* CONFIG_DRIVER_TI_EMAC */ |
||||
|
||||
void dsp_lpsc_on(unsigned domain, unsigned int id) |
||||
{ |
||||
dv_reg_p mdstat, mdctl, ptstat, ptcmd; |
||||
struct davinci_psc_regs *psc_regs; |
||||
|
||||
psc_regs = davinci_psc0_regs; |
||||
mdstat = &psc_regs->psc0.mdstat[id]; |
||||
mdctl = &psc_regs->psc0.mdctl[id]; |
||||
ptstat = &psc_regs->ptstat; |
||||
ptcmd = &psc_regs->ptcmd; |
||||
|
||||
while (*ptstat & (0x1 << domain)) |
||||
; |
||||
|
||||
if ((*mdstat & 0x1f) == 0x03) |
||||
return; /* Already on and enabled */ |
||||
|
||||
*mdctl |= 0x03; |
||||
|
||||
*ptcmd = 0x1 << domain; |
||||
|
||||
while (*ptstat & (0x1 << domain)) |
||||
; |
||||
while ((*mdstat & 0x1f) != 0x03) |
||||
; /* Probably an overkill... */ |
||||
} |
||||
|
||||
static void dspwake(void) |
||||
{ |
||||
unsigned *resetvect = (unsigned *)DAVINCI_L3CBARAM_BASE; |
||||
u32 val; |
||||
|
||||
/* if the device is ARM only, return */ |
||||
if ((readl(CHIP_REV_ID_REG) & 0x3f) == 0x10) |
||||
return; |
||||
|
||||
if (hwconfig_subarg_cmp_f("dsp", "wake", "no", NULL)) |
||||
return; |
||||
|
||||
*resetvect++ = 0x1E000; /* DSP Idle */ |
||||
/* clear out the next 10 words as NOP */ |
||||
memset(resetvect, 0, sizeof(unsigned) * 10); |
||||
|
||||
/* setup the DSP reset vector */ |
||||
writel(DAVINCI_L3CBARAM_BASE, HOST1CFG); |
||||
|
||||
dsp_lpsc_on(1, DAVINCI_LPSC_GEM); |
||||
val = readl(PSC0_MDCTL + (15 * 4)); |
||||
val |= 0x100; |
||||
writel(val, (PSC0_MDCTL + (15 * 4))); |
||||
} |
||||
|
||||
int misc_init_r(void) |
||||
{ |
||||
dspwake(); |
||||
return 0; |
||||
} |
||||
|
||||
static const struct pinmux_config gpio_pins[] = { |
||||
/* GP7[14] selects bootmode*/ |
||||
{ pinmux(16), 8, 3 }, /* GP7[14] */ |
||||
}; |
||||
|
||||
const struct pinmux_resource pinmuxes[] = { |
||||
#ifdef CONFIG_DRIVER_TI_EMAC |
||||
PINMUX_ITEM(emac_pins_mdio), |
||||
#ifdef CONFIG_DRIVER_TI_EMAC_USE_RMII |
||||
PINMUX_ITEM(emac_pins_rmii), |
||||
#else |
||||
PINMUX_ITEM(emac_pins_mii), |
||||
#endif |
||||
#endif |
||||
PINMUX_ITEM(uart2_pins_txrx), |
||||
PINMUX_ITEM(uart2_pins_rtscts), |
||||
PINMUX_ITEM(uart0_pins_txrx), |
||||
PINMUX_ITEM(uart0_pins_rtscts), |
||||
#ifdef CONFIG_NAND_DAVINCI |
||||
PINMUX_ITEM(emifa_pins_cs3), |
||||
PINMUX_ITEM(emifa_pins_nand), |
||||
#endif |
||||
PINMUX_ITEM(gpio_pins), |
||||
}; |
||||
|
||||
const int pinmuxes_size = ARRAY_SIZE(pinmuxes); |
||||
|
||||
const struct lpsc_resource lpsc[] = { |
||||
{ DAVINCI_LPSC_AEMIF }, /* NAND, NOR */ |
||||
{ DAVINCI_LPSC_EMAC }, /* image download */ |
||||
{ DAVINCI_LPSC_UART2 }, /* console */ |
||||
{ DAVINCI_LPSC_UART0 }, /* console */ |
||||
{ DAVINCI_LPSC_GPIO }, |
||||
}; |
||||
|
||||
const int lpsc_size = ARRAY_SIZE(lpsc); |
||||
|
||||
#ifndef CONFIG_DA850_EVM_MAX_CPU_CLK |
||||
#define CONFIG_DA850_EVM_MAX_CPU_CLK 300000000 |
||||
#endif |
||||
|
||||
#define REV_AM18X_EVM 0x100 |
||||
|
||||
/*
|
||||
* get_board_rev() - setup to pass kernel board revision information |
||||
* Returns: |
||||
* bit[0-3] Maximum cpu clock rate supported by onboard SoC |
||||
* 0000b - 300 MHz |
||||
* 0001b - 372 MHz |
||||
* 0010b - 408 MHz |
||||
* 0011b - 456 MHz |
||||
*/ |
||||
u32 get_board_rev(void) |
||||
{ |
||||
char *s; |
||||
u32 maxcpuclk = CONFIG_DA850_EVM_MAX_CPU_CLK; |
||||
u32 rev = 0; |
||||
|
||||
s = getenv("maxcpuclk"); |
||||
if (s) |
||||
maxcpuclk = simple_strtoul(s, NULL, 10); |
||||
|
||||
if (maxcpuclk >= 456000000) |
||||
rev = 3; |
||||
else if (maxcpuclk >= 408000000) |
||||
rev = 2; |
||||
else if (maxcpuclk >= 372000000) |
||||
rev = 1; |
||||
#ifdef CONFIG_DA850_AM18X_EVM |
||||
rev |= REV_AM18X_EVM; |
||||
#endif |
||||
return rev; |
||||
} |
||||
|
||||
int board_early_init_f(void) |
||||
{ |
||||
/*
|
||||
* Power on required peripherals |
||||
* ARM does not have access by default to PSC0 and PSC1 |
||||
* assuming here that the DSP bootloader has set the IOPU |
||||
* such that PSC access is available to ARM |
||||
*/ |
||||
if (da8xx_configure_lpsc_items(lpsc, ARRAY_SIZE(lpsc))) |
||||
return 1; |
||||
|
||||
return 0; |
||||
} |
||||
|
||||
int board_init(void) |
||||
{ |
||||
#ifndef CONFIG_USE_IRQ |
||||
irq_init(); |
||||
#endif |
||||
|
||||
/* arch number of the board */ |
||||
gd->bd->bi_arch_number = MACH_TYPE_DAVINCI_DA850_EVM; |
||||
|
||||
/* address of boot parameters */ |
||||
gd->bd->bi_boot_params = LINUX_BOOT_PARAM_ADDR; |
||||
|
||||
/* setup the SUSPSRC for ARM to control emulation suspend */ |
||||
writel(readl(&davinci_syscfg_regs->suspsrc) & |
||||
~(DAVINCI_SYSCFG_SUSPSRC_EMAC | DAVINCI_SYSCFG_SUSPSRC_I2C | |
||||
DAVINCI_SYSCFG_SUSPSRC_SPI1 | DAVINCI_SYSCFG_SUSPSRC_TIMER0 | |
||||
DAVINCI_SYSCFG_SUSPSRC_UART0), |
||||
&davinci_syscfg_regs->suspsrc); |
||||
|
||||
/* configure pinmux settings */ |
||||
if (davinci_configure_pin_mux_items(pinmuxes, ARRAY_SIZE(pinmuxes))) |
||||
return 1; |
||||
|
||||
#ifdef CONFIG_DRIVER_TI_EMAC |
||||
davinci_emac_mii_mode_sel(HAS_RMII); |
||||
#endif /* CONFIG_DRIVER_TI_EMAC */ |
||||
|
||||
/* enable the console UART */ |
||||
writel((DAVINCI_UART_PWREMU_MGMT_FREE | DAVINCI_UART_PWREMU_MGMT_URRST | |
||||
DAVINCI_UART_PWREMU_MGMT_UTRST), |
||||
#if (CONFIG_SYS_NS16550_COM1 == DAVINCI_UART0_BASE) |
||||
&davinci_uart0_ctrl_regs->pwremu_mgmt); |
||||
#else |
||||
&davinci_uart2_ctrl_regs->pwremu_mgmt); |
||||
#endif |
||||
return 0; |
||||
} |
||||
|
||||
#ifdef CONFIG_DRIVER_TI_EMAC |
||||
/*
|
||||
* Initializes on-board ethernet controllers. |
||||
*/ |
||||
int board_eth_init(bd_t *bis) |
||||
{ |
||||
if (!davinci_emac_initialize()) { |
||||
printf("Error: Ethernet init failed!\n"); |
||||
return -1; |
||||
} |
||||
|
||||
return 0; |
||||
} |
||||
#endif /* CONFIG_DRIVER_TI_EMAC */ |
||||
|
||||
static int init_led(int gpio, char *name, int val) |
||||
{ |
||||
int ret; |
||||
|
||||
ret = gpio_request(gpio, name); |
||||
if (ret) |
||||
return -1; |
||||
ret = gpio_direction_output(gpio, val); |
||||
if (ret) |
||||
return -1; |
||||
|
||||
return gpio; |
||||
} |
||||
|
||||
#define LED_ON 0 |
||||
#define LED_OFF 1 |
||||
|
||||
#if !defined(CONFIG_SPL_BUILD) |
||||
#ifdef CONFIG_SHOW_BOOT_PROGRESS |
||||
void show_boot_progress(int status) |
||||
{ |
||||
static int red; |
||||
static int green; |
||||
|
||||
if (red == 0) |
||||
red = init_led(CONFIG_IPAM390_GPIO_LED_RED, "red", LED_OFF); |
||||
if (red != CONFIG_IPAM390_GPIO_LED_RED) |
||||
return; |
||||
if (green == 0) |
||||
green = init_led(CONFIG_IPAM390_GPIO_LED_GREEN, "green", |
||||
LED_OFF); |
||||
if (green != CONFIG_IPAM390_GPIO_LED_GREEN) |
||||
return; |
||||
|
||||
switch (status) { |
||||
case BOOTSTAGE_ID_RUN_OS: |
||||
/*
|
||||
* set normal state |
||||
* LED Red : off |
||||
* LED green: off |
||||
*/ |
||||
gpio_set_value(red, LED_OFF); |
||||
gpio_set_value(green, LED_OFF); |
||||
break; |
||||
case BOOTSTAGE_ID_MAIN_LOOP: |
||||
/*
|
||||
* U-Boot operation |
||||
* LED Red : on |
||||
* LED green: on |
||||
*/ |
||||
gpio_set_value(red, LED_ON); |
||||
gpio_set_value(green, LED_ON); |
||||
break; |
||||
} |
||||
} |
||||
#endif |
||||
#endif |
||||
|
||||
#ifdef CONFIG_SPL_OS_BOOT |
||||
int spl_start_uboot(void) |
||||
{ |
||||
int ret; |
||||
int bootmode = 0; |
||||
|
||||
/*
|
||||
* GP7[14] selects bootmode: |
||||
* 1: boot linux |
||||
* 0: boot u-boot |
||||
* if error accessing gpio boot U-Boot |
||||
* |
||||
* SPL bootmode |
||||
* 0: boot linux |
||||
* 1: boot u-boot |
||||
*/ |
||||
ret = gpio_request(CONFIG_IPAM390_GPIO_BOOTMODE , "bootmode"); |
||||
if (ret) |
||||
bootmode = 1; |
||||
if (!bootmode) { |
||||
ret = gpio_direction_input(CONFIG_IPAM390_GPIO_BOOTMODE); |
||||
if (ret) |
||||
bootmode = 1; |
||||
} |
||||
if (!bootmode) |
||||
ret = gpio_get_value(CONFIG_IPAM390_GPIO_BOOTMODE); |
||||
if (!bootmode) |
||||
if (ret == 0) |
||||
bootmode = 1; |
||||
if (bootmode) { |
||||
/*
|
||||
* Booting U-Boot |
||||
* LED Red : on |
||||
* LED green: off |
||||
*/ |
||||
init_led(CONFIG_IPAM390_GPIO_LED_RED, "red", LED_ON); |
||||
init_led(CONFIG_IPAM390_GPIO_LED_GREEN, "green", LED_OFF); |
||||
} else { |
||||
/*
|
||||
* Booting Linux |
||||
* LED Red : off |
||||
* LED green: off |
||||
*/ |
||||
init_led(CONFIG_IPAM390_GPIO_LED_RED, "red", LED_OFF); |
||||
init_led(CONFIG_IPAM390_GPIO_LED_GREEN, "green", LED_OFF); |
||||
} |
||||
return bootmode; |
||||
} |
||||
#endif |
||||
@ -0,0 +1,53 @@ |
||||
/* |
||||
* (C) Copyright 2002 |
||||
* Gary Jennejohn, DENX Software Engineering, <garyj@denx.de> |
||||
* |
||||
* (C) Copyright 2008 |
||||
* Guennadi Liakhovetki, DENX Software Engineering, <lg@denx.de> |
||||
* |
||||
* SPDX-License-Identifier: GPL-2.0+ |
||||
*/ |
||||
|
||||
MEMORY { .sram : ORIGIN = CONFIG_SPL_TEXT_BASE,\ |
||||
LENGTH = CONFIG_SPL_MAX_FOOTPRINT } |
||||
|
||||
OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") |
||||
OUTPUT_ARCH(arm) |
||||
ENTRY(_start) |
||||
SECTIONS |
||||
{ |
||||
. = 0x00000000; |
||||
|
||||
. = ALIGN(4); |
||||
.text : |
||||
{ |
||||
__start = .; |
||||
arch/arm/cpu/arm926ejs/start.o (.text*) |
||||
*(.text*) |
||||
} >.sram |
||||
|
||||
. = ALIGN(4); |
||||
.rodata : { *(SORT_BY_ALIGNMENT(.rodata*)) } >.sram |
||||
|
||||
. = ALIGN(4); |
||||
.data : { *(SORT_BY_ALIGNMENT(.data*)) } >.sram |
||||
|
||||
. = ALIGN(4); |
||||
.rel.dyn : { |
||||
__rel_dyn_start = .; |
||||
*(.rel*) |
||||
__rel_dyn_end = .; |
||||
} >.sram |
||||
|
||||
.bss : |
||||
{ |
||||
. = ALIGN(4); |
||||
__bss_start = .; |
||||
*(.bss*) |
||||
. = ALIGN(4); |
||||
__bss_end = .; |
||||
} >.sram |
||||
|
||||
__image_copy_end = .; |
||||
_end = .; |
||||
} |
||||
@ -0,0 +1,331 @@ |
||||
/*
|
||||
* (C) Heiko Schocher, DENX Software Engineering, hs@denx.de. |
||||
* Based on: |
||||
* U-Boot:include/configs/da850evm.h |
||||
* |
||||
* Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/
|
||||
* |
||||
* Based on davinci_dvevm.h. Original Copyrights follow: |
||||
* |
||||
* Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net> |
||||
* |
||||
* SPDX-License-Identifier: GPL-2.0+ |
||||
*/ |
||||
|
||||
#ifndef __CONFIG_H |
||||
#define __CONFIG_H |
||||
|
||||
/*
|
||||
* Board |
||||
*/ |
||||
#define CONFIG_DRIVER_TI_EMAC |
||||
#define CONFIG_BARIX_IPAM390 |
||||
|
||||
/*
|
||||
* SoC Configuration |
||||
*/ |
||||
#define CONFIG_MACH_DAVINCI_DA850_EVM |
||||
#define CONFIG_ARM926EJS /* arm926ejs CPU core */ |
||||
#define CONFIG_SOC_DA8XX /* TI DA8xx SoC */ |
||||
#define CONFIG_SOC_DA850 /* TI DA850 SoC */ |
||||
#define CONFIG_SYS_EXCEPTION_VECTORS_HIGH |
||||
#define CONFIG_SYS_CLK_FREQ clk_get(DAVINCI_ARM_CLKID) |
||||
#define CONFIG_SYS_OSCIN_FREQ 24000000 |
||||
#define CONFIG_SYS_TIMERBASE DAVINCI_TIMER0_BASE |
||||
#define CONFIG_SYS_HZ_CLOCK clk_get(DAVINCI_AUXCLK_CLKID) |
||||
#define CONFIG_SYS_HZ 1000 |
||||
#define CONFIG_SYS_DA850_PLL_INIT |
||||
#define CONFIG_SYS_DA850_DDR_INIT |
||||
#define CONFIG_SYS_TEXT_BASE 0xc1080000 |
||||
|
||||
/*
|
||||
* Memory Info |
||||
*/ |
||||
#define CONFIG_SYS_MALLOC_LEN (0x10000 + 1*1024*1024) /* malloc() len */ |
||||
#define PHYS_SDRAM_1 DAVINCI_DDR_EMIF_DATA_BASE /* DDR Start */ |
||||
#define PHYS_SDRAM_1_SIZE (128 << 20) /* SDRAM size 128MB */ |
||||
#define CONFIG_MAX_RAM_BANK_SIZE (512 << 20) /* max size from SPRS586*/ |
||||
|
||||
/* memtest start addr */ |
||||
#define CONFIG_SYS_MEMTEST_START (PHYS_SDRAM_1 + 0x2000000) |
||||
|
||||
/* memtest will be run on 16MB */ |
||||
#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + 16 * 1024 * 1024) |
||||
|
||||
#define CONFIG_NR_DRAM_BANKS 1 /* we have 1 bank of DRAM */ |
||||
|
||||
#define CONFIG_SYS_DA850_SYSCFG_SUSPSRC ( \ |
||||
DAVINCI_SYSCFG_SUSPSRC_TIMER0 | \
|
||||
DAVINCI_SYSCFG_SUSPSRC_UART2 | \
|
||||
DAVINCI_SYSCFG_SUSPSRC_UART0 | \
|
||||
DAVINCI_SYSCFG_SUSPSRC_EMAC) |
||||
|
||||
/*
|
||||
* PLL configuration |
||||
*/ |
||||
#define CONFIG_SYS_DV_CLKMODE 0 |
||||
#define CONFIG_SYS_DA850_PLL0_POSTDIV 1 |
||||
#define CONFIG_SYS_DA850_PLL0_PLLDIV1 0x8000 |
||||
#define CONFIG_SYS_DA850_PLL0_PLLDIV2 0x8001 |
||||
#define CONFIG_SYS_DA850_PLL0_PLLDIV3 0x8002 |
||||
#define CONFIG_SYS_DA850_PLL0_PLLDIV4 0x8003 |
||||
#define CONFIG_SYS_DA850_PLL0_PLLDIV5 0x8002 |
||||
#define CONFIG_SYS_DA850_PLL0_PLLDIV6 CONFIG_SYS_DA850_PLL0_PLLDIV1 |
||||
#define CONFIG_SYS_DA850_PLL0_PLLDIV7 0x8005 |
||||
|
||||
#define CONFIG_SYS_DA850_PLL1_POSTDIV 1 |
||||
#define CONFIG_SYS_DA850_PLL1_PLLDIV1 0x8000 |
||||
#define CONFIG_SYS_DA850_PLL1_PLLDIV2 0x8001 |
||||
#define CONFIG_SYS_DA850_PLL1_PLLDIV3 0x8002 |
||||
|
||||
#define CONFIG_SYS_DA850_PLL0_PLLM 24 |
||||
#define CONFIG_SYS_DA850_PLL1_PLLM 24 |
||||
|
||||
/*
|
||||
* DDR2 memory configuration |
||||
*/ |
||||
#define CONFIG_SYS_DA850_DDR2_DDRPHYCR (DV_DDR_PHY_PWRDNEN | \ |
||||
DV_DDR_PHY_EXT_STRBEN | \
|
||||
(0x2 << DV_DDR_PHY_RD_LATENCY_SHIFT)) |
||||
#define CONFIG_SYS_DA850_DDR2_SDRCR 0x00000498 |
||||
|
||||
#define CONFIG_SYS_DA850_DDR2_SDBCR2 0x00000004 |
||||
#define CONFIG_SYS_DA850_DDR2_PBBPR 0x00000020 |
||||
|
||||
|
||||
#define CONFIG_SYS_DA850_DDR2_SDTIMR ( \ |
||||
(13 << DV_DDR_SDTMR1_RFC_SHIFT) | \
|
||||
(2 << DV_DDR_SDTMR1_RP_SHIFT) | \
|
||||
(2 << DV_DDR_SDTMR1_RCD_SHIFT) | \
|
||||
(2 << DV_DDR_SDTMR1_WR_SHIFT) | \
|
||||
(5 << DV_DDR_SDTMR1_RAS_SHIFT) | \
|
||||
(8 << DV_DDR_SDTMR1_RC_SHIFT) | \
|
||||
(1 << DV_DDR_SDTMR1_RRD_SHIFT) | \
|
||||
(1 << DV_DDR_SDTMR1_WTR_SHIFT)) |
||||
|
||||
#define CONFIG_SYS_DA850_DDR2_SDTIMR2 ( \ |
||||
(8 << DV_DDR_SDTMR2_RASMAX_SHIFT) | \
|
||||
(2 << DV_DDR_SDTMR2_XP_SHIFT) | \
|
||||
(0 << DV_DDR_SDTMR2_ODT_SHIFT) | \
|
||||
(14 << DV_DDR_SDTMR2_XSNR_SHIFT) | \
|
||||
(0xc7 << DV_DDR_SDTMR2_XSRD_SHIFT) | \
|
||||
(1 << DV_DDR_SDTMR2_RTP_SHIFT) | \
|
||||
(2 << DV_DDR_SDTMR2_CKE_SHIFT)) |
||||
|
||||
#define CONFIG_SYS_DA850_DDR2_SDBCR ( \ |
||||
(1 << DV_DDR_SDCR_DDR2EN_SHIFT) | \
|
||||
(1 << DV_DDR_SDCR_DDRDRIVE0_SHIFT) | \
|
||||
(1 << DV_DDR_SDCR_DDREN_SHIFT) | \
|
||||
(1 << DV_DDR_SDCR_SDRAMEN_SHIFT) | \
|
||||
(1 << DV_DDR_SDCR_BUS_WIDTH_SHIFT) | \
|
||||
(2 << DV_DDR_SDCR_CL_SHIFT) | \
|
||||
(3 << DV_DDR_SDCR_IBANK_SHIFT) | \
|
||||
(2 << DV_DDR_SDCR_PAGESIZE_SHIFT)) |
||||
|
||||
#define CONFIG_SYS_DA850_CS3CFG (DAVINCI_ABCR_WSETUP(2) | \ |
||||
DAVINCI_ABCR_WSTROBE(2) | \
|
||||
DAVINCI_ABCR_WHOLD(1) | \
|
||||
DAVINCI_ABCR_RSETUP(1) | \
|
||||
DAVINCI_ABCR_RSTROBE(4) | \
|
||||
DAVINCI_ABCR_RHOLD(0) | \
|
||||
DAVINCI_ABCR_TA(1) | \
|
||||
DAVINCI_ABCR_ASIZE_8BIT) |
||||
|
||||
|
||||
/*
|
||||
* Serial Driver info |
||||
*/ |
||||
#define CONFIG_SYS_NS16550 |
||||
#define CONFIG_SYS_NS16550_SERIAL |
||||
#define CONFIG_SYS_NS16550_REG_SIZE -4 /* NS16550 register size */ |
||||
#define CONFIG_SYS_NS16550_COM1 DAVINCI_UART0_BASE /* Base address of UART0 */ |
||||
#define CONFIG_SYS_NS16550_CLK clk_get(DAVINCI_UART2_CLKID) |
||||
#define CONFIG_CONS_INDEX 1 /* use UART0 for console */ |
||||
#define CONFIG_BAUDRATE 115200 /* Default baud rate */ |
||||
|
||||
/*
|
||||
* Flash & Environment |
||||
*/ |
||||
#define CONFIG_NAND_DAVINCI |
||||
#define CONFIG_SYS_NO_FLASH |
||||
#define CONFIG_ENV_IS_IN_NAND /* U-Boot env in NAND Flash */ |
||||
#define CONFIG_ENV_OFFSET 0x0 /* Block 0--not used by bootcode */ |
||||
#define CONFIG_ENV_SIZE (128 << 10) |
||||
#define CONFIG_SYS_NAND_USE_FLASH_BBT |
||||
#define CONFIG_SYS_NAND_4BIT_HW_ECC_OOBFIRST |
||||
#define CONFIG_SYS_NAND_PAGE_2K |
||||
#define CONFIG_SYS_NAND_CS 3 |
||||
#define CONFIG_SYS_NAND_BASE DAVINCI_ASYNC_EMIF_DATA_CE3_BASE |
||||
#define CONFIG_SYS_NAND_MASK_CLE 0x10 |
||||
#define CONFIG_SYS_NAND_MASK_ALE 0x8 |
||||
#undef CONFIG_SYS_NAND_HW_ECC |
||||
#define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND devices */ |
||||
#define CONFIG_SYS_NAND_HW_ECC_OOBFIRST |
||||
#define CONFIG_SYS_NAND_5_ADDR_CYCLE |
||||
#define CONFIG_SYS_NAND_PAGE_SIZE (2 << 10) |
||||
#define CONFIG_SYS_NAND_BLOCK_SIZE (128 << 10) |
||||
#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x40000 |
||||
#define CONFIG_SYS_NAND_U_BOOT_SIZE 0x120000 |
||||
#define CONFIG_SYS_NAND_U_BOOT_DST 0xc1080000 |
||||
#define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_NAND_U_BOOT_DST |
||||
#define CONFIG_SYS_NAND_U_BOOT_RELOC_SP (CONFIG_SYS_NAND_U_BOOT_DST - \ |
||||
CONFIG_SYS_NAND_U_BOOT_SIZE - \
|
||||
CONFIG_SYS_MALLOC_LEN - \
|
||||
GENERATED_GBL_DATA_SIZE) |
||||
#define CONFIG_SYS_NAND_ECCPOS { \ |
||||
24, 25, 26, 27, 28, \
|
||||
29, 30, 31, 32, 33, 34, 35, 36, 37, 38, \
|
||||
39, 40, 41, 42, 43, 44, 45, 46, 47, 48, \
|
||||
49, 50, 51, 52, 53, 54, 55, 56, 57, 58, \
|
||||
59, 60, 61, 62, 63 } |
||||
#define CONFIG_SYS_NAND_PAGE_COUNT 64 |
||||
#define CONFIG_SYS_NAND_BAD_BLOCK_POS 0 |
||||
#define CONFIG_SYS_NAND_ECCSIZE 512 |
||||
#define CONFIG_SYS_NAND_ECCBYTES 10 |
||||
#define CONFIG_SYS_NAND_OOBSIZE 64 |
||||
#define CONFIG_SPL_NAND_SUPPORT |
||||
#define CONFIG_SPL_NAND_BASE |
||||
#define CONFIG_SPL_NAND_DRIVERS |
||||
#define CONFIG_SPL_NAND_ECC |
||||
#define CONFIG_SPL_NAND_SIMPLE |
||||
#define CONFIG_SPL_NAND_LOAD |
||||
|
||||
/*
|
||||
* Network & Ethernet Configuration |
||||
*/ |
||||
#ifdef CONFIG_DRIVER_TI_EMAC |
||||
#define CONFIG_DRIVER_TI_EMAC_USE_RMII |
||||
#define CONFIG_BOOTP_DEFAULT |
||||
#define CONFIG_BOOTP_DNS |
||||
#define CONFIG_BOOTP_DNS2 |
||||
#define CONFIG_BOOTP_SEND_HOSTNAME |
||||
#define CONFIG_NET_RETRY_COUNT 10 |
||||
#endif |
||||
|
||||
/*
|
||||
* U-Boot general configuration |
||||
*/ |
||||
#define CONFIG_MISC_INIT_R |
||||
#define CONFIG_BOARD_EARLY_INIT_F |
||||
#define CONFIG_BOOTFILE "uImage" /* Boot file name */ |
||||
#define CONFIG_SYS_PROMPT "U-Boot > " /* Command Prompt */ |
||||
#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ |
||||
#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) |
||||
#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ |
||||
#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Args Buffer Size */ |
||||
#define CONFIG_SYS_LOAD_ADDR (PHYS_SDRAM_1 + 0x700000) |
||||
#define CONFIG_VERSION_VARIABLE |
||||
#define CONFIG_AUTO_COMPLETE |
||||
#define CONFIG_SYS_HUSH_PARSER |
||||
#define CONFIG_CMDLINE_EDITING |
||||
#define CONFIG_SYS_LONGHELP |
||||
#define CONFIG_CRC32_VERIFY |
||||
#define CONFIG_MX_CYCLIC |
||||
|
||||
/*
|
||||
* Linux Information |
||||
*/ |
||||
#define LINUX_BOOT_PARAM_ADDR (PHYS_SDRAM_1 + 0x100) |
||||
#define CONFIG_HWCONFIG /* enable hwconfig */ |
||||
#define CONFIG_CMDLINE_TAG |
||||
#define CONFIG_REVISION_TAG |
||||
#define CONFIG_SETUP_MEMORY_TAGS |
||||
#define CONFIG_BOOTARGS \ |
||||
"mem=128M console=ttyS0,115200n8 root=/dev/mtdblock0p4 rw noinitrd ip=dhcp" |
||||
#define CONFIG_BOOTDELAY 3 |
||||
#define CONFIG_EXTRA_ENV_SETTINGS \ |
||||
"hwconfig=dsp:wake=yes\0" \
|
||||
"addmtd=setenv bootargs ${bootargs} ${mtdparts}\0" \
|
||||
"mtdids=" MTDIDS_DEFAULT "\0" \
|
||||
"mtdparts=" MTDPARTS_DEFAULT "\0" \
|
||||
"setbootparms=nand read c0100000 200000 400000;" \
|
||||
"spl export atags c0100000;" \
|
||||
"nand erase.part bootparms;" \
|
||||
"nand write c0000100 180000 20000\0" \
|
||||
"\0" |
||||
|
||||
/*
|
||||
* U-Boot commands |
||||
*/ |
||||
#include <config_cmd_default.h> |
||||
#define CONFIG_CMD_ENV |
||||
#define CONFIG_CMD_ASKENV |
||||
#define CONFIG_CMD_DHCP |
||||
#define CONFIG_CMD_DIAG |
||||
#define CONFIG_CMD_MII |
||||
#define CONFIG_CMD_PING |
||||
#define CONFIG_CMD_SAVES |
||||
#define CONFIG_CMD_MEMORY |
||||
|
||||
#ifdef CONFIG_CMD_BDI |
||||
#define CONFIG_CLOCKS |
||||
#endif |
||||
|
||||
#ifndef CONFIG_DRIVER_TI_EMAC |
||||
#undef CONFIG_CMD_NET |
||||
#undef CONFIG_CMD_DHCP |
||||
#undef CONFIG_CMD_MII |
||||
#undef CONFIG_CMD_PING |
||||
#endif |
||||
|
||||
#define CONFIG_CMD_NAND |
||||
#define CONFIG_CMD_NAND_TRIMFFS |
||||
|
||||
#define CONFIG_CMD_MTDPARTS |
||||
#define CONFIG_MTD_DEVICE |
||||
#define CONFIG_MTD_PARTITIONS |
||||
#define CONFIG_LZO |
||||
#define CONFIG_RBTREE |
||||
#define CONFIG_CMD_UBI |
||||
#define CONFIG_CMD_UBIFS |
||||
|
||||
#define MTDIDS_NAME_STR "davinci_nand.0" |
||||
#define MTDIDS_DEFAULT "nand0=" MTDIDS_NAME_STR |
||||
#define MTDPARTS_DEFAULT "mtdparts=" MTDIDS_NAME_STR ":" \ |
||||
"128k(u-boot-env)," \
|
||||
"1408k(u-boot)," \
|
||||
"128k(bootparms)," \
|
||||
"384k(factory-info)," \
|
||||
"4M(kernel)," \
|
||||
"-(rootfs)" |
||||
|
||||
/* defines for SPL */ |
||||
#define CONFIG_SPL |
||||
#define CONFIG_SPL_FRAMEWORK |
||||
#define CONFIG_SPL_BOARD_INIT |
||||
#define CONFIG_SYS_SPL_MALLOC_START (CONFIG_SYS_TEXT_BASE - \ |
||||
CONFIG_SYS_MALLOC_LEN) |
||||
#define CONFIG_SYS_SPL_MALLOC_SIZE CONFIG_SYS_MALLOC_LEN |
||||
#define CONFIG_SPL_SERIAL_SUPPORT |
||||
#define CONFIG_SPL_LIBCOMMON_SUPPORT |
||||
#define CONFIG_SPL_LIBGENERIC_SUPPORT |
||||
#define CONFIG_SPL_LDSCRIPT "board/$(BOARDDIR)/u-boot-spl-ipam390.lds" |
||||
#define CONFIG_SPL_STACK 0x8001ff00 |
||||
#define CONFIG_SPL_TEXT_BASE 0x80000000 |
||||
#define CONFIG_SPL_MAX_SIZE 0x20000 |
||||
#define CONFIG_SPL_MAX_FOOTPRINT 32768 |
||||
|
||||
/* additions for new relocation code, must added to all boards */ |
||||
#define CONFIG_SYS_SDRAM_BASE 0xc0000000 |
||||
|
||||
#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + 0x1000 - \ |
||||
GENERATED_GBL_DATA_SIZE) |
||||
|
||||
/* add FALCON boot mode */ |
||||
#define CONFIG_CMD_SPL |
||||
#define CONFIG_SPL_OS_BOOT |
||||
#define CONFIG_SYS_NAND_SPL_KERNEL_OFFS 0x00200000 |
||||
#define CONFIG_SYS_SPL_ARGS_ADDR LINUX_BOOT_PARAM_ADDR |
||||
#define CONFIG_CMD_SPL_NAND_OFS 0x00180000 |
||||
#define CONFIG_CMD_SPL_WRITE_SIZE 0x400 |
||||
|
||||
/* GPIO support */ |
||||
#define CONFIG_SPL_GPIO_SUPPORT |
||||
#define CONFIG_DA8XX_GPIO |
||||
#define CONFIG_IPAM390_GPIO_BOOTMODE ((16 * 7) + 14) |
||||
|
||||
#define CONFIG_SHOW_BOOT_PROGRESS |
||||
#define CONFIG_IPAM390_GPIO_LED_RED ((16 * 7) + 11) |
||||
#define CONFIG_IPAM390_GPIO_LED_GREEN ((16 * 7) + 12) |
||||
|
||||
#endif /* __CONFIG_H */ |
||||
Loading…
Reference in new issue