Tom Rini
7 years ago
commit
040b2583c3
@ -0,0 +1,9 @@ |
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// SPDX-License-Identifier: GPL-2.0 |
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/* |
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* Device Tree Source extras for U-Boot for the Ebisu board |
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* |
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* Copyright (C) 2018 Marek Vasut <marek.vasut@gmail.com> |
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*/ |
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|
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#include "r8a77990-ebisu.dts" |
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#include "r8a77990-u-boot.dtsi" |
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@ -0,0 +1,65 @@ |
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/* SPDX-License-Identifier: GPL-2.0 */ |
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/* |
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* Device Tree Source for the ebisu board |
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* |
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* Copyright (C) 2018 Renesas Electronics Corp. |
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*/ |
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|
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/dts-v1/; |
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#include "r8a77990.dtsi" |
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#include <dt-bindings/gpio/gpio.h> |
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|
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/ { |
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model = "Renesas Ebisu board based on r8a77990"; |
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compatible = "renesas,ebisu", "renesas,r8a77990"; |
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|
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aliases { |
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serial0 = &scif2; |
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ethernet0 = &avb; |
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}; |
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|
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chosen { |
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bootargs = "ignore_loglevel"; |
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stdout-path = "serial0:115200n8"; |
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}; |
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|
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memory@48000000 { |
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device_type = "memory"; |
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/* first 128MB is reserved for secure area. */ |
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reg = <0x0 0x48000000 0x0 0x38000000>; |
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}; |
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}; |
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|
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&avb { |
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pinctrl-0 = <&avb_pins>; |
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pinctrl-names = "default"; |
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renesas,no-ether-link; |
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phy-handle = <&phy0>; |
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phy-mode = "rgmii-txid"; |
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status = "okay"; |
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|
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phy0: ethernet-phy@0 { |
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rxc-skew-ps = <1500>; |
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reg = <0>; |
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interrupt-parent = <&gpio2>; |
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interrupts = <21 IRQ_TYPE_LEVEL_LOW>; |
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reset-gpios = <&gpio1 20 GPIO_ACTIVE_LOW>; |
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}; |
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}; |
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|
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&extal_clk { |
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clock-frequency = <48000000>; |
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}; |
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|
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&pfc { |
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avb_pins: avb { |
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mux { |
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groups = "avb_link", "avb_mii"; |
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function = "avb"; |
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}; |
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}; |
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}; |
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|
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&scif2 { |
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status = "okay"; |
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}; |
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@ -0,0 +1,8 @@ |
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// SPDX-License-Identifier: GPL-2.0 |
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/* |
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* Device Tree Source extras for U-Boot on RCar R8A77990 SoC |
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* |
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* Copyright (C) 2018 Marek Vasut <marek.vasut@gmail.com> |
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*/ |
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|
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#include "r8a779x-u-boot.dtsi" |
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@ -0,0 +1,281 @@ |
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/* SPDX-License-Identifier: GPL-2.0 */ |
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/* |
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* Device Tree Source for the r8a77990 SoC |
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* |
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* Copyright (C) 2018 Renesas Electronics Corp. |
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*/ |
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|
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#include <dt-bindings/clock/renesas-cpg-mssr.h> |
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#include <dt-bindings/interrupt-controller/arm-gic.h> |
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/ { |
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compatible = "renesas,r8a77990"; |
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#address-cells = <2>; |
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#size-cells = <2>; |
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cpus { |
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#address-cells = <1>; |
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#size-cells = <0>; |
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|
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/* 1 core only at this point */ |
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a53_0: cpu@0 { |
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compatible = "arm,cortex-a53", "arm,armv8"; |
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reg = <0x0>; |
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device_type = "cpu"; |
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power-domains = <&sysc 5>; |
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next-level-cache = <&L2_CA53>; |
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enable-method = "psci"; |
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}; |
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|
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L2_CA53: cache-controller-0 { |
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compatible = "cache"; |
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power-domains = <&sysc 21>; |
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cache-unified; |
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cache-level = <2>; |
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}; |
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}; |
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|
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extal_clk: extal { |
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compatible = "fixed-clock"; |
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#clock-cells = <0>; |
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/* This value must be overridden by the board */ |
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clock-frequency = <0>; |
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}; |
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pmu_a53 { |
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compatible = "arm,cortex-a53-pmu"; |
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interrupts-extended = <&gic GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>; |
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interrupt-affinity = <&a53_0>; |
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}; |
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psci { |
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compatible = "arm,psci-1.0", "arm,psci-0.2"; |
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method = "smc"; |
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}; |
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soc: soc { |
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compatible = "simple-bus"; |
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interrupt-parent = <&gic>; |
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#address-cells = <2>; |
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#size-cells = <2>; |
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ranges; |
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gpio0: gpio@e6050000 { |
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compatible = "renesas,gpio-r8a77990", |
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"renesas,rcar-gen3-gpio"; |
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reg = <0 0xe6050000 0 0x50>; |
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interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>; |
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#gpio-cells = <2>; |
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gpio-controller; |
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gpio-ranges = <&pfc 0 0 18>; |
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#interrupt-cells = <2>; |
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interrupt-controller; |
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clocks = <&cpg CPG_MOD 912>; |
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power-domains = <&sysc 32>; |
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resets = <&cpg 912>; |
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}; |
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|
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gpio1: gpio@e6051000 { |
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compatible = "renesas,gpio-r8a77990", |
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"renesas,rcar-gen3-gpio"; |
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reg = <0 0xe6051000 0 0x50>; |
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interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; |
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#gpio-cells = <2>; |
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gpio-controller; |
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gpio-ranges = <&pfc 0 32 23>; |
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#interrupt-cells = <2>; |
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interrupt-controller; |
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clocks = <&cpg CPG_MOD 911>; |
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power-domains = <&sysc 32>; |
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resets = <&cpg 911>; |
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}; |
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|
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gpio2: gpio@e6052000 { |
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compatible = "renesas,gpio-r8a77990", |
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"renesas,rcar-gen3-gpio"; |
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reg = <0 0xe6052000 0 0x50>; |
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interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; |
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#gpio-cells = <2>; |
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gpio-controller; |
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gpio-ranges = <&pfc 0 64 26>; |
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#interrupt-cells = <2>; |
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interrupt-controller; |
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clocks = <&cpg CPG_MOD 910>; |
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power-domains = <&sysc 32>; |
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resets = <&cpg 910>; |
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}; |
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gpio3: gpio@e6053000 { |
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compatible = "renesas,gpio-r8a77990", |
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"renesas,rcar-gen3-gpio"; |
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reg = <0 0xe6053000 0 0x50>; |
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interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; |
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#gpio-cells = <2>; |
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gpio-controller; |
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gpio-ranges = <&pfc 0 96 16>; |
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#interrupt-cells = <2>; |
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interrupt-controller; |
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clocks = <&cpg CPG_MOD 909>; |
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power-domains = <&sysc 32>; |
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resets = <&cpg 909>; |
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}; |
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gpio4: gpio@e6054000 { |
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compatible = "renesas,gpio-r8a77990", |
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"renesas,rcar-gen3-gpio"; |
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reg = <0 0xe6054000 0 0x50>; |
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interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>; |
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#gpio-cells = <2>; |
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gpio-controller; |
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gpio-ranges = <&pfc 0 128 11>; |
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#interrupt-cells = <2>; |
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interrupt-controller; |
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clocks = <&cpg CPG_MOD 908>; |
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power-domains = <&sysc 32>; |
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resets = <&cpg 908>; |
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}; |
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gpio5: gpio@e6055000 { |
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compatible = "renesas,gpio-r8a77990", |
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"renesas,rcar-gen3-gpio"; |
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reg = <0 0xe6055000 0 0x50>; |
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interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; |
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#gpio-cells = <2>; |
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gpio-controller; |
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gpio-ranges = <&pfc 0 160 20>; |
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#interrupt-cells = <2>; |
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interrupt-controller; |
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clocks = <&cpg CPG_MOD 907>; |
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power-domains = <&sysc 32>; |
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resets = <&cpg 907>; |
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}; |
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gpio6: gpio@e6055400 { |
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compatible = "renesas,gpio-r8a77990", |
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"renesas,rcar-gen3-gpio"; |
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reg = <0 0xe6055400 0 0x50>; |
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interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; |
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#gpio-cells = <2>; |
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gpio-controller; |
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gpio-ranges = <&pfc 0 192 18>; |
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#interrupt-cells = <2>; |
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interrupt-controller; |
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clocks = <&cpg CPG_MOD 906>; |
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power-domains = <&sysc 32>; |
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resets = <&cpg 906>; |
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}; |
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pfc: pin-controller@e6060000 { |
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compatible = "renesas,pfc-r8a77990"; |
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reg = <0 0xe6060000 0 0x508>; |
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}; |
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cpg: clock-controller@e6150000 { |
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compatible = "renesas,r8a77990-cpg-mssr"; |
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reg = <0 0xe6150000 0 0x1000>; |
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clocks = <&extal_clk>; |
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clock-names = "extal"; |
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#clock-cells = <2>; |
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#power-domain-cells = <0>; |
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#reset-cells = <1>; |
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}; |
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rst: reset-controller@e6160000 { |
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compatible = "renesas,r8a77990-rst"; |
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reg = <0 0xe6160000 0 0x0200>; |
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}; |
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sysc: system-controller@e6180000 { |
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compatible = "renesas,r8a77990-sysc"; |
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reg = <0 0xe6180000 0 0x0400>; |
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#power-domain-cells = <1>; |
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}; |
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avb: ethernet@e6800000 { |
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compatible = "renesas,etheravb-r8a77990", |
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"renesas,etheravb-rcar-gen3"; |
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reg = <0 0xe6800000 0 0x800>, <0 0xe6a00000 0 0x10000>; |
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interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>, |
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<GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>, |
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<GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>, |
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<GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>, |
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<GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>, |
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<GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>, |
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<GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>, |
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<GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>, |
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<GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>, |
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<GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>, |
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<GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>, |
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<GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>, |
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<GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>, |
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<GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>, |
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<GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>, |
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<GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>, |
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<GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>, |
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<GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>, |
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<GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>, |
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<GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>, |
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<GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>, |
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<GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>, |
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<GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>, |
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<GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>, |
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<GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>; |
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interrupt-names = "ch0", "ch1", "ch2", "ch3", |
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"ch4", "ch5", "ch6", "ch7", |
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"ch8", "ch9", "ch10", "ch11", |
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"ch12", "ch13", "ch14", "ch15", |
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"ch16", "ch17", "ch18", "ch19", |
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"ch20", "ch21", "ch22", "ch23", |
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"ch24"; |
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clocks = <&cpg CPG_MOD 812>; |
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power-domains = <&sysc 32>; |
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resets = <&cpg 812>; |
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phy-mode = "rgmii"; |
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#address-cells = <1>; |
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#size-cells = <0>; |
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status = "disabled"; |
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}; |
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scif2: serial@e6e88000 { |
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compatible = "renesas,scif-r8a77990", |
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"renesas,rcar-gen3-scif", "renesas,scif"; |
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reg = <0 0xe6e88000 0 64>; |
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interrupts = <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>; |
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clocks = <&cpg CPG_MOD 310>; |
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clock-names = "fck"; |
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power-domains = <&sysc 32>; |
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resets = <&cpg 310>; |
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status = "disabled"; |
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}; |
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gic: interrupt-controller@f1010000 { |
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compatible = "arm,gic-400"; |
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#interrupt-cells = <3>; |
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#address-cells = <0>; |
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interrupt-controller; |
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reg = <0x0 0xf1010000 0 0x1000>, |
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<0x0 0xf1020000 0 0x20000>, |
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<0x0 0xf1040000 0 0x20000>, |
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<0x0 0xf1060000 0 0x20000>; |
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interrupts = <GIC_PPI 9 |
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(GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_HIGH)>; |
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clocks = <&cpg CPG_MOD 408>; |
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clock-names = "clk"; |
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power-domains = <&sysc 32>; |
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resets = <&cpg 408>; |
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}; |
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|
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prr: chipid@fff00044 { |
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compatible = "renesas,prr"; |
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reg = <0 0xfff00044 0 4>; |
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}; |
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}; |
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|
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timer { |
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compatible = "arm,armv8-timer"; |
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interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>, |
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<&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>, |
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<&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>, |
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<&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>; |
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}; |
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}; |
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@ -0,0 +1,15 @@ |
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if TARGET_EBISU |
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config SYS_SOC |
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default "rmobile" |
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|
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config SYS_BOARD |
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default "ebisu" |
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|
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config SYS_VENDOR |
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default "renesas" |
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|
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config SYS_CONFIG_NAME |
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default "ebisu" |
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endif |
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@ -0,0 +1,6 @@ |
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EBISU BOARD |
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M: Marek Vasut <marek.vasut+renesas@gmail.com> |
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S: Maintained |
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F: board/renesas/ebisu/ |
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F: include/configs/ebisu.h |
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F: configs/r8a77990_ebisu_defconfig |
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@ -0,0 +1,9 @@ |
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#
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# board/renesas/ebisu/Makefile
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#
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# Copyright (C) 2018 Renesas Electronics Corporation
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#
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# SPDX-License-Identifier: GPL-2.0+
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#
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|
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obj-y := ebisu.o
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@ -0,0 +1,86 @@ |
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// SPDX-License-Identifier: GPL-2.0+
|
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/*
|
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* board/renesas/ebisu/ebisu.c |
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* This file is Ebisu board support. |
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* |
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* Copyright (C) 2018 Marek Vasut <marek.vasut+renesas@gmail.com> |
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*/ |
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|
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#include <common.h> |
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#include <malloc.h> |
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#include <netdev.h> |
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#include <dm.h> |
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#include <dm/platform_data/serial_sh.h> |
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#include <asm/processor.h> |
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#include <asm/mach-types.h> |
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#include <asm/io.h> |
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#include <linux/errno.h> |
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#include <asm/arch/sys_proto.h> |
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#include <asm/gpio.h> |
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#include <asm/arch/gpio.h> |
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#include <asm/arch/rmobile.h> |
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#include <asm/arch/rcar-mstp.h> |
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#include <asm/arch/sh_sdhi.h> |
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#include <i2c.h> |
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#include <mmc.h> |
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|
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DECLARE_GLOBAL_DATA_PTR; |
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|
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void s_init(void) |
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{ |
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} |
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|
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#define TMU0_MSTP125 BIT(25) /* secure */ |
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|
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int board_early_init_f(void) |
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{ |
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/* TMU0 */ |
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mstp_clrbits_le32(MSTPSR1, SMSTPCR1, TMU0_MSTP125); |
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|
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return 0; |
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} |
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|
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int board_init(void) |
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{ |
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/* adress of boot parameters */ |
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gd->bd->bi_boot_params = CONFIG_SYS_TEXT_BASE + 0x50000; |
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|
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return 0; |
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} |
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|
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int dram_init(void) |
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{ |
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if (fdtdec_setup_memory_size() != 0) |
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return -EINVAL; |
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|
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return 0; |
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} |
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|
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int dram_init_banksize(void) |
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{ |
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fdtdec_setup_memory_banksize(); |
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|
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return 0; |
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} |
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|
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#define RST_BASE 0xE6160000 |
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#define RST_CA57RESCNT (RST_BASE + 0x40) |
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#define RST_CA53RESCNT (RST_BASE + 0x44) |
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#define RST_RSTOUTCR (RST_BASE + 0x58) |
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#define RST_CA57_CODE 0xA5A5000F |
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#define RST_CA53_CODE 0x5A5A000F |
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|
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void reset_cpu(ulong addr) |
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{ |
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unsigned long midr, cputype; |
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|
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asm volatile("mrs %0, midr_el1" : "=r" (midr)); |
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cputype = (midr >> 4) & 0xfff; |
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|
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if (cputype == 0xd03) |
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writel(RST_CA53_CODE, RST_CA53RESCNT); |
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else if (cputype == 0xd07) |
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writel(RST_CA57_CODE, RST_CA57RESCNT); |
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else |
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hang(); |
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} |
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@ -0,0 +1,64 @@ |
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CONFIG_ARM=y |
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CONFIG_ARCH_RMOBILE=y |
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CONFIG_SYS_TEXT_BASE=0x50000000 |
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CONFIG_SYS_MALLOC_F_LEN=0x2000 |
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CONFIG_RCAR_GEN3=y |
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CONFIG_R8A77990=y |
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CONFIG_TARGET_EBISU=y |
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CONFIG_DEFAULT_DEVICE_TREE="r8a77990-ebisu-u-boot" |
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CONFIG_SMBIOS_PRODUCT_NAME="" |
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CONFIG_FIT=y |
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# CONFIG_ARCH_FIXUP_FDT_MEMORY is not set |
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CONFIG_USE_BOOTARGS=y |
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CONFIG_BOOTARGS="console=ttySC0,115200" |
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CONFIG_SUPPORT_RAW_INITRD=y |
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CONFIG_DEFAULT_FDT_FILE="r8a77990-ebisu.dtb" |
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CONFIG_VERSION_VARIABLE=y |
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CONFIG_HUSH_PARSER=y |
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CONFIG_CMD_BOOTZ=y |
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CONFIG_CMD_GPIO=y |
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CONFIG_CMD_I2C=y |
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CONFIG_CMD_MMC=y |
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CONFIG_CMD_USB=y |
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CONFIG_CMD_DHCP=y |
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CONFIG_CMD_MII=y |
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CONFIG_CMD_PING=y |
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CONFIG_CMD_EXT2=y |
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CONFIG_CMD_EXT4=y |
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CONFIG_CMD_EXT4_WRITE=y |
||||
CONFIG_CMD_FAT=y |
||||
CONFIG_CMD_FS_GENERIC=y |
||||
CONFIG_OF_CONTROL=y |
||||
CONFIG_ENV_IS_IN_MMC=y |
||||
CONFIG_REGMAP=y |
||||
CONFIG_SYSCON=y |
||||
CONFIG_CLK=y |
||||
CONFIG_CLK_RENESAS=y |
||||
CONFIG_DM_GPIO=y |
||||
CONFIG_RCAR_GPIO=y |
||||
CONFIG_DM_I2C=y |
||||
CONFIG_SYS_I2C_RCAR_IIC=y |
||||
CONFIG_DM_MMC=y |
||||
CONFIG_MMC_IO_VOLTAGE=y |
||||
CONFIG_MMC_UHS_SUPPORT=y |
||||
CONFIG_MMC_HS200_SUPPORT=y |
||||
CONFIG_RENESAS_SDHI=y |
||||
CONFIG_PHY_MICREL=y |
||||
CONFIG_PHY_MICREL_KSZ90X1=y |
||||
CONFIG_DM_ETH=y |
||||
CONFIG_RENESAS_RAVB=y |
||||
CONFIG_PINCTRL=y |
||||
CONFIG_PINCONF=y |
||||
CONFIG_PINCTRL_PFC=y |
||||
CONFIG_DM_REGULATOR=y |
||||
CONFIG_DM_REGULATOR_FIXED=y |
||||
CONFIG_DM_REGULATOR_GPIO=y |
||||
CONFIG_SCIF_CONSOLE=y |
||||
CONFIG_USB=y |
||||
CONFIG_DM_USB=y |
||||
CONFIG_USB_XHCI_HCD=y |
||||
CONFIG_USB_EHCI_HCD=y |
||||
CONFIG_USB_EHCI_GENERIC=y |
||||
CONFIG_USB_STORAGE=y |
||||
CONFIG_OF_LIBFDT_OVERLAY=y |
||||
CONFIG_SMBIOS_MANUFACTURER="" |
||||
@ -0,0 +1,302 @@ |
||||
// SPDX-License-Identifier: GPL-2.0+
|
||||
/*
|
||||
* Renesas R8A77990 CPG MSSR driver |
||||
* |
||||
* Copyright (C) 2017-2018 Marek Vasut <marek.vasut@gmail.com> |
||||
* |
||||
* Based on the following driver from Linux kernel: |
||||
* r8a7796 Clock Pulse Generator / Module Standby and Software Reset |
||||
* |
||||
* Copyright (C) 2016 Glider bvba |
||||
*/ |
||||
|
||||
#include <common.h> |
||||
#include <clk-uclass.h> |
||||
#include <dm.h> |
||||
|
||||
#include <dt-bindings/clock/r8a77990-cpg-mssr.h> |
||||
|
||||
#include "renesas-cpg-mssr.h" |
||||
#include "rcar-gen3-cpg.h" |
||||
|
||||
enum clk_ids { |
||||
/* Core Clock Outputs exported to DT */ |
||||
LAST_DT_CORE_CLK = R8A77990_CLK_CPEX, |
||||
|
||||
/* External Input Clocks */ |
||||
CLK_EXTAL, |
||||
|
||||
/* Internal Core Clocks */ |
||||
CLK_MAIN, |
||||
CLK_PLL0, |
||||
CLK_PLL1, |
||||
CLK_PLL3, |
||||
CLK_PLL0D4, |
||||
CLK_PLL0D6, |
||||
CLK_PLL0D8, |
||||
CLK_PLL0D20, |
||||
CLK_PLL0D24, |
||||
CLK_PLL1D2, |
||||
CLK_PE, |
||||
CLK_S0, |
||||
CLK_S1, |
||||
CLK_S2, |
||||
CLK_S3, |
||||
CLK_SDSRC, |
||||
|
||||
/* Module Clocks */ |
||||
MOD_CLK_BASE |
||||
}; |
||||
|
||||
static const struct cpg_core_clk r8a77990_core_clks[] = { |
||||
/* External Clock Inputs */ |
||||
DEF_INPUT("extal", CLK_EXTAL), |
||||
|
||||
/* Internal Core Clocks */ |
||||
DEF_BASE(".main", CLK_MAIN, CLK_TYPE_GEN3_MAIN, CLK_EXTAL), |
||||
DEF_BASE(".pll1", CLK_PLL1, CLK_TYPE_GEN3_PLL1, CLK_MAIN), |
||||
DEF_BASE(".pll3", CLK_PLL3, CLK_TYPE_GEN3_PLL3, CLK_MAIN), |
||||
|
||||
DEF_FIXED(".pll0", CLK_PLL0, CLK_MAIN, 1, 100), |
||||
DEF_FIXED(".pll0d4", CLK_PLL0D4, CLK_PLL0, 4, 1), |
||||
DEF_FIXED(".pll0d6", CLK_PLL0D6, CLK_PLL0, 6, 1), |
||||
DEF_FIXED(".pll0d8", CLK_PLL0D8, CLK_PLL0, 8, 1), |
||||
DEF_FIXED(".pll0d20", CLK_PLL0D20, CLK_PLL0, 20, 1), |
||||
DEF_FIXED(".pll0d24", CLK_PLL0D24, CLK_PLL0, 24, 1), |
||||
DEF_FIXED(".pll1d2", CLK_PLL1D2, CLK_PLL1, 2, 1), |
||||
DEF_FIXED(".pe", CLK_PE, CLK_PLL0D20, 1, 1), |
||||
DEF_FIXED(".s0", CLK_S0, CLK_PLL1, 2, 1), |
||||
DEF_FIXED(".s1", CLK_S1, CLK_PLL1, 3, 1), |
||||
DEF_FIXED(".s2", CLK_S2, CLK_PLL1, 4, 1), |
||||
DEF_FIXED(".s3", CLK_S3, CLK_PLL1, 6, 1), |
||||
DEF_FIXED(".sdsrc", CLK_SDSRC, CLK_PLL1, 2, 1), |
||||
|
||||
/* Core Clock Outputs */ |
||||
DEF_FIXED("za2", R8A77990_CLK_ZA2, CLK_PLL0D24, 1, 1), |
||||
DEF_FIXED("za8", R8A77990_CLK_ZA8, CLK_PLL0D8, 1, 1), |
||||
DEF_FIXED("ztr", R8A77990_CLK_ZTR, CLK_PLL1, 6, 1), |
||||
DEF_FIXED("zt", R8A77990_CLK_ZT, CLK_PLL1, 4, 1), |
||||
DEF_FIXED("zx", R8A77990_CLK_ZX, CLK_PLL1, 3, 1), |
||||
DEF_FIXED("s0d1", R8A77990_CLK_S0D1, CLK_S0, 1, 1), |
||||
DEF_FIXED("s0d3", R8A77990_CLK_S0D3, CLK_S0, 3, 1), |
||||
DEF_FIXED("s0d6", R8A77990_CLK_S0D6, CLK_S0, 6, 1), |
||||
DEF_FIXED("s0d12", R8A77990_CLK_S0D12, CLK_S0, 12, 1), |
||||
DEF_FIXED("s0d24", R8A77990_CLK_S0D24, CLK_S0, 24, 1), |
||||
DEF_FIXED("s1d1", R8A77990_CLK_S1D1, CLK_S1, 1, 1), |
||||
DEF_FIXED("s1d2", R8A77990_CLK_S1D2, CLK_S1, 2, 1), |
||||
DEF_FIXED("s1d4", R8A77990_CLK_S1D4, CLK_S1, 4, 1), |
||||
DEF_FIXED("s2d1", R8A77990_CLK_S2D1, CLK_S2, 1, 1), |
||||
DEF_FIXED("s2d2", R8A77990_CLK_S2D2, CLK_S2, 2, 1), |
||||
DEF_FIXED("s2d4", R8A77990_CLK_S2D4, CLK_S2, 4, 1), |
||||
DEF_FIXED("s3d1", R8A77990_CLK_S3D1, CLK_S3, 1, 1), |
||||
DEF_FIXED("s3d2", R8A77990_CLK_S3D2, CLK_S3, 2, 1), |
||||
DEF_FIXED("s3d4", R8A77990_CLK_S3D4, CLK_S3, 4, 1), |
||||
|
||||
DEF_GEN3_SD("sd0", R8A77990_CLK_SD0, CLK_SDSRC, 0x0074), |
||||
DEF_GEN3_SD("sd1", R8A77990_CLK_SD1, CLK_SDSRC, 0x0078), |
||||
DEF_GEN3_SD("sd3", R8A77990_CLK_SD3, CLK_SDSRC, 0x026c), |
||||
|
||||
DEF_FIXED("cl", R8A77990_CLK_CL, CLK_PLL1, 48, 1), |
||||
DEF_FIXED("cp", R8A77990_CLK_CP, CLK_EXTAL, 2, 1), |
||||
DEF_FIXED("cpex", R8A77990_CLK_CPEX, CLK_EXTAL, 4, 1), |
||||
DEF_FIXED("osc", R8A77990_CLK_OSC, CLK_EXTAL, 384, 1), |
||||
DEF_FIXED("r", R8A77990_CLK_R, CLK_EXTAL, 1536, 1), |
||||
|
||||
DEF_GEN3_PE("s0d6c", R8A77990_CLK_S0D6C, CLK_S0, 6, CLK_PE, 6), |
||||
DEF_GEN3_PE("s3d1c", R8A77990_CLK_S3D1C, CLK_S3, 1, CLK_PE, 1), |
||||
DEF_GEN3_PE("s3d2c", R8A77990_CLK_S3D2C, CLK_S3, 2, CLK_PE, 2), |
||||
DEF_GEN3_PE("s3d4c", R8A77990_CLK_S3D4C, CLK_S3, 4, CLK_PE, 4), |
||||
|
||||
DEF_DIV6P1("canfd", R8A77990_CLK_CANFD, CLK_PLL0D6, 0x244), |
||||
DEF_DIV6P1("csi0", R8A77990_CLK_CSI0, CLK_PLL1D2, 0x00c), |
||||
DEF_DIV6P1("mso", R8A77990_CLK_MSO, CLK_PLL1D2, 0x014), |
||||
}; |
||||
|
||||
static const struct mssr_mod_clk r8a77990_mod_clks[] = { |
||||
DEF_MOD("scif5", 202, R8A77990_CLK_S3D4C), |
||||
DEF_MOD("scif4", 203, R8A77990_CLK_S3D4C), |
||||
DEF_MOD("scif3", 204, R8A77990_CLK_S3D4C), |
||||
DEF_MOD("scif1", 206, R8A77990_CLK_S3D4C), |
||||
DEF_MOD("scif0", 207, R8A77990_CLK_S3D4C), |
||||
DEF_MOD("msiof3", 208, R8A77990_CLK_MSO), |
||||
DEF_MOD("msiof2", 209, R8A77990_CLK_MSO), |
||||
DEF_MOD("msiof1", 210, R8A77990_CLK_MSO), |
||||
DEF_MOD("msiof0", 211, R8A77990_CLK_MSO), |
||||
DEF_MOD("sys-dmac2", 217, R8A77990_CLK_S3D1), |
||||
DEF_MOD("sys-dmac1", 218, R8A77990_CLK_S3D1), |
||||
DEF_MOD("sys-dmac0", 219, R8A77990_CLK_S3D1), |
||||
|
||||
DEF_MOD("cmt3", 300, R8A77990_CLK_R), |
||||
DEF_MOD("cmt2", 301, R8A77990_CLK_R), |
||||
DEF_MOD("cmt1", 302, R8A77990_CLK_R), |
||||
DEF_MOD("cmt0", 303, R8A77990_CLK_R), |
||||
DEF_MOD("scif2", 310, R8A77990_CLK_S3D4C), |
||||
DEF_MOD("sdif3", 311, R8A77990_CLK_SD3), |
||||
DEF_MOD("sdif1", 313, R8A77990_CLK_SD1), |
||||
DEF_MOD("sdif0", 314, R8A77990_CLK_SD0), |
||||
DEF_MOD("pcie0", 319, R8A77990_CLK_S3D1), |
||||
DEF_MOD("usb3-if0", 328, R8A77990_CLK_S3D1), |
||||
DEF_MOD("usb-dmac0", 330, R8A77990_CLK_S3D1), |
||||
DEF_MOD("usb-dmac1", 331, R8A77990_CLK_S3D1), |
||||
|
||||
DEF_MOD("rwdt", 402, R8A77990_CLK_R), |
||||
DEF_MOD("intc-ex", 407, R8A77990_CLK_CP), |
||||
DEF_MOD("intc-ap", 408, R8A77990_CLK_S0D3), |
||||
|
||||
DEF_MOD("audmac0", 502, R8A77990_CLK_S3D4), |
||||
DEF_MOD("drif7", 508, R8A77990_CLK_S3D2), |
||||
DEF_MOD("drif6", 509, R8A77990_CLK_S3D2), |
||||
DEF_MOD("drif5", 510, R8A77990_CLK_S3D2), |
||||
DEF_MOD("drif4", 511, R8A77990_CLK_S3D2), |
||||
DEF_MOD("drif3", 512, R8A77990_CLK_S3D2), |
||||
DEF_MOD("drif2", 513, R8A77990_CLK_S3D2), |
||||
DEF_MOD("drif1", 514, R8A77990_CLK_S3D2), |
||||
DEF_MOD("drif0", 515, R8A77990_CLK_S3D2), |
||||
DEF_MOD("hscif4", 516, R8A77990_CLK_S3D1C), |
||||
DEF_MOD("hscif3", 517, R8A77990_CLK_S3D1C), |
||||
DEF_MOD("hscif2", 518, R8A77990_CLK_S3D1C), |
||||
DEF_MOD("hscif1", 519, R8A77990_CLK_S3D1C), |
||||
DEF_MOD("hscif0", 520, R8A77990_CLK_S3D1C), |
||||
DEF_MOD("thermal", 522, R8A77990_CLK_CP), |
||||
DEF_MOD("pwm", 523, R8A77990_CLK_S3D4C), |
||||
|
||||
DEF_MOD("fcpvd1", 602, R8A77990_CLK_S1D2), |
||||
DEF_MOD("fcpvd0", 603, R8A77990_CLK_S1D2), |
||||
DEF_MOD("fcpvb0", 607, R8A77990_CLK_S0D1), |
||||
DEF_MOD("fcpvi0", 611, R8A77990_CLK_S0D1), |
||||
DEF_MOD("fcpf0", 615, R8A77990_CLK_S0D1), |
||||
DEF_MOD("fcpcs", 619, R8A77990_CLK_S0D1), |
||||
DEF_MOD("vspd1", 622, R8A77990_CLK_S1D2), |
||||
DEF_MOD("vspd0", 623, R8A77990_CLK_S1D2), |
||||
DEF_MOD("vspb", 626, R8A77990_CLK_S0D1), |
||||
DEF_MOD("vspi0", 631, R8A77990_CLK_S0D1), |
||||
|
||||
DEF_MOD("ehci0", 703, R8A77990_CLK_S3D4), |
||||
DEF_MOD("hsusb", 704, R8A77990_CLK_S3D4), |
||||
DEF_MOD("csi40", 716, R8A77990_CLK_CSI0), |
||||
DEF_MOD("du1", 723, R8A77990_CLK_S2D1), |
||||
DEF_MOD("du0", 724, R8A77990_CLK_S2D1), |
||||
DEF_MOD("lvds", 727, R8A77990_CLK_S2D1), |
||||
|
||||
DEF_MOD("vin7", 804, R8A77990_CLK_S1D2), |
||||
DEF_MOD("vin6", 805, R8A77990_CLK_S1D2), |
||||
DEF_MOD("vin5", 806, R8A77990_CLK_S1D2), |
||||
DEF_MOD("vin4", 807, R8A77990_CLK_S1D2), |
||||
DEF_MOD("etheravb", 812, R8A77990_CLK_S3D2), |
||||
|
||||
DEF_MOD("gpio6", 906, R8A77990_CLK_S3D4), |
||||
DEF_MOD("gpio5", 907, R8A77990_CLK_S3D4), |
||||
DEF_MOD("gpio4", 908, R8A77990_CLK_S3D4), |
||||
DEF_MOD("gpio3", 909, R8A77990_CLK_S3D4), |
||||
DEF_MOD("gpio2", 910, R8A77990_CLK_S3D4), |
||||
DEF_MOD("gpio1", 911, R8A77990_CLK_S3D4), |
||||
DEF_MOD("gpio0", 912, R8A77990_CLK_S3D4), |
||||
DEF_MOD("can-fd", 914, R8A77990_CLK_S3D2), |
||||
DEF_MOD("can-if1", 915, R8A77990_CLK_S3D4), |
||||
DEF_MOD("can-if0", 916, R8A77990_CLK_S3D4), |
||||
DEF_MOD("i2c6", 918, R8A77990_CLK_S3D2), |
||||
DEF_MOD("i2c5", 919, R8A77990_CLK_S3D2), |
||||
DEF_MOD("i2c-dvfs", 926, R8A77990_CLK_CP), |
||||
DEF_MOD("i2c4", 927, R8A77990_CLK_S3D2), |
||||
DEF_MOD("i2c3", 928, R8A77990_CLK_S3D2), |
||||
DEF_MOD("i2c2", 929, R8A77990_CLK_S3D2), |
||||
DEF_MOD("i2c1", 930, R8A77990_CLK_S3D2), |
||||
DEF_MOD("i2c0", 931, R8A77990_CLK_S3D2), |
||||
|
||||
DEF_MOD("ssi-all", 1005, R8A77990_CLK_S3D4), |
||||
DEF_MOD("ssi9", 1006, MOD_CLK_ID(1005)), |
||||
DEF_MOD("ssi8", 1007, MOD_CLK_ID(1005)), |
||||
DEF_MOD("ssi7", 1008, MOD_CLK_ID(1005)), |
||||
DEF_MOD("ssi6", 1009, MOD_CLK_ID(1005)), |
||||
DEF_MOD("ssi5", 1010, MOD_CLK_ID(1005)), |
||||
DEF_MOD("ssi4", 1011, MOD_CLK_ID(1005)), |
||||
DEF_MOD("ssi3", 1012, MOD_CLK_ID(1005)), |
||||
DEF_MOD("ssi2", 1013, MOD_CLK_ID(1005)), |
||||
DEF_MOD("ssi1", 1014, MOD_CLK_ID(1005)), |
||||
DEF_MOD("ssi0", 1015, MOD_CLK_ID(1005)), |
||||
DEF_MOD("scu-all", 1017, R8A77990_CLK_S3D4), |
||||
DEF_MOD("scu-dvc1", 1018, MOD_CLK_ID(1017)), |
||||
DEF_MOD("scu-dvc0", 1019, MOD_CLK_ID(1017)), |
||||
DEF_MOD("scu-ctu1-mix1", 1020, MOD_CLK_ID(1017)), |
||||
DEF_MOD("scu-ctu0-mix0", 1021, MOD_CLK_ID(1017)), |
||||
DEF_MOD("scu-src9", 1022, MOD_CLK_ID(1017)), |
||||
DEF_MOD("scu-src8", 1023, MOD_CLK_ID(1017)), |
||||
DEF_MOD("scu-src7", 1024, MOD_CLK_ID(1017)), |
||||
DEF_MOD("scu-src6", 1025, MOD_CLK_ID(1017)), |
||||
DEF_MOD("scu-src5", 1026, MOD_CLK_ID(1017)), |
||||
DEF_MOD("scu-src4", 1027, MOD_CLK_ID(1017)), |
||||
DEF_MOD("scu-src3", 1028, MOD_CLK_ID(1017)), |
||||
DEF_MOD("scu-src2", 1029, MOD_CLK_ID(1017)), |
||||
DEF_MOD("scu-src1", 1030, MOD_CLK_ID(1017)), |
||||
DEF_MOD("scu-src0", 1031, MOD_CLK_ID(1017)), |
||||
}; |
||||
|
||||
/*
|
||||
* CPG Clock Data |
||||
*/ |
||||
|
||||
/*
|
||||
* MD19 EXTAL (MHz) PLL0 PLL1 PLL3 |
||||
*-------------------------------------------------------------------- |
||||
* 0 48 x 1 x100/4 x100/3 x100/3 |
||||
* 1 48 x 1 x100/4 x100/3 x58/3 |
||||
*/ |
||||
#define CPG_PLL_CONFIG_INDEX(md) (((md) & BIT(19)) >> 19) |
||||
|
||||
static const struct rcar_gen3_cpg_pll_config cpg_pll_configs[2] = { |
||||
/* EXTAL div PLL1 mult/div PLL3 mult/div */ |
||||
{ 1, 100, 3, 100, 3, }, |
||||
{ 1, 100, 3, 58, 3, }, |
||||
}; |
||||
|
||||
static const struct mstp_stop_table r8a77990_mstp_table[] = { |
||||
{ 0x00200000, 0x0, 0x00200000, 0 }, |
||||
{ 0xFFFFFFFF, 0x0, 0xFFFFFFFF, 0 }, |
||||
{ 0x340E2FDC, 0x2040, 0x340E2FDC, 0 }, |
||||
{ 0xFFFFFFDF, 0x400, 0xFFFFFFDF, 0 }, |
||||
{ 0x80000184, 0x180, 0x80000184, 0 }, |
||||
{ 0xC3FFFFFF, 0x0, 0xC3FFFFFF, 0 }, |
||||
{ 0xFFFFFFFF, 0x0, 0xFFFFFFFF, 0 }, |
||||
{ 0xFFFFFFFF, 0x0, 0xFFFFFFFF, 0 }, |
||||
{ 0x01F1FFF7, 0x0, 0x01F1FFF7, 0 }, |
||||
{ 0xFFFFFFFE, 0x0, 0xFFFFFFFE, 0 }, |
||||
{ 0xFFFEFFE0, 0x0, 0xFFFEFFE0, 0 }, |
||||
{ 0x000000B7, 0x0, 0x000000B7, 0 }, |
||||
}; |
||||
|
||||
static const void *r8a77990_get_pll_config(const u32 cpg_mode) |
||||
{ |
||||
return &cpg_pll_configs[CPG_PLL_CONFIG_INDEX(cpg_mode)]; |
||||
} |
||||
|
||||
static const struct cpg_mssr_info r8a77990_cpg_mssr_info = { |
||||
.core_clk = r8a77990_core_clks, |
||||
.core_clk_size = ARRAY_SIZE(r8a77990_core_clks), |
||||
.mod_clk = r8a77990_mod_clks, |
||||
.mod_clk_size = ARRAY_SIZE(r8a77990_mod_clks), |
||||
.mstp_table = r8a77990_mstp_table, |
||||
.mstp_table_size = ARRAY_SIZE(r8a77990_mstp_table), |
||||
.reset_node = "renesas,r8a77990-rst", |
||||
.mod_clk_base = MOD_CLK_BASE, |
||||
.clk_extal_id = CLK_EXTAL, |
||||
.clk_extalr_id = ~0, |
||||
.get_pll_config = r8a77990_get_pll_config, |
||||
}; |
||||
|
||||
static const struct udevice_id r8a77990_clk_ids[] = { |
||||
{ |
||||
.compatible = "renesas,r8a77990-cpg-mssr", |
||||
.data = (ulong)&r8a77990_cpg_mssr_info |
||||
}, |
||||
{ } |
||||
}; |
||||
|
||||
U_BOOT_DRIVER(clk_r8a77990) = { |
||||
.name = "clk_r8a77990", |
||||
.id = UCLASS_CLK, |
||||
.of_match = r8a77990_clk_ids, |
||||
.priv_auto_alloc_size = sizeof(struct gen3_clk_priv), |
||||
.ops = &gen3_clk_ops, |
||||
.probe = gen3_clk_probe, |
||||
.remove = gen3_clk_remove, |
||||
}; |
||||
File diff suppressed because it is too large
Load Diff
@ -0,0 +1,33 @@ |
||||
/* SPDX-License-Identifier: GPL-2.0+ */ |
||||
/*
|
||||
* include/configs/ebisu.h |
||||
* This file is Ebisu board configuration. |
||||
* |
||||
* Copyright (C) 2018 Renesas Electronics Corporation |
||||
*/ |
||||
|
||||
#ifndef __EBISU_H |
||||
#define __EBISU_H |
||||
|
||||
#undef DEBUG |
||||
|
||||
#include "rcar-gen3-common.h" |
||||
|
||||
/* Ethernet RAVB */ |
||||
#define CONFIG_NET_MULTI |
||||
#define CONFIG_BITBANGMII |
||||
#define CONFIG_BITBANGMII_MULTI |
||||
|
||||
/* Board Clock */ |
||||
/* XTAL_CLK : 33.33MHz */ |
||||
#define CONFIG_SYS_CLK_FREQ 48000000u |
||||
|
||||
/* Generic Timer Definitions (use in assembler source) */ |
||||
#define COUNTER_FREQUENCY 0xFE502A /* 16.66MHz from CPclk */ |
||||
|
||||
/* Environment in eMMC, at the end of 2nd "boot sector" */ |
||||
#define CONFIG_ENV_OFFSET (-CONFIG_ENV_SIZE) |
||||
#define CONFIG_SYS_MMC_ENV_DEV 2 |
||||
#define CONFIG_SYS_MMC_ENV_PART 2 |
||||
|
||||
#endif /* __EBISU_H */ |
||||
@ -0,0 +1,63 @@ |
||||
/* SPDX-License-Identifier: GPL-2.0 */ |
||||
/*
|
||||
* Copyright (C) 2018 Renesas Electronics Corp. |
||||
*/ |
||||
#ifndef __DT_BINDINGS_CLOCK_R8A77990_CPG_MSSR_H__ |
||||
#define __DT_BINDINGS_CLOCK_R8A77990_CPG_MSSR_H__ |
||||
|
||||
#include <dt-bindings/clock/renesas-cpg-mssr.h> |
||||
|
||||
/* r8a77990 CPG Core Clocks */ |
||||
#define R8A77990_CLK_Z2 0 |
||||
#define R8A77990_CLK_ZR 1 |
||||
#define R8A77990_CLK_ZG 2 |
||||
#define R8A77990_CLK_ZTR 3 |
||||
#define R8A77990_CLK_ZT 4 |
||||
#define R8A77990_CLK_ZX 5 |
||||
#define R8A77990_CLK_S0D1 6 |
||||
#define R8A77990_CLK_S0D3 7 |
||||
#define R8A77990_CLK_S0D6 8 |
||||
#define R8A77990_CLK_S0D12 9 |
||||
#define R8A77990_CLK_S0D24 10 |
||||
#define R8A77990_CLK_S1D1 11 |
||||
#define R8A77990_CLK_S1D2 12 |
||||
#define R8A77990_CLK_S1D4 13 |
||||
#define R8A77990_CLK_S2D1 14 |
||||
#define R8A77990_CLK_S2D2 15 |
||||
#define R8A77990_CLK_S2D4 16 |
||||
#define R8A77990_CLK_S3D1 17 |
||||
#define R8A77990_CLK_S3D2 18 |
||||
#define R8A77990_CLK_S3D4 19 |
||||
#define R8A77990_CLK_S0D6C 20 |
||||
#define R8A77990_CLK_S3D1C 21 |
||||
#define R8A77990_CLK_S3D2C 22 |
||||
#define R8A77990_CLK_S3D4C 23 |
||||
#define R8A77990_CLK_LB 24 |
||||
#define R8A77990_CLK_CL 25 |
||||
#define R8A77990_CLK_ZB3 26 |
||||
#define R8A77990_CLK_ZB3D2 27 |
||||
#define R8A77990_CLK_CR 28 |
||||
#define R8A77990_CLK_CRD2 29 |
||||
#define R8A77990_CLK_SD0H 30 |
||||
#define R8A77990_CLK_SD0 31 |
||||
#define R8A77990_CLK_SD1H 32 |
||||
#define R8A77990_CLK_SD1 33 |
||||
#define R8A77990_CLK_SD3H 34 |
||||
#define R8A77990_CLK_SD3 35 |
||||
#define R8A77990_CLK_RPC 36 |
||||
#define R8A77990_CLK_RPCD2 37 |
||||
#define R8A77990_CLK_ZA2 38 |
||||
#define R8A77990_CLK_ZA8 39 |
||||
#define R8A77990_CLK_Z2D 40 |
||||
#define R8A77990_CLK_CANFD 41 |
||||
#define R8A77990_CLK_MSO 42 |
||||
#define R8A77990_CLK_R 43 |
||||
#define R8A77990_CLK_OSC 44 |
||||
#define R8A77990_CLK_LV0 45 |
||||
#define R8A77990_CLK_LV1 46 |
||||
#define R8A77990_CLK_CSI0 47 |
||||
#define R8A77990_CLK_POST3 48 |
||||
#define R8A77990_CLK_CP 49 |
||||
#define R8A77990_CLK_CPEX 50 |
||||
|
||||
#endif /* __DT_BINDINGS_CLOCK_R8A77990_CPG_MSSR_H__ */ |
||||
Loading…
Reference in new issue