From 041cdb5f3d0fe778546bcf5b8b69e6b774db1d9e Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Heiko=20St=C3=BCbner?= Date: Sat, 16 Jul 2016 00:17:15 +0200 Subject: [PATCH] cosmetic: rockchip: sort socs according to numbers MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Having some sort of ordering proofed helpful in a lot of other places already. So for a larger number of rockchip socs it might be helpful as well instead of an ever increasing unsorted list. Signed-off-by: Heiko Stuebner Reviewed-by: Andreas Färber Acked-by: Simon Glass --- arch/arm/mach-rockchip/Kconfig | 20 ++++++++++---------- arch/arm/mach-rockchip/Makefile | 4 ++-- drivers/pinctrl/Kconfig | 16 ++++++++-------- drivers/pinctrl/rockchip/Makefile | 2 +- 4 files changed, 21 insertions(+), 21 deletions(-) diff --git a/arch/arm/mach-rockchip/Kconfig b/arch/arm/mach-rockchip/Kconfig index 86b77f8..a3faafe 100644 --- a/arch/arm/mach-rockchip/Kconfig +++ b/arch/arm/mach-rockchip/Kconfig @@ -1,5 +1,14 @@ if ARCH_ROCKCHIP +config ROCKCHIP_RK3036 + bool "Support Rockchip RK3036" + select CPU_V7 + help + The Rockchip RK3036 is a ARM-based SoC with a dual-core Cortex-A7 + including NEON and GPU, Mali-400 graphics, several DDR3 options + and video codec support. Peripherals include Gigabit Ethernet, + USB2 host and OTG, SDIO, I2S, UART, SPI, I2C and PWMs. + config ROCKCHIP_RK3288 bool "Support Rockchip RK3288" select CPU_V7 @@ -10,15 +19,6 @@ config ROCKCHIP_RK3288 and video codec support. Peripherals include Gigabit Ethernet, USB2 host and OTG, SDIO, I2S, UART,s, SPI, I2C and PWMs. -config ROCKCHIP_RK3036 - bool "Support Rockchip RK3036" - select CPU_V7 - help - The Rockchip RK3036 is a ARM-based SoC with a dual-core Cortex-A7 - including NEON and GPU, Mali-400 graphics, several DDR3 options - and video codec support. Peripherals include Gigabit Ethernet, - USB2 host and OTG, SDIO, I2S, UART, SPI, I2C and PWMs. - config ROCKCHIP_SPL_BACK_TO_BROM bool "SPL returns to bootrom" default y if ROCKCHIP_RK3036 @@ -27,6 +27,6 @@ config ROCKCHIP_SPL_BACK_TO_BROM SPL will return to the boot rom, which will then load the U-Boot binary to keep going on. -source "arch/arm/mach-rockchip/rk3288/Kconfig" source "arch/arm/mach-rockchip/rk3036/Kconfig" +source "arch/arm/mach-rockchip/rk3288/Kconfig" endif diff --git a/arch/arm/mach-rockchip/Makefile b/arch/arm/mach-rockchip/Makefile index 6763af4..722b582 100644 --- a/arch/arm/mach-rockchip/Makefile +++ b/arch/arm/mach-rockchip/Makefile @@ -5,8 +5,8 @@ # ifdef CONFIG_SPL_BUILD -obj-$(CONFIG_ROCKCHIP_RK3288) += rk3288-board-spl.o obj-$(CONFIG_ROCKCHIP_RK3036) += rk3036-board-spl.o +obj-$(CONFIG_ROCKCHIP_RK3288) += rk3288-board-spl.o obj-$(CONFIG_ROCKCHIP_SPL_BACK_TO_BROM) += save_boot_param.o else obj-$(CONFIG_ROCKCHIP_RK3288) += board.o @@ -14,5 +14,5 @@ endif ifndef CONFIG_ARM64 obj-y += rk_timer.o endif -obj-$(CONFIG_ROCKCHIP_RK3288) += rk3288/ obj-$(CONFIG_ROCKCHIP_RK3036) += rk3036/ +obj-$(CONFIG_ROCKCHIP_RK3288) += rk3288/ diff --git a/drivers/pinctrl/Kconfig b/drivers/pinctrl/Kconfig index 951a922..2972dba 100644 --- a/drivers/pinctrl/Kconfig +++ b/drivers/pinctrl/Kconfig @@ -123,21 +123,21 @@ config QCA953X_PINCTRL both the GPIO definitions and pin control functions for each available multiplex function. -config ROCKCHIP_RK3288_PINCTRL - bool "Rockchip pin control driver" +config ROCKCHIP_RK3036_PINCTRL + bool "Rockchip rk3036 pin control driver" depends on DM help - Support pin multiplexing control on Rockchip rk3288 SoCs. The driver - is controlled by a device tree node which contains both the GPIO + Support pin multiplexing control on Rockchip rk3036 SoCs. The driver is + controlled by a device tree node which contains both the GPIO definitions and pin control functions for each available multiplex function. -config ROCKCHIP_RK3036_PINCTRL - bool "Rockchip rk3036 pin control driver" +config ROCKCHIP_RK3288_PINCTRL + bool "Rockchip pin control driver" depends on DM help - Support pin multiplexing control on Rockchip rk3036 SoCs. The driver is - controlled by a device tree node which contains both the GPIO + Support pin multiplexing control on Rockchip rk3288 SoCs. The driver + is controlled by a device tree node which contains both the GPIO definitions and pin control functions for each available multiplex function. diff --git a/drivers/pinctrl/rockchip/Makefile b/drivers/pinctrl/rockchip/Makefile index 0b2e95e..64e9587 100644 --- a/drivers/pinctrl/rockchip/Makefile +++ b/drivers/pinctrl/rockchip/Makefile @@ -5,5 +5,5 @@ # SPDX-License-Identifier: GPL-2.0+ # -obj-$(CONFIG_ROCKCHIP_RK3288_PINCTRL) += pinctrl_rk3288.o obj-$(CONFIG_ROCKCHIP_RK3036_PINCTRL) += pinctrl_rk3036.o +obj-$(CONFIG_ROCKCHIP_RK3288_PINCTRL) += pinctrl_rk3288.o