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ARM: uniphier: remove DRAM base address from board parameters

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The base address of each DRAM channel can be calculated from other
parameters, so does not need hard-coding.  What we need is the size
of each DRAM channel and DRAM_SPARSE flag to decide the start address
of DRAM channel 1.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
master
Masahiro Yamada 8 years ago
parent cf3175bcd8
commit 04cd4e7215
6 changed files with 36 additions and 57 deletions
Show all changes Ignore whitespace when comparing lines Ignore changes in amount of whitespace Ignore changes in whitespace at EOL
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  1. 2
      arch/arm/mach-uniphier/bcu/bcu-ld4.c
  2. 2
      arch/arm/mach-uniphier/bcu/bcu-sld3.c
  3. 30
      arch/arm/mach-uniphier/boards.c
  4. 53
      arch/arm/mach-uniphier/dram_init.c
  5. 4
      arch/arm/mach-uniphier/init.h
  6. 2
      arch/arm/mach-uniphier/memconf.c

2
arch/arm/mach-uniphier/bcu/bcu-ld4.c
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@ -24,7 +24,7 @@ void uniphier_ld4_bcu_init(const struct uniphier_board_data *bd)
writel(0x11111111, BCSCR5); /* 0xe0000000-0Xffffffff: IPPC/IPPD-bus */
/* Specify DDR channel */
shift = (bd->dram_ch[1].base - bd->dram_ch[0].base) / 0x04000000 * 4;
shift = bd->dram_ch[0].size / 0x04000000 * 4;
writel(ch(shift), BCIPPCCHR2); /* 0x80000000-0x9fffffff */
shift -= 32;

2
arch/arm/mach-uniphier/bcu/bcu-sld3.c
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@ -28,7 +28,7 @@ void uniphier_sld3_bcu_init(const struct uniphier_board_data *bd)
writel(0x24440000, BCSCR5);
/* Specify DDR channel */
shift = (bd->dram_ch[1].base - bd->dram_ch[0].base) / 0x04000000 * 4;
shift = bd->dram_ch[0].size / 0x04000000 * 4;
writel(ch(shift), BCIPPCCHR2); /* 0x80000000-0x9fffffff */
shift -= 32;

30
arch/arm/mach-uniphier/boards.c
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@ -18,20 +18,18 @@ static const struct uniphier_board_data uniphier_sld3_data = {
.dram_freq = 1600,
.dram_nr_ch = 3,
.dram_ch[0] = {
.base = 0x80000000,
.size = 0x20000000,
.width = 32,
},
.dram_ch[1] = {
.base = 0xc0000000,
.size = 0x20000000,
.width = 16,
},
.dram_ch[2] = {
.base = 0xc0000000,
.size = 0x10000000,
.width = 16,
},
.flags = UNIPHIER_BD_DRAM_SPARSE,
};
#endif
@ -40,12 +38,10 @@ static const struct uniphier_board_data uniphier_ld4_data = {
.dram_freq = 1600,
.dram_nr_ch = 2,
.dram_ch[0] = {
.base = 0x80000000,
.size = 0x10000000,
.width = 16,
},
.dram_ch[1] = {
.base = 0x90000000,
.size = 0x10000000,
.width = 16,
},
@ -59,12 +55,10 @@ static const struct uniphier_board_data uniphier_pro4_data = {
.dram_freq = 1600,
.dram_nr_ch = 2,
.dram_ch[0] = {
.base = 0x80000000,
.size = 0x20000000,
.width = 32,
},
.dram_ch[1] = {
.base = 0xa0000000,
.size = 0x20000000,
.width = 32,
},
@ -75,12 +69,10 @@ static const struct uniphier_board_data uniphier_pro4_2g_data = {
.dram_freq = 1600,
.dram_nr_ch = 2,
.dram_ch[0] = {
.base = 0x80000000,
.size = 0x40000000,
.width = 32,
},
.dram_ch[1] = {
.base = 0xc0000000,
.size = 0x40000000,
.width = 32,
},
@ -92,12 +84,10 @@ static const struct uniphier_board_data uniphier_sld8_data = {
.dram_freq = 1333,
.dram_nr_ch = 2,
.dram_ch[0] = {
.base = 0x80000000,
.size = 0x10000000,
.width = 16,
},
.dram_ch[1] = {
.base = 0x90000000,
.size = 0x10000000,
.width = 16,
},
@ -110,12 +100,10 @@ static const struct uniphier_board_data uniphier_pro5_data = {
.dram_freq = 1866,
.dram_nr_ch = 2,
.dram_ch[0] = {
.base = 0x80000000,
.size = 0x20000000,
.width = 32,
},
.dram_ch[1] = {
.base = 0xa0000000,
.size = 0x20000000,
.width = 32,
},
@ -127,17 +115,14 @@ static const struct uniphier_board_data uniphier_pxs2_data = {
.dram_freq = 2133,
.dram_nr_ch = 3,
.dram_ch[0] = {
.base = 0x80000000,
.size = 0x40000000,
.width = 32,
},
.dram_ch[1] = {
.base = 0xc0000000,
.size = 0x20000000,
.width = 32,
},
.dram_ch[2] = {
.base = 0xe0000000,
.size = 0x20000000,
.width = 16,
},
@ -149,17 +134,14 @@ static const struct uniphier_board_data uniphier_ld6b_data = {
.dram_freq = 1866,
.dram_nr_ch = 3,
.dram_ch[0] = {
.base = 0x80000000,
.size = 0x40000000,
.width = 32,
},
.dram_ch[1] = {
.base = 0xc0000000,
.size = 0x20000000,
.width = 32,
},
.dram_ch[2] = {
.base = 0xe0000000,
.size = 0x20000000,
.width = 16,
},
@ -171,12 +153,10 @@ static const struct uniphier_board_data uniphier_ld11_data = {
.dram_freq = 1600,
.dram_nr_ch = 2,
.dram_ch[0] = {
.base = 0x80000000,
.size = 0x20000000,
.width = 16,
},
.dram_ch[1] = {
.base = 0xa0000000,
.size = 0x20000000,
.width = 16,
},
@ -188,17 +168,14 @@ static const struct uniphier_board_data uniphier_ld20_ref_data = {
.dram_freq = 1866,
.dram_nr_ch = 3,
.dram_ch[0] = {
.base = 0x80000000,
.size = 0x40000000,
.width = 32,
},
.dram_ch[1] = {
.base = 0xc0000000,
.size = 0x40000000,
.width = 32,
},
.dram_ch[2] = {
.base = 0x100000000UL,
.size = 0x40000000,
.width = 32,
},
@ -209,17 +186,14 @@ static const struct uniphier_board_data uniphier_ld20_data = {
.dram_freq = 1866,
.dram_nr_ch = 3,
.dram_ch[0] = {
.base = 0x80000000,
.size = 0x40000000,
.width = 32,
},
.dram_ch[1] = {
.base = 0xc0000000,
.size = 0x40000000,
.width = 32,
},
.dram_ch[2] = {
.base = 0x100000000UL,
.size = 0x40000000,
.width = 32,
},
@ -230,12 +204,10 @@ static const struct uniphier_board_data uniphier_ld21_data = {
.dram_freq = 1866,
.dram_nr_ch = 2,
.dram_ch[0] = {
.base = 0x80000000,
.size = 0x20000000,
.width = 32,
},
.dram_ch[1] = {
.base = 0xc0000000,
.size = 0x40000000,
.width = 32,
},

53
arch/arm/mach-uniphier/dram_init.c
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@ -11,10 +11,12 @@
#include <linux/errno.h>
#include <linux/sizes.h>
#include "init.h"
#include "sg-regs.h"
#include "soc-info.h"
#define pr_warn(fmt, args...) printf(fmt, ##args)
#define pr_err(fmt, args...) printf(fmt, ##args)
DECLARE_GLOBAL_DATA_PTR;
struct uniphier_memif_data {
@ -76,7 +78,12 @@ static const struct uniphier_memif_data uniphier_memif_data[] = {
};
UNIPHIER_DEFINE_SOCDATA_FUNC(uniphier_get_memif_data, uniphier_memif_data)
static int uniphier_memconf_decode(struct uniphier_dram_ch *dram_ch)
struct uniphier_dram_map {
unsigned long base;
unsigned long size;
};
static int uniphier_memconf_decode(struct uniphier_dram_map *dram_map)
{
const struct uniphier_memif_data *data;
unsigned long size;
@ -91,7 +98,7 @@ static int uniphier_memconf_decode(struct uniphier_dram_ch *dram_ch)
val = readl(SG_MEMCONF);
/* set up ch0 */
dram_ch[0].base = CONFIG_SYS_SDRAM_BASE;
dram_map[0].base = CONFIG_SYS_SDRAM_BASE;
switch (val & SG_MEMCONF_CH0_SZ_MASK) {
case SG_MEMCONF_CH0_SZ_64M:
@ -117,20 +124,20 @@ static int uniphier_memconf_decode(struct uniphier_dram_ch *dram_ch)
if ((val & SG_MEMCONF_CH0_NUM_MASK) == SG_MEMCONF_CH0_NUM_2)
size *= 2;
dram_ch[0].size = size;
dram_map[0].size = size;
/* set up ch1 */
dram_ch[1].base = dram_ch[0].base + size;
dram_map[1].base = dram_map[0].base + size;
if (val & SG_MEMCONF_SPARSEMEM) {
if (dram_ch[1].base > data->sparse_ch1_base) {
if (dram_map[1].base > data->sparse_ch1_base) {
pr_warn("Sparse mem is enabled, but ch0 and ch1 overlap\n");
pr_warn("Only ch0 is available\n");
dram_ch[1].base = 0;
dram_map[1].base = 0;
return 0;
}
dram_ch[1].base = data->sparse_ch1_base;
dram_map[1].base = data->sparse_ch1_base;
}
switch (val & SG_MEMCONF_CH1_SZ_MASK) {
@ -157,13 +164,13 @@ static int uniphier_memconf_decode(struct uniphier_dram_ch *dram_ch)
if ((val & SG_MEMCONF_CH1_NUM_MASK) == SG_MEMCONF_CH1_NUM_2)
size *= 2;
dram_ch[1].size = size;
dram_map[1].size = size;
if (!data->have_ch2 || val & SG_MEMCONF_CH2_DISABLE)
return 0;
/* set up ch2 */
dram_ch[2].base = dram_ch[1].base + size;
dram_map[2].base = dram_map[1].base + size;
switch (val & SG_MEMCONF_CH2_SZ_MASK) {
case SG_MEMCONF_CH2_SZ_64M:
@ -189,25 +196,25 @@ static int uniphier_memconf_decode(struct uniphier_dram_ch *dram_ch)
if ((val & SG_MEMCONF_CH2_NUM_MASK) == SG_MEMCONF_CH2_NUM_2)
size *= 2;
dram_ch[2].size = size;
dram_map[2].size = size;
return 0;
}
int dram_init(void)
{
struct uniphier_dram_ch dram_ch[UNIPHIER_MAX_NR_DRAM_CH] = {};
struct uniphier_dram_map dram_map[3] = {};
int ret, i;
gd->ram_size = 0;
ret = uniphier_memconf_decode(dram_ch);
ret = uniphier_memconf_decode(dram_map);
if (ret)
return ret;
for (i = 0; i < ARRAY_SIZE(dram_ch); i++) {
for (i = 0; i < ARRAY_SIZE(dram_map); i++) {
if (!dram_ch[i].size)
if (!dram_map[i].size)
break;
/*
@ -215,11 +222,11 @@ int dram_init(void)
* but it does not expect sparse memory. We use the first
* contiguous chunk here.
*/
if (i > 0 &&
dram_ch[i - 1].base + dram_ch[i - 1].size < dram_ch[i].base)
if (i > 0 && dram_map[i - 1].base + dram_map[i - 1].size <
dram_map[i].base)
break;
gd->ram_size += dram_ch[i].size;
gd->ram_size += dram_map[i].size;
}
return 0;
@ -227,17 +234,17 @@ int dram_init(void)
void dram_init_banksize(void)
{
struct uniphier_dram_ch dram_ch[UNIPHIER_MAX_NR_DRAM_CH] = {};
struct uniphier_dram_map dram_map[3] = {};
int i;
uniphier_memconf_decode(dram_ch);
uniphier_memconf_decode(dram_map);
for (i = 0; i < ARRAY_SIZE(dram_ch); i++) {
for (i = 0; i < ARRAY_SIZE(dram_map); i++) {
if (i >= ARRAY_SIZE(gd->bd->bi_dram))
break;
gd->bd->bi_dram[i].start = dram_ch[i].base;
gd->bd->bi_dram[i].size = dram_ch[i].size;
gd->bd->bi_dram[i].start = dram_map[i].base;
gd->bd->bi_dram[i].size = dram_map[i].size;
}
}

4
arch/arm/mach-uniphier/init.h
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@ -13,7 +13,6 @@
#define UNIPHIER_MAX_NR_DRAM_CH 3
struct uniphier_dram_ch {
unsigned long base;
unsigned long size;
unsigned int width;
};
@ -24,7 +23,8 @@ struct uniphier_board_data {
struct uniphier_dram_ch dram_ch[UNIPHIER_MAX_NR_DRAM_CH];
unsigned int flags;
#define UNIPHIER_BD_DDR3PLUS BIT(2)
#define UNIPHIER_BD_DRAM_SPARSE BIT(9)
#define UNIPHIER_BD_DDR3PLUS BIT(8)
#define UNIPHIER_BD_BOARD_GET_TYPE(f) ((f) & 0x7)
#define UNIPHIER_BD_BOARD_LD20_REF 0 /* LD20 reference */

2
arch/arm/mach-uniphier/memconf.c
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@ -93,7 +93,7 @@ static int __uniphier_memconf_init(const struct uniphier_board_data *bd,
}
/* is sparse mem? */
if (bd->dram_ch[0].base + bd->dram_ch[0].size < bd->dram_ch[1].base)
if (bd->flags & UNIPHIER_BD_DRAM_SPARSE)
val |= SG_MEMCONF_SPARSEMEM;
if (!have_ch2)

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