@ -227,7 +227,7 @@ struct uart_port {
# define SCIF_ORER 0x0001 /* Overrun error bit */
# define SCSCR_INIT(port) 0x38 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */
# elif defined(CONFIG_R8A7790) || defined(CONFIG_R8A7791) || \
defined ( CONFIG_R8A7794 )
defined ( CONFIG_R8A7793 ) | | defined ( CONFIG_R8A779 4 )
# define SCIF_ORER 0x0001
# define SCSCR_INIT(port) 0x32 /* TIE=0,RIE=0,TE=1,RE=1,REIE=0, */
# else
@ -304,7 +304,8 @@ struct uart_port {
/* SH7763 SCIF2 support */
# define SCIF2_RFDC_MASK 0x001f
# define SCIF2_TXROOM_MAX 16
# elif defined(CONFIG_R8A7790) || defined(CONFIG_R8A7791)
# elif defined(CONFIG_R8A7790) || defined(CONFIG_R8A7791) || \
defined ( CONFIG_R8A7793 )
# define SCIF_ERRORS (SCIF_PER | SCIF_FER | SCIF_ER | SCIF_BRK)
# define SCIF_RFDC_MASK 0x003f
# else
@ -589,7 +590,7 @@ SCIF_FNS(SCSPTR, 0, 0, 0, 0)
SCIF_FNS ( SCSPTR , 0 , 0 , 0x20 , 16 )
# endif
# if defined(CONFIG_R8A7790) || defined(CONFIG_R8A7791) || \
defined ( CONFIG_R8A7794 )
defined ( CONFIG_R8A7793 ) | | defined ( CONFIG_R8A779 4 )
SCIF_FNS ( DL , 0 , 0 , 0x30 , 16 )
SCIF_FNS ( CKS , 0 , 0 , 0x34 , 16 )
# endif
@ -734,7 +735,8 @@ static inline int scbrr_calc(struct uart_port port, int bps, int clk)
# define SCBRR_VALUE(bps, clk) scbrr_calc(sh_sci, bps, clk)
# elif defined(__H8300H__) || defined(__H8300S__)
# define SCBRR_VALUE(bps, clk) (((clk*1000 / 32) / bps)-1)
# elif defined(CONFIG_R8A7790) || defined(CONFIG_R8A7791)
# elif defined(CONFIG_R8A7790) || defined(CONFIG_R8A7791) || \
defined ( CONFIG_R8A7793 )
# define DL_VALUE(bps, clk) (clk / bps / 16) /* External Clock */
# define SCBRR_VALUE(bps, clk) ((clk+16*bps) / (32*bps)-1) /* Internal Clock */
# else /* Generic SH */