Conflicts: boards.cfg Conflicts were trivial once u-boot-arm/master boards.cfg was reformatted (commitmaster6130c146) to match u-boot/master's own reformatting (commit1b37fa83).
Albert ARIBAUD
11 years ago
commit
05d134b084
@ -1,28 +0,0 @@ |
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/*
|
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* net.h - misc Blackfin network helpers |
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* |
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* Copyright (c) 2008-2009 Analog Devices Inc. |
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* |
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* Licensed under the GPL-2 or later. |
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*/ |
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|
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#ifndef __ASM_BFIN_RAND_MAC__ |
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#define __ASM_BFIN_RAND_MAC__ |
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/* If the board does not have a real MAC assigned to it, then generate a
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* locally administrated pseudo-random one based on CYCLES and compile date. |
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*/ |
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static inline void bfin_gen_rand_mac(uchar *mac_addr) |
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{ |
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/* make something up */ |
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const char s[] = __DATE__; |
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size_t i; |
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u32 cycles; |
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for (i = 0; i < 6; ++i) { |
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asm("%0 = CYCLES;" : "=r" (cycles)); |
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mac_addr[i] = cycles ^ s[i]; |
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} |
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mac_addr[0] = (mac_addr[0] | 0x02) & ~0x01; /* make it local unicast */ |
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} |
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#endif |
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@ -0,0 +1 @@ |
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*.dtb |
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@ -1,87 +0,0 @@ |
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/* |
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* (C) Copyright 2007 |
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* Wolfgang Denk, DENX Software Engineering, wd@denx.de. |
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* |
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* SPDX-License-Identifier: GPL-2.0+ |
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*/ |
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|
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OUTPUT_ARCH(powerpc) |
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SECTIONS |
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{ |
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/* Read-only sections, merged into text segment: */ |
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. = + SIZEOF_HEADERS; |
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.text : |
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{ |
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/* WARNING - the following is hand-optimized to fit within */ |
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/* the sector layout of our flash chips! XXX FIXME XXX */ |
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|
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arch/powerpc/cpu/ppc4xx/start.o (.text*) |
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|
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/* Align to next NAND block */ |
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. = ALIGN(0x4000); |
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common/env_embedded.o (.ppcenv) |
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/* Keep some space here for redundant env and potential bad env blocks */ |
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. = ALIGN(0x10000); |
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|
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*(.text*) |
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} |
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_etext = .; |
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PROVIDE (etext = .); |
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.rodata : |
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{ |
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*(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) |
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} |
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|
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/* Read-write section, merged into data segment: */ |
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. = (. + 0x00FF) & 0xFFFFFF00; |
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_erotext = .; |
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PROVIDE (erotext = .); |
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.reloc : |
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{ |
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KEEP(*(.got)) |
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_GOT2_TABLE_ = .; |
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KEEP(*(.got2)) |
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_FIXUP_TABLE_ = .; |
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KEEP(*(.fixup)) |
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} |
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__got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2; |
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__fixup_entries = (. - _FIXUP_TABLE_)>>2; |
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|
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.data : |
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{ |
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*(.data*) |
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*(.sdata*) |
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} |
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_edata = .; |
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PROVIDE (edata = .); |
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|
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. = .; |
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|
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.u_boot_list : { |
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KEEP(*(SORT(.u_boot_list*))); |
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} |
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|
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. = .; |
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__start___ex_table = .; |
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__ex_table : { *(__ex_table) } |
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__stop___ex_table = .; |
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|
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. = ALIGN(256); |
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__init_begin = .; |
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.text.init : { *(.text.init) } |
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.data.init : { *(.data.init) } |
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. = ALIGN(256); |
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__init_end = .; |
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|
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__bss_start = .; |
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.bss (NOLOAD) : |
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{ |
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*(.bss*) |
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*(.sbss*) |
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*(COMMON) |
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. = ALIGN(4); |
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} |
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|
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__bss_end = . ; |
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PROVIDE (end = .); |
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} |
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@ -1,88 +0,0 @@ |
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/* |
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* (C) Copyright 2007 |
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* Wolfgang Denk, DENX Software Engineering, wd@denx.de. |
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* |
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* SPDX-License-Identifier: GPL-2.0+ |
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*/ |
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|
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OUTPUT_ARCH(powerpc) |
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SECTIONS |
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{ |
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/* Read-only sections, merged into text segment: */ |
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. = + SIZEOF_HEADERS; |
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.text : |
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{ |
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/* WARNING - the following is hand-optimized to fit within */ |
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/* the sector layout of our flash chips! XXX FIXME XXX */ |
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|
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arch/powerpc/cpu/ppc4xx/start.o (.text*) |
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board/amcc/bamboo/init.o (.text*) |
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|
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/* Align to next NAND block */ |
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. = ALIGN(0x4000); |
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common/env_embedded.o (.ppcenv) |
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/* Keep some space here for redundant env and potential bad env blocks */ |
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. = ALIGN(0x10000); |
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|
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*(.text*) |
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} |
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_etext = .; |
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PROVIDE (etext = .); |
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.rodata : |
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{ |
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*(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) |
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} |
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|
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/* Read-write section, merged into data segment: */ |
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. = (. + 0x00FF) & 0xFFFFFF00; |
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_erotext = .; |
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PROVIDE (erotext = .); |
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.reloc : |
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{ |
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KEEP(*(.got)) |
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_GOT2_TABLE_ = .; |
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KEEP(*(.got2)) |
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_FIXUP_TABLE_ = .; |
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KEEP(*(.fixup)) |
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} |
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__got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2; |
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__fixup_entries = (. - _FIXUP_TABLE_)>>2; |
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|
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.data : |
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{ |
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*(.data*) |
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*(.sdata*) |
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} |
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_edata = .; |
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PROVIDE (edata = .); |
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|
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. = .; |
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|
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.u_boot_list : { |
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KEEP(*(SORT(.u_boot_list*))); |
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} |
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|
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. = .; |
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__start___ex_table = .; |
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__ex_table : { *(__ex_table) } |
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__stop___ex_table = .; |
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|
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. = ALIGN(256); |
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__init_begin = .; |
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.text.init : { *(.text.init) } |
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.data.init : { *(.data.init) } |
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. = ALIGN(256); |
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__init_end = .; |
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|
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__bss_start = .; |
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.bss (NOLOAD) : |
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{ |
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*(.bss*) |
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*(.sbss*) |
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*(COMMON) |
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. = ALIGN(4); |
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} |
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|
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__bss_end = . ; |
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PROVIDE (end = .); |
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} |
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@ -1,88 +0,0 @@ |
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/* |
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* (C) Copyright 2008 |
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* Stefan Roese, DENX Software Engineering, sr@denx.de. |
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* |
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* SPDX-License-Identifier: GPL-2.0+ |
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*/ |
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|
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OUTPUT_ARCH(powerpc) |
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SECTIONS |
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{ |
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/* Read-only sections, merged into text segment: */ |
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. = + SIZEOF_HEADERS; |
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.text : |
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{ |
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/* WARNING - the following is hand-optimized to fit within */ |
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/* the sector layout of our flash chips! XXX FIXME XXX */ |
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|
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arch/powerpc/cpu/ppc4xx/start.o (.text) |
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board/amcc/canyonlands/init.o (.text*) |
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|
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/* Align to next NAND block */ |
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. = ALIGN(0x20000); |
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common/env_embedded.o (.ppcenv) |
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/* Keep some space here for redundant env and potential bad env blocks */ |
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. = ALIGN(0x80000); |
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|
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*(.text*) |
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} |
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_etext = .; |
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PROVIDE (etext = .); |
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.rodata : |
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{ |
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*(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) |
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} |
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|
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/* Read-write section, merged into data segment: */ |
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. = (. + 0x00FF) & 0xFFFFFF00; |
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_erotext = .; |
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PROVIDE (erotext = .); |
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.reloc : |
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{ |
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KEEP(*(.got)) |
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_GOT2_TABLE_ = .; |
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KEEP(*(.got2)) |
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_FIXUP_TABLE_ = .; |
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KEEP(*(.fixup)) |
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} |
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__got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2; |
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__fixup_entries = (. - _FIXUP_TABLE_)>>2; |
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|
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.data : |
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{ |
||||
*(.data*) |
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*(.sdata*) |
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} |
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_edata = .; |
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PROVIDE (edata = .); |
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|
||||
. = .; |
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|
||||
.u_boot_list : { |
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KEEP(*(SORT(.u_boot_list*))); |
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} |
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|
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. = .; |
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__start___ex_table = .; |
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__ex_table : { *(__ex_table) } |
||||
__stop___ex_table = .; |
||||
|
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. = ALIGN(256); |
||||
__init_begin = .; |
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.text.init : { *(.text.init) } |
||||
.data.init : { *(.data.init) } |
||||
. = ALIGN(256); |
||||
__init_end = .; |
||||
|
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__bss_start = .; |
||||
.bss (NOLOAD) : |
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{ |
||||
*(.bss*) |
||||
*(.sbss*) |
||||
*(COMMON) |
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. = ALIGN(4); |
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} |
||||
|
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__bss_end = . ; |
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PROVIDE (end = .); |
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} |
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@ -1,87 +0,0 @@ |
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/* |
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* (C) Copyright 2007 |
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* Wolfgang Denk, DENX Software Engineering, wd@denx.de. |
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* |
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* SPDX-License-Identifier: GPL-2.0+ |
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*/ |
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|
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OUTPUT_ARCH(powerpc) |
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SECTIONS |
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{ |
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/* Read-only sections, merged into text segment: */ |
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. = + SIZEOF_HEADERS; |
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.text : |
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{ |
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/* WARNING - the following is hand-optimized to fit within */ |
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/* the sector layout of our flash chips! XXX FIXME XXX */ |
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|
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arch/powerpc/cpu/ppc4xx/start.o (.text*) |
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|
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/* Align to next NAND block */ |
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. = ALIGN(0x4000); |
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common/env_embedded.o (.ppcenv) |
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/* Keep some space here for redundant env and potential bad env blocks */ |
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. = ALIGN(0x10000); |
||||
|
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*(.text*) |
||||
} |
||||
_etext = .; |
||||
PROVIDE (etext = .); |
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.rodata : |
||||
{ |
||||
*(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) |
||||
} |
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|
||||
/* Read-write section, merged into data segment: */ |
||||
. = (. + 0x00FF) & 0xFFFFFF00; |
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_erotext = .; |
||||
PROVIDE (erotext = .); |
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.reloc : |
||||
{ |
||||
KEEP(*(.got)) |
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_GOT2_TABLE_ = .; |
||||
KEEP(*(.got2)) |
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_FIXUP_TABLE_ = .; |
||||
KEEP(*(.fixup)) |
||||
} |
||||
__got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2; |
||||
__fixup_entries = (. - _FIXUP_TABLE_)>>2; |
||||
|
||||
.data : |
||||
{ |
||||
*(.data*) |
||||
*(.sdata*) |
||||
} |
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_edata = .; |
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PROVIDE (edata = .); |
||||
|
||||
. = .; |
||||
|
||||
.u_boot_list : { |
||||
KEEP(*(SORT(.u_boot_list*))); |
||||
} |
||||
|
||||
. = .; |
||||
__start___ex_table = .; |
||||
__ex_table : { *(__ex_table) } |
||||
__stop___ex_table = .; |
||||
|
||||
. = ALIGN(256); |
||||
__init_begin = .; |
||||
.text.init : { *(.text.init) } |
||||
.data.init : { *(.data.init) } |
||||
. = ALIGN(256); |
||||
__init_end = .; |
||||
|
||||
__bss_start = .; |
||||
.bss (NOLOAD) : |
||||
{ |
||||
*(.bss*) |
||||
*(.sbss*) |
||||
*(COMMON) |
||||
. = ALIGN(4); |
||||
} |
||||
|
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__bss_end = . ; |
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PROVIDE (end = .); |
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} |
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@ -1,88 +0,0 @@ |
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/* |
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* (C) Copyright 2006 |
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* Wolfgang Denk, DENX Software Engineering, wd@denx.de. |
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* |
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* SPDX-License-Identifier: GPL-2.0+ |
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*/ |
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|
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OUTPUT_ARCH(powerpc) |
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SECTIONS |
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{ |
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/* Read-only sections, merged into text segment: */ |
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. = + SIZEOF_HEADERS; |
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.text : |
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{ |
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/* WARNING - the following is hand-optimized to fit within */ |
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/* the sector layout of our flash chips! XXX FIXME XXX */ |
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|
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arch/powerpc/cpu/ppc4xx/start.o (.text) |
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board/amcc/sequoia/init.o (.text*) |
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|
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/* Align to next NAND block */ |
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. = ALIGN(0x4000); |
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common/env_embedded.o (.ppcenv) |
||||
/* Keep some space here for redundant env and potential bad env blocks */ |
||||
. = ALIGN(0x10000); |
||||
|
||||
*(.text*) |
||||
} |
||||
_etext = .; |
||||
PROVIDE (etext = .); |
||||
.rodata : |
||||
{ |
||||
*(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) |
||||
} |
||||
|
||||
/* Read-write section, merged into data segment: */ |
||||
. = (. + 0x00FF) & 0xFFFFFF00; |
||||
_erotext = .; |
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PROVIDE (erotext = .); |
||||
.reloc : |
||||
{ |
||||
KEEP(*(.got)) |
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_GOT2_TABLE_ = .; |
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KEEP(*(.got2)) |
||||
_FIXUP_TABLE_ = .; |
||||
KEEP(*(.fixup)) |
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} |
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__got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2; |
||||
__fixup_entries = (. - _FIXUP_TABLE_)>>2; |
||||
|
||||
.data : |
||||
{ |
||||
*(.data*) |
||||
*(.sdata*) |
||||
} |
||||
_edata = .; |
||||
PROVIDE (edata = .); |
||||
|
||||
. = .; |
||||
|
||||
.u_boot_list : { |
||||
KEEP(*(SORT(.u_boot_list*))); |
||||
} |
||||
|
||||
. = .; |
||||
__start___ex_table = .; |
||||
__ex_table : { *(__ex_table) } |
||||
__stop___ex_table = .; |
||||
|
||||
. = ALIGN(256); |
||||
__init_begin = .; |
||||
.text.init : { *(.text.init) } |
||||
.data.init : { *(.data.init) } |
||||
. = ALIGN(256); |
||||
__init_end = .; |
||||
|
||||
__bss_start = .; |
||||
.bss (NOLOAD) : |
||||
{ |
||||
*(.bss*) |
||||
*(.sbss*) |
||||
*(COMMON) |
||||
. = ALIGN(4); |
||||
} |
||||
|
||||
__bss_end = . ; |
||||
PROVIDE (end = .); |
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} |
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@ -1,118 +0,0 @@ |
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/* |
||||
* (C) Copyright 2006 |
||||
* Wolfgang Denk, DENX Software Engineering, wd@denx.de. |
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* |
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* SPDX-License-Identifier: GPL-2.0+ |
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*/ |
||||
|
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OUTPUT_ARCH(powerpc) |
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SECTIONS |
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{ |
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/* Read-only sections, merged into text segment: */ |
||||
. = + SIZEOF_HEADERS; |
||||
.interp : { *(.interp) } |
||||
.hash : { *(.hash) } |
||||
.dynsym : { *(.dynsym) } |
||||
.dynstr : { *(.dynstr) } |
||||
.rel.text : { *(.rel.text) } |
||||
.rela.text : { *(.rela.text) } |
||||
.rel.data : { *(.rel.data) } |
||||
.rela.data : { *(.rela.data) } |
||||
.rel.rodata : { *(.rel.rodata) } |
||||
.rela.rodata : { *(.rela.rodata) } |
||||
.rel.got : { *(.rel.got) } |
||||
.rela.got : { *(.rela.got) } |
||||
.rel.ctors : { *(.rel.ctors) } |
||||
.rela.ctors : { *(.rela.ctors) } |
||||
.rel.dtors : { *(.rel.dtors) } |
||||
.rela.dtors : { *(.rela.dtors) } |
||||
.rel.bss : { *(.rel.bss) } |
||||
.rela.bss : { *(.rela.bss) } |
||||
.rel.plt : { *(.rel.plt) } |
||||
.rela.plt : { *(.rela.plt) } |
||||
.init : { *(.init) } |
||||
.plt : { *(.plt) } |
||||
.text : |
||||
{ |
||||
/* WARNING - the following is hand-optimized to fit within */ |
||||
/* the sector layout of our flash chips! XXX FIXME XXX */ |
||||
|
||||
arch/powerpc/cpu/ppc4xx/start.o (.text) |
||||
|
||||
/* Align to next NAND block */ |
||||
. = ALIGN(0x4000); |
||||
common/env_embedded.o (.ppcenv) |
||||
/* Keep some space here for redundant env and potential bad env blocks */ |
||||
. = ALIGN(0x10000); |
||||
|
||||
*(.text) |
||||
*(.got1) |
||||
} |
||||
_etext = .; |
||||
PROVIDE (etext = .); |
||||
.rodata : |
||||
{ |
||||
*(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) |
||||
} |
||||
.fini : { *(.fini) } =0 |
||||
.ctors : { *(.ctors) } |
||||
.dtors : { *(.dtors) } |
||||
|
||||
/* Read-write section, merged into data segment: */ |
||||
. = (. + 0x00FF) & 0xFFFFFF00; |
||||
_erotext = .; |
||||
PROVIDE (erotext = .); |
||||
.reloc : |
||||
{ |
||||
*(.got) |
||||
_GOT2_TABLE_ = .; |
||||
*(.got2) |
||||
_FIXUP_TABLE_ = .; |
||||
*(.fixup) |
||||
} |
||||
__got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2; |
||||
__fixup_entries = (. - _FIXUP_TABLE_)>>2; |
||||
|
||||
.data : |
||||
{ |
||||
*(.data) |
||||
*(.data1) |
||||
*(.sdata) |
||||
*(.sdata2) |
||||
*(.dynamic) |
||||
CONSTRUCTORS |
||||
} |
||||
_edata = .; |
||||
PROVIDE (edata = .); |
||||
|
||||
. = .; |
||||
|
||||
.u_boot_list : { |
||||
KEEP(*(SORT(.u_boot_list*))); |
||||
} |
||||
|
||||
. = .; |
||||
__start___ex_table = .; |
||||
__ex_table : { *(__ex_table) } |
||||
__stop___ex_table = .; |
||||
|
||||
. = ALIGN(256); |
||||
__init_begin = .; |
||||
.text.init : { *(.text.init) } |
||||
.data.init : { *(.data.init) } |
||||
. = ALIGN(256); |
||||
__init_end = .; |
||||
|
||||
__bss_start = .; |
||||
.bss (NOLOAD) : |
||||
{ |
||||
*(.sbss) *(.scommon) |
||||
*(.dynbss) |
||||
*(.bss) |
||||
*(COMMON) |
||||
. = ALIGN(4); |
||||
} |
||||
|
||||
__bss_end = . ; |
||||
PROVIDE (end = .); |
||||
} |
||||
@ -0,0 +1,235 @@ |
||||
/*
|
||||
* Copyright 2013 Freescale Semiconductor, Inc. |
||||
* |
||||
* SPDX-License-Identifier: GPL-2.0+ |
||||
*/ |
||||
|
||||
/* Power-One ZM7300 DPM */ |
||||
#include "zm7300.h" |
||||
|
||||
#define DPM_WP 0x96 |
||||
#define WRP_OPCODE 0x01 |
||||
#define WRM_OPCODE 0x02 |
||||
#define RRP_OPCODE 0x11 |
||||
|
||||
#define DPM_SUCCESS 0x01 |
||||
#define DPM_EXEC_FAIL 0x00 |
||||
|
||||
static const uint16_t hex_to_1_10mv[] = { |
||||
5000, |
||||
5125, |
||||
5250, |
||||
5375, |
||||
5500, |
||||
5625, |
||||
5750, |
||||
5875, |
||||
6000, |
||||
6125, |
||||
6250, |
||||
6375, |
||||
6500, |
||||
6625, |
||||
6750, |
||||
6875, |
||||
7000, |
||||
7125, |
||||
7250, |
||||
7375, |
||||
7500, |
||||
7625, |
||||
7750, |
||||
7875, |
||||
8000, |
||||
8125, |
||||
8250, |
||||
8375, |
||||
8500, |
||||
8625, |
||||
8750, |
||||
8875, |
||||
9000, |
||||
9125, |
||||
9250, |
||||
9375, |
||||
9500, /* 0.95mV */ |
||||
9625, |
||||
9750, |
||||
9875, |
||||
10000, /* 1.0V */ |
||||
10125, |
||||
10250, |
||||
10375, |
||||
10500, |
||||
10625, |
||||
10750, |
||||
10875, |
||||
11000, |
||||
11125, |
||||
11250, |
||||
11375, |
||||
11500, |
||||
11625, |
||||
11750, |
||||
11875, |
||||
12000, |
||||
12125, |
||||
12250, |
||||
12375, |
||||
0, /* reserved */ |
||||
}; |
||||
|
||||
|
||||
/* Read Data d from Register r of POL p */ |
||||
u8 dpm_rrp(uchar r) |
||||
{ |
||||
u8 ret[5]; |
||||
|
||||
ret[0] = RRP_OPCODE; |
||||
/* POL is 0 */ |
||||
ret[1] = 0; |
||||
ret[2] = r; |
||||
i2c_read(I2C_DPM_ADDR, 0, -3, ret, 2); |
||||
if (ret[1] == DPM_SUCCESS) { /* the DPM returned success as status */ |
||||
debug("RRP_OPCODE returned success data is %x\n", ret[0]); |
||||
return ret[0]; |
||||
} else { |
||||
return -1; |
||||
} |
||||
} |
||||
|
||||
/* Write Data d into DPM register r (RAM) */ |
||||
int dpm_wrm(u8 r, u8 d) |
||||
{ |
||||
u8 ret[5]; |
||||
|
||||
ret[0] = WRM_OPCODE; |
||||
ret[1] = r; |
||||
ret[2] = d; |
||||
i2c_read(I2C_DPM_ADDR, 0, -3, ret, 1); |
||||
if (ret[0] == DPM_SUCCESS) { /* the DPM returned success as status */ |
||||
debug("WRM_OPCODE returned success data is %x\n", ret[0]); |
||||
return ret[0]; |
||||
} else { |
||||
return -1; |
||||
} |
||||
} |
||||
|
||||
/* Write Data d into Register r of POL(s) a */ |
||||
int dpm_wrp(u8 r, u8 d) |
||||
{ |
||||
u8 ret[7]; |
||||
|
||||
ret[0] = WRP_OPCODE; |
||||
/* only POL0 is present */ |
||||
ret[1] = 0x01; |
||||
ret[2] = 0x00; |
||||
ret[3] = 0x00; |
||||
ret[4] = 0x00; |
||||
ret[5] = r; |
||||
ret[6] = d; |
||||
i2c_read(I2C_DPM_ADDR, 0, -7, ret, 1); |
||||
if (ret[0] == DPM_SUCCESS) { /* the DPM returned success as status */ |
||||
debug("WRP_OPCODE returned success data is %x\n", ret[0]); |
||||
return 0; |
||||
} else { |
||||
return -1; |
||||
} |
||||
} |
||||
|
||||
/* Uses the DPM command RRP */ |
||||
u8 zm_read(uchar reg) |
||||
{ |
||||
u8 d; |
||||
d = dpm_rrp(reg); |
||||
return d; |
||||
} |
||||
|
||||
/* ZM_write --
|
||||
Steps: |
||||
a. Write data to the register |
||||
b. Read data from register and compare to written value |
||||
c. Return return_code & voltage_read |
||||
*/ |
||||
u8 zm_write(u8 reg, u8 data) |
||||
{ |
||||
u8 d; |
||||
|
||||
/* write data to register */ |
||||
dpm_wrp(reg, data); |
||||
|
||||
/* read register and compare to written value */ |
||||
d = dpm_rrp(reg); |
||||
if (d != data) { |
||||
printf("zm_write : Comparison register data failed\n"); |
||||
return -1; |
||||
} |
||||
|
||||
return d; |
||||
} |
||||
|
||||
/* zm_write_out_voltage
|
||||
* voltage in 1/10 mV |
||||
*/ |
||||
int zm_write_voltage(int voltage) |
||||
{ |
||||
u8 reg = 0x7, vid; |
||||
uint16_t voltage_read; |
||||
u8 ret; |
||||
|
||||
vid = (voltage - 5000) / ZM_STEP; |
||||
|
||||
ret = zm_write(reg, vid); |
||||
if (ret != -1) { |
||||
voltage_read = hex_to_1_10mv[ret]; |
||||
debug("voltage set to %dmV\n", voltage_read/10); |
||||
return voltage_read; |
||||
} |
||||
return -1; |
||||
} |
||||
|
||||
/* zm_read_out_voltage
|
||||
* voltage in 1/10 mV |
||||
*/ |
||||
int zm_read_voltage(void) |
||||
{ |
||||
u8 reg = 0x7; |
||||
u8 ret; |
||||
int voltage; |
||||
|
||||
ret = zm_read(reg); |
||||
if (ret != -1) { |
||||
voltage = hex_to_1_10mv[ret]; |
||||
debug("Voltage read is %dmV\n", voltage/10); |
||||
return voltage; |
||||
} else { |
||||
return -1; |
||||
} |
||||
} |
||||
|
||||
int zm_disable_wp() |
||||
{ |
||||
u8 new_wp_value; |
||||
|
||||
/* Disable using Write-Protect register 0x96 */ |
||||
new_wp_value = 0x8; |
||||
if ((dpm_wrm(DPM_WP, new_wp_value)) < 0) { |
||||
printf("Disable Write-Protect register failed\n"); |
||||
return -1; |
||||
} |
||||
return 0; |
||||
} |
||||
|
||||
int zm_enable_wp() |
||||
{ |
||||
u8 orig_wp_value; |
||||
orig_wp_value = 0x0; |
||||
|
||||
/* Enable using Write-Protect register 0x96 */ |
||||
if ((dpm_wrm(DPM_WP, orig_wp_value)) < 0) { |
||||
printf("Enable Write-Protect register failed\n"); |
||||
return -1; |
||||
} |
||||
return 0; |
||||
} |
||||
|
||||
@ -0,0 +1,22 @@ |
||||
/*
|
||||
* Copyright 2013 Freescale Semiconductor, Inc. |
||||
* |
||||
* SPDX-License-Identifier: GPL-2.0+ |
||||
*/ |
||||
|
||||
#ifndef __ZM7300_H_ |
||||
#define __ZM7300_H 1_ |
||||
|
||||
#include <common.h> |
||||
#include <i2c.h> |
||||
#include <errno.h> |
||||
#include <asm/io.h> |
||||
|
||||
#define ZM_STEP 125 |
||||
int zm7300_set_voltage(int voltage_1_10mv); |
||||
int zm_write_voltage(int voltage); |
||||
int zm_read_voltage(void); |
||||
int zm_disable_wp(void); |
||||
int zm_enable_wp(void); |
||||
|
||||
#endif /* __ZM7300_H_ */ |
||||
@ -0,0 +1,141 @@ |
||||
/*
|
||||
* Copyright 2013 Freescale Semiconductor, Inc. |
||||
* |
||||
* SPDX-License-Identifier: GPL-2.0+ |
||||
*/ |
||||
|
||||
#include <common.h> |
||||
#include <ns16550.h> |
||||
#include <malloc.h> |
||||
#include <mmc.h> |
||||
#include <nand.h> |
||||
#include <i2c.h> |
||||
#include <fsl_esdhc.h> |
||||
#include <spi_flash.h> |
||||
|
||||
DECLARE_GLOBAL_DATA_PTR; |
||||
|
||||
#define SYSCLK_MASK 0x00200000 |
||||
#define BOARDREV_MASK 0x10100000 |
||||
|
||||
#define SYSCLK_66 66666666 |
||||
#define SYSCLK_100 100000000 |
||||
|
||||
unsigned long get_board_sys_clk(ulong dummy) |
||||
{ |
||||
ccsr_gpio_t *pgpio = (void *)(CONFIG_SYS_MPC85xx_GPIO_ADDR); |
||||
u32 val_gpdat, sysclk_gpio; |
||||
|
||||
val_gpdat = in_be32(&pgpio->gpdat); |
||||
sysclk_gpio = val_gpdat & SYSCLK_MASK; |
||||
|
||||
if (sysclk_gpio == 0) |
||||
return SYSCLK_66; |
||||
else |
||||
return SYSCLK_100; |
||||
|
||||
return 0; |
||||
} |
||||
|
||||
phys_size_t get_effective_memsize(void) |
||||
{ |
||||
return CONFIG_SYS_L2_SIZE; |
||||
} |
||||
|
||||
void board_init_f(ulong bootflag) |
||||
{ |
||||
u32 plat_ratio, bus_clk; |
||||
ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR; |
||||
|
||||
console_init_f(); |
||||
|
||||
/* Set pmuxcr to allow both i2c1 and i2c2 */ |
||||
setbits_be32(&gur->pmuxcr, in_be32(&gur->pmuxcr) | 0x1000); |
||||
setbits_be32(&gur->pmuxcr, |
||||
in_be32(&gur->pmuxcr) | MPC85xx_PMUXCR_SD_DATA); |
||||
|
||||
/* Read back the register to synchronize the write. */ |
||||
in_be32(&gur->pmuxcr); |
||||
|
||||
#ifdef CONFIG_SPL_SPI_BOOT |
||||
clrbits_be32(&gur->pmuxcr, MPC85xx_PMUXCR_SD_DATA); |
||||
#endif |
||||
|
||||
/* initialize selected port with appropriate baud rate */ |
||||
plat_ratio = in_be32(&gur->porpllsr) & MPC85xx_PORPLLSR_PLAT_RATIO; |
||||
plat_ratio >>= 1; |
||||
bus_clk = CONFIG_SYS_CLK_FREQ * plat_ratio; |
||||
gd->bus_clk = bus_clk; |
||||
|
||||
NS16550_init((NS16550_t)CONFIG_SYS_NS16550_COM1, |
||||
bus_clk / 16 / CONFIG_BAUDRATE); |
||||
#ifdef CONFIG_SPL_MMC_BOOT |
||||
puts("\nSD boot...\n"); |
||||
#elif defined(CONFIG_SPL_SPI_BOOT) |
||||
puts("\nSPI Flash boot...\n"); |
||||
#endif |
||||
|
||||
/* copy code to RAM and jump to it - this should not return */ |
||||
/* NOTE - code has to be copied out of NAND buffer before
|
||||
* other blocks can be read. |
||||
*/ |
||||
relocate_code(CONFIG_SPL_RELOC_STACK, 0, CONFIG_SPL_RELOC_TEXT_BASE); |
||||
} |
||||
|
||||
void board_init_r(gd_t *gd, ulong dest_addr) |
||||
{ |
||||
/* Pointer is writable since we allocated a register for it */ |
||||
gd = (gd_t *)CONFIG_SPL_GD_ADDR; |
||||
bd_t *bd; |
||||
|
||||
memset(gd, 0, sizeof(gd_t)); |
||||
bd = (bd_t *)(CONFIG_SPL_GD_ADDR + sizeof(gd_t)); |
||||
memset(bd, 0, sizeof(bd_t)); |
||||
gd->bd = bd; |
||||
bd->bi_memstart = CONFIG_SYS_INIT_L2_ADDR; |
||||
bd->bi_memsize = CONFIG_SYS_L2_SIZE; |
||||
|
||||
probecpu(); |
||||
get_clocks(); |
||||
mem_malloc_init(CONFIG_SPL_RELOC_MALLOC_ADDR, |
||||
CONFIG_SPL_RELOC_MALLOC_SIZE); |
||||
|
||||
#ifdef CONFIG_SPL_MMC_BOOT |
||||
mmc_initialize(bd); |
||||
#endif |
||||
/* relocate environment function pointers etc. */ |
||||
#ifdef CONFIG_SPL_NAND_BOOT |
||||
nand_spl_load_image(CONFIG_ENV_OFFSET, CONFIG_ENV_SIZE, |
||||
(uchar *)CONFIG_ENV_ADDR); |
||||
#endif |
||||
#ifdef CONFIG_SPL_NAND_BOOT |
||||
nand_spl_load_image(CONFIG_ENV_OFFSET, CONFIG_ENV_SIZE, |
||||
(uchar *)CONFIG_ENV_ADDR); |
||||
#endif |
||||
#ifdef CONFIG_SPL_MMC_BOOT |
||||
mmc_spl_load_image(CONFIG_ENV_OFFSET, CONFIG_ENV_SIZE, |
||||
(uchar *)CONFIG_ENV_ADDR); |
||||
#endif |
||||
#ifdef CONFIG_SPL_SPI_BOOT |
||||
spi_spl_load_image(CONFIG_ENV_OFFSET, CONFIG_ENV_SIZE, |
||||
(uchar *)CONFIG_ENV_ADDR); |
||||
#endif |
||||
|
||||
gd->env_addr = (ulong)(CONFIG_ENV_ADDR); |
||||
gd->env_valid = 1; |
||||
|
||||
gd->ram_size = initdram(0); |
||||
#ifdef CONFIG_SPL_NAND_BOOT |
||||
puts("Tertiary program loader running in sram..."); |
||||
#else |
||||
puts("Second program loader running in sram...\n"); |
||||
#endif |
||||
|
||||
#ifdef CONFIG_SPL_MMC_BOOT |
||||
mmc_boot(); |
||||
#elif defined(CONFIG_SPL_SPI_BOOT) |
||||
spi_boot(); |
||||
#elif defined(CONFIG_SPL_NAND_BOOT) |
||||
nand_boot(); |
||||
#endif |
||||
} |
||||
@ -0,0 +1,84 @@ |
||||
/*
|
||||
* Copyright 2011 Freescale Semiconductor, Inc. |
||||
* |
||||
* SPDX-License-Identifier: GPL-2.0+ |
||||
*/ |
||||
|
||||
#include <common.h> |
||||
#include <ns16550.h> |
||||
#include <asm/io.h> |
||||
#include <nand.h> |
||||
#include <linux/compiler.h> |
||||
#include <asm/fsl_law.h> |
||||
#include <fsl_ddr_sdram.h> |
||||
#include <asm/global_data.h> |
||||
|
||||
DECLARE_GLOBAL_DATA_PTR; |
||||
#define SYSCLK_MASK 0x00200000 |
||||
#define BOARDREV_MASK 0x10100000 |
||||
|
||||
#define SYSCLK_66 66666666 |
||||
#define SYSCLK_100 100000000 |
||||
|
||||
unsigned long get_board_sys_clk(ulong dummy) |
||||
{ |
||||
ccsr_gpio_t *pgpio = (void *)(CONFIG_SYS_MPC85xx_GPIO_ADDR); |
||||
u32 val_gpdat, sysclk_gpio; |
||||
|
||||
val_gpdat = in_be32(&pgpio->gpdat); |
||||
sysclk_gpio = val_gpdat & SYSCLK_MASK; |
||||
|
||||
if (sysclk_gpio == 0) |
||||
return SYSCLK_66; |
||||
else |
||||
return SYSCLK_100; |
||||
|
||||
return 0; |
||||
} |
||||
|
||||
void board_init_f(ulong bootflag) |
||||
{ |
||||
u32 plat_ratio; |
||||
ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR; |
||||
|
||||
#if defined(CONFIG_SYS_NAND_BR_PRELIM) && defined(CONFIG_SYS_NAND_OR_PRELIM) |
||||
set_lbc_br(0, CONFIG_SYS_NAND_BR_PRELIM); |
||||
set_lbc_or(0, CONFIG_SYS_NAND_OR_PRELIM); |
||||
#endif |
||||
|
||||
/* initialize selected port with appropriate baud rate */ |
||||
plat_ratio = in_be32(&gur->porpllsr) & MPC85xx_PORPLLSR_PLAT_RATIO; |
||||
plat_ratio >>= 1; |
||||
gd->bus_clk = CONFIG_SYS_CLK_FREQ * plat_ratio; |
||||
|
||||
NS16550_init((NS16550_t)CONFIG_SYS_NS16550_COM1, |
||||
gd->bus_clk / 16 / CONFIG_BAUDRATE); |
||||
|
||||
puts("\nNAND boot... "); |
||||
|
||||
/* copy code to RAM and jump to it - this should not return */ |
||||
/* NOTE - code has to be copied out of NAND buffer before
|
||||
* other blocks can be read. |
||||
*/ |
||||
relocate_code(CONFIG_SPL_RELOC_STACK, 0, CONFIG_SPL_RELOC_TEXT_BASE); |
||||
} |
||||
|
||||
void board_init_r(gd_t *gd, ulong dest_addr) |
||||
{ |
||||
puts("\nSecond program loader running in sram..."); |
||||
nand_boot(); |
||||
} |
||||
|
||||
void putc(char c) |
||||
{ |
||||
if (c == '\n') |
||||
NS16550_putc((NS16550_t)CONFIG_SYS_NS16550_COM1, '\r'); |
||||
|
||||
NS16550_putc((NS16550_t)CONFIG_SYS_NS16550_COM1, c); |
||||
} |
||||
|
||||
void puts(const char *str) |
||||
{ |
||||
while (*str) |
||||
putc(*str++); |
||||
} |
||||
@ -0,0 +1,12 @@ |
||||
#
|
||||
# Copyright 2014 Freescale Semiconductor, Inc.
|
||||
#
|
||||
# SPDX-License-Identifier: GPL-2.0+
|
||||
#
|
||||
|
||||
obj-$(CONFIG_T4240RDB) += t4240rdb.o
|
||||
obj-y += ddr.o
|
||||
obj-y += eth.o
|
||||
obj-$(CONFIG_PCI) += pci.o
|
||||
obj-y += law.o
|
||||
obj-y += tlb.o
|
||||
@ -0,0 +1,118 @@ |
||||
/*
|
||||
* Copyright 2014 Freescale Semiconductor, Inc. |
||||
* |
||||
* SPDX-License-Identifier: GPL-2.0+ |
||||
*/ |
||||
|
||||
#include <common.h> |
||||
#include <i2c.h> |
||||
#include <hwconfig.h> |
||||
#include <asm/mmu.h> |
||||
#include <fsl_ddr_sdram.h> |
||||
#include <fsl_ddr_dimm_params.h> |
||||
#include <asm/fsl_law.h> |
||||
#include "ddr.h" |
||||
|
||||
DECLARE_GLOBAL_DATA_PTR; |
||||
|
||||
void fsl_ddr_board_options(memctl_options_t *popts, |
||||
dimm_params_t *pdimm, |
||||
unsigned int ctrl_num) |
||||
{ |
||||
const struct board_specific_parameters *pbsp, *pbsp_highest = NULL; |
||||
ulong ddr_freq; |
||||
|
||||
if (ctrl_num > 2) { |
||||
printf("Not supported controller number %d\n", ctrl_num); |
||||
return; |
||||
} |
||||
if (!pdimm->n_ranks) |
||||
return; |
||||
|
||||
/*
|
||||
* we use identical timing for all slots. If needed, change the code |
||||
* to pbsp = rdimms[ctrl_num] or pbsp = udimms[ctrl_num]; |
||||
*/ |
||||
if (popts->registered_dimm_en) |
||||
pbsp = rdimms[0]; |
||||
else |
||||
pbsp = udimms[0]; |
||||
|
||||
|
||||
/* Get clk_adjust, cpo, write_data_delay,2T, according to the board ddr
|
||||
* freqency and n_banks specified in board_specific_parameters table. |
||||
*/ |
||||
ddr_freq = get_ddr_freq(0) / 1000000; |
||||
while (pbsp->datarate_mhz_high) { |
||||
if (pbsp->n_ranks == pdimm->n_ranks && |
||||
(pdimm->rank_density >> 30) >= pbsp->rank_gb) { |
||||
if (ddr_freq <= pbsp->datarate_mhz_high) { |
||||
popts->clk_adjust = pbsp->clk_adjust; |
||||
popts->wrlvl_start = pbsp->wrlvl_start; |
||||
popts->wrlvl_ctl_2 = pbsp->wrlvl_ctl_2; |
||||
popts->wrlvl_ctl_3 = pbsp->wrlvl_ctl_3; |
||||
goto found; |
||||
} |
||||
pbsp_highest = pbsp; |
||||
} |
||||
pbsp++; |
||||
} |
||||
|
||||
if (pbsp_highest) { |
||||
printf("Error: board specific timing not found for data\n" |
||||
"rate %lu MT/s\n" |
||||
"Trying to use the highest speed (%u) parameters\n", |
||||
ddr_freq, pbsp_highest->datarate_mhz_high); |
||||
popts->clk_adjust = pbsp_highest->clk_adjust; |
||||
popts->wrlvl_start = pbsp_highest->wrlvl_start; |
||||
popts->wrlvl_ctl_2 = pbsp->wrlvl_ctl_2; |
||||
popts->wrlvl_ctl_3 = pbsp->wrlvl_ctl_3; |
||||
} else { |
||||
panic("DIMM is not supported by this board"); |
||||
} |
||||
found: |
||||
debug("Found timing match: n_ranks %d, data rate %d, rank_gb %d\n" |
||||
"\tclk_adjust %d, wrlvl_start %d, wrlvl_ctrl_2 0x%x,\n" |
||||
"wrlvl_ctrl_3 0x%x\n", |
||||
pbsp->n_ranks, pbsp->datarate_mhz_high, pbsp->rank_gb, |
||||
pbsp->clk_adjust, pbsp->wrlvl_start, pbsp->wrlvl_ctl_2, |
||||
pbsp->wrlvl_ctl_3); |
||||
|
||||
/*
|
||||
* Factors to consider for half-strength driver enable: |
||||
* - number of DIMMs installed |
||||
*/ |
||||
popts->half_strength_driver_enable = 0; |
||||
/*
|
||||
* Write leveling override |
||||
*/ |
||||
popts->wrlvl_override = 1; |
||||
popts->wrlvl_sample = 0xf; |
||||
|
||||
/*
|
||||
* Rtt and Rtt_WR override |
||||
*/ |
||||
popts->rtt_override = 0; |
||||
|
||||
/* Enable ZQ calibration */ |
||||
popts->zq_en = 1; |
||||
|
||||
/* DHC_EN =1, ODT = 75 Ohm */ |
||||
popts->ddr_cdr1 = DDR_CDR1_DHC_EN | DDR_CDR1_ODT(DDR_CDR_ODT_75ohm); |
||||
popts->ddr_cdr2 = DDR_CDR2_ODT(DDR_CDR_ODT_75ohm); |
||||
} |
||||
|
||||
phys_size_t initdram(int board_type) |
||||
{ |
||||
phys_size_t dram_size; |
||||
|
||||
puts("Initializing....using SPD\n"); |
||||
|
||||
dram_size = fsl_ddr_sdram(); |
||||
|
||||
dram_size = setup_ddr_tlbs(dram_size / 0x100000); |
||||
dram_size *= 0x100000; |
||||
|
||||
puts(" DDR: "); |
||||
return dram_size; |
||||
} |
||||
@ -0,0 +1,78 @@ |
||||
/*
|
||||
* Copyright 2014 Freescale Semiconductor, Inc. |
||||
* |
||||
* SPDX-License-Identifier: GPL-2.0+ |
||||
*/ |
||||
|
||||
#ifndef __DDR_H__ |
||||
#define __DDR_H__ |
||||
struct board_specific_parameters { |
||||
u32 n_ranks; |
||||
u32 datarate_mhz_high; |
||||
u32 rank_gb; |
||||
u32 clk_adjust; |
||||
u32 wrlvl_start; |
||||
u32 wrlvl_ctl_2; |
||||
u32 wrlvl_ctl_3; |
||||
}; |
||||
|
||||
/*
|
||||
* These tables contain all valid speeds we want to override with board |
||||
* specific parameters. datarate_mhz_high values need to be in ascending order |
||||
* for each n_ranks group. |
||||
*/ |
||||
static const struct board_specific_parameters udimm0[] = { |
||||
/*
|
||||
* memory controller 0 |
||||
* num| hi| rank| clk| wrlvl | wrlvl | wrlvl |
||||
* ranks| mhz| GB |adjst| start | ctl2 | ctl3 |
||||
*/ |
||||
{2, 1350, 4, 4, 8, 0x0809090b, 0x0c0c0d0a}, |
||||
{2, 1350, 0, 5, 7, 0x0709090b, 0x0c0c0d09}, |
||||
{2, 1666, 4, 4, 8, 0x080a0a0d, 0x0d10100b}, |
||||
{2, 1666, 0, 5, 7, 0x080a0a0c, 0x0d0d0e0a}, |
||||
{2, 1900, 0, 4, 8, 0x090a0b0e, 0x0f11120c}, |
||||
{2, 2140, 0, 4, 8, 0x090a0b0e, 0x0f11120c}, |
||||
{1, 1350, 0, 5, 8, 0x0809090b, 0x0c0c0d0a}, |
||||
{1, 1700, 0, 5, 8, 0x080a0a0c, 0x0c0d0e0a}, |
||||
{1, 1900, 0, 4, 8, 0x080a0a0c, 0x0e0e0f0a}, |
||||
{1, 2140, 0, 4, 8, 0x090a0b0c, 0x0e0f100b}, |
||||
{} |
||||
}; |
||||
|
||||
static const struct board_specific_parameters rdimm0[] = { |
||||
/*
|
||||
* memory controller 0 |
||||
* num| hi| rank| clk| wrlvl | wrlvl | wrlvl |
||||
* ranks| mhz| GB |adjst| start | ctl2 | ctl3 |
||||
*/ |
||||
{4, 1350, 0, 5, 9, 0x08070605, 0x06070806}, |
||||
{4, 1666, 0, 5, 11, 0x0a080706, 0x07090906}, |
||||
{4, 2140, 0, 5, 12, 0x0b090807, 0x080a0b07}, |
||||
{2, 1350, 0, 5, 9, 0x08070605, 0x06070806}, |
||||
{2, 1666, 0, 5, 11, 0x0a090806, 0x08090a06}, |
||||
{2, 2140, 0, 5, 12, 0x0b090807, 0x080a0b07}, |
||||
{1, 1350, 0, 5, 9, 0x08070605, 0x06070806}, |
||||
{1, 1666, 0, 5, 11, 0x0a090806, 0x08090a06}, |
||||
{1, 2140, 0, 4, 12, 0x0b090807, 0x080a0b07}, |
||||
{} |
||||
}; |
||||
|
||||
/*
|
||||
* The three slots have slightly different timing. The center values are good |
||||
* for all slots. We use identical speed tables for them. In future use, if |
||||
* DIMMs require separated tables, make more entries as needed. |
||||
*/ |
||||
static const struct board_specific_parameters *udimms[] = { |
||||
udimm0, |
||||
}; |
||||
|
||||
/*
|
||||
* The three slots have slightly different timing. See comments above. |
||||
*/ |
||||
static const struct board_specific_parameters *rdimms[] = { |
||||
rdimm0, |
||||
}; |
||||
|
||||
|
||||
#endif |
||||
@ -0,0 +1,146 @@ |
||||
/*
|
||||
* Copyright 2014 Freescale Semiconductor, Inc. |
||||
* |
||||
* Chunhe Lan <Chunhe.Lan@freescale.com> |
||||
* |
||||
* SPDX-License-Identifier: GPL-2.0+ |
||||
*/ |
||||
|
||||
#include <common.h> |
||||
#include <command.h> |
||||
#include <netdev.h> |
||||
#include <asm/mmu.h> |
||||
#include <asm/processor.h> |
||||
#include <asm/cache.h> |
||||
#include <asm/immap_85xx.h> |
||||
#include <asm/fsl_law.h> |
||||
#include <fsl_ddr_sdram.h> |
||||
#include <asm/fsl_serdes.h> |
||||
#include <asm/fsl_portals.h> |
||||
#include <asm/fsl_liodn.h> |
||||
#include <malloc.h> |
||||
#include <fm_eth.h> |
||||
#include <fsl_mdio.h> |
||||
#include <miiphy.h> |
||||
#include <phy.h> |
||||
#include <asm/fsl_dtsec.h> |
||||
#include <asm/fsl_serdes.h> |
||||
#include <hwconfig.h> |
||||
|
||||
#include "../common/fman.h" |
||||
#include "t4rdb.h" |
||||
|
||||
void fdt_fixup_board_enet(void *fdt) |
||||
{ |
||||
return; |
||||
} |
||||
|
||||
int board_eth_init(bd_t *bis) |
||||
{ |
||||
#if defined(CONFIG_FMAN_ENET) |
||||
int i, interface; |
||||
struct memac_mdio_info dtsec_mdio_info; |
||||
struct memac_mdio_info tgec_mdio_info; |
||||
struct mii_dev *dev; |
||||
ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); |
||||
u32 srds_prtcl_s1, srds_prtcl_s2; |
||||
|
||||
srds_prtcl_s1 = in_be32(&gur->rcwsr[4]) & |
||||
FSL_CORENET2_RCWSR4_SRDS1_PRTCL; |
||||
srds_prtcl_s1 >>= FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT; |
||||
srds_prtcl_s2 = in_be32(&gur->rcwsr[4]) & |
||||
FSL_CORENET2_RCWSR4_SRDS2_PRTCL; |
||||
srds_prtcl_s2 >>= FSL_CORENET2_RCWSR4_SRDS2_PRTCL_SHIFT; |
||||
|
||||
dtsec_mdio_info.regs = |
||||
(struct memac_mdio_controller *)CONFIG_SYS_FM2_DTSEC_MDIO_ADDR; |
||||
|
||||
dtsec_mdio_info.name = DEFAULT_FM_MDIO_NAME; |
||||
|
||||
/* Register the 1G MDIO bus */ |
||||
fm_memac_mdio_init(bis, &dtsec_mdio_info); |
||||
|
||||
tgec_mdio_info.regs = |
||||
(struct memac_mdio_controller *)CONFIG_SYS_FM2_TGEC_MDIO_ADDR; |
||||
tgec_mdio_info.name = DEFAULT_FM_TGEC_MDIO_NAME; |
||||
|
||||
/* Register the 10G MDIO bus */ |
||||
fm_memac_mdio_init(bis, &tgec_mdio_info); |
||||
|
||||
if (srds_prtcl_s1 == 28) { |
||||
/* SGMII */ |
||||
fm_info_set_phy_address(FM1_DTSEC1, SGMII_PHY_ADDR1); |
||||
fm_info_set_phy_address(FM1_DTSEC2, SGMII_PHY_ADDR2); |
||||
fm_info_set_phy_address(FM1_DTSEC3, SGMII_PHY_ADDR3); |
||||
fm_info_set_phy_address(FM1_DTSEC4, SGMII_PHY_ADDR4); |
||||
} else { |
||||
puts("Invalid SerDes1 protocol for T4240RDB\n"); |
||||
} |
||||
|
||||
for (i = FM1_DTSEC1; i < FM1_DTSEC1 + CONFIG_SYS_NUM_FM1_DTSEC; i++) { |
||||
interface = fm_info_get_enet_if(i); |
||||
switch (interface) { |
||||
case PHY_INTERFACE_MODE_SGMII: |
||||
dev = miiphy_get_dev_by_name(DEFAULT_FM_MDIO_NAME); |
||||
fm_info_set_mdio(i, dev); |
||||
break; |
||||
default: |
||||
break; |
||||
} |
||||
} |
||||
|
||||
for (i = FM1_10GEC1; i < FM1_10GEC1 + CONFIG_SYS_NUM_FM1_10GEC; i++) { |
||||
switch (fm_info_get_enet_if(i)) { |
||||
case PHY_INTERFACE_MODE_XGMII: |
||||
dev = miiphy_get_dev_by_name(DEFAULT_FM_TGEC_MDIO_NAME); |
||||
fm_info_set_mdio(i, dev); |
||||
break; |
||||
default: |
||||
break; |
||||
} |
||||
} |
||||
|
||||
#if (CONFIG_SYS_NUM_FMAN == 2) |
||||
if (srds_prtcl_s2 == 56) { |
||||
/* SGMII && XFI */ |
||||
fm_info_set_phy_address(FM2_DTSEC1, SGMII_PHY_ADDR5); |
||||
fm_info_set_phy_address(FM2_DTSEC2, SGMII_PHY_ADDR6); |
||||
fm_info_set_phy_address(FM2_DTSEC3, SGMII_PHY_ADDR7); |
||||
fm_info_set_phy_address(FM2_DTSEC4, SGMII_PHY_ADDR8); |
||||
fm_info_set_phy_address(FM1_10GEC1, FM1_10GEC1_PHY_ADDR); |
||||
fm_info_set_phy_address(FM1_10GEC2, FM1_10GEC2_PHY_ADDR); |
||||
fm_info_set_phy_address(FM2_10GEC1, FM2_10GEC2_PHY_ADDR); |
||||
fm_info_set_phy_address(FM2_10GEC2, FM2_10GEC1_PHY_ADDR); |
||||
} else { |
||||
puts("Invalid SerDes2 protocol for T4240RDB\n"); |
||||
} |
||||
|
||||
for (i = FM2_DTSEC1; i < FM2_DTSEC1 + CONFIG_SYS_NUM_FM2_DTSEC; i++) { |
||||
interface = fm_info_get_enet_if(i); |
||||
switch (interface) { |
||||
case PHY_INTERFACE_MODE_SGMII: |
||||
dev = miiphy_get_dev_by_name(DEFAULT_FM_MDIO_NAME); |
||||
fm_info_set_mdio(i, dev); |
||||
break; |
||||
default: |
||||
break; |
||||
} |
||||
} |
||||
|
||||
for (i = FM2_10GEC1; i < FM2_10GEC1 + CONFIG_SYS_NUM_FM2_10GEC; i++) { |
||||
switch (fm_info_get_enet_if(i)) { |
||||
case PHY_INTERFACE_MODE_XGMII: |
||||
dev = miiphy_get_dev_by_name(DEFAULT_FM_TGEC_MDIO_NAME); |
||||
fm_info_set_mdio(i, dev); |
||||
break; |
||||
default: |
||||
break; |
||||
} |
||||
} |
||||
#endif /* CONFIG_SYS_NUM_FMAN */ |
||||
|
||||
cpu_eth_init(bis); |
||||
#endif /* CONFIG_FMAN_ENET */ |
||||
|
||||
return pci_eth_init(bis); |
||||
} |
||||
@ -0,0 +1,28 @@ |
||||
/*
|
||||
* Copyright 2014 Freescale Semiconductor, Inc. |
||||
* |
||||
* SPDX-License-Identifier: GPL-2.0+ |
||||
*/ |
||||
|
||||
#include <common.h> |
||||
#include <asm/fsl_law.h> |
||||
#include <asm/mmu.h> |
||||
|
||||
struct law_entry law_table[] = { |
||||
SET_LAW(CONFIG_SYS_FLASH_BASE_PHYS, LAW_SIZE_256M, LAW_TRGT_IF_IFC), |
||||
#ifdef CONFIG_SYS_BMAN_MEM_PHYS |
||||
SET_LAW(CONFIG_SYS_BMAN_MEM_PHYS, LAW_SIZE_32M, LAW_TRGT_IF_BMAN), |
||||
#endif |
||||
#ifdef CONFIG_SYS_QMAN_MEM_PHYS |
||||
SET_LAW(CONFIG_SYS_QMAN_MEM_PHYS, LAW_SIZE_32M, LAW_TRGT_IF_QMAN), |
||||
#endif |
||||
#ifdef CONFIG_SYS_DCSRBAR_PHYS |
||||
/* Limit DCSR to 32M to access NPC Trace Buffer */ |
||||
SET_LAW(CONFIG_SYS_DCSRBAR_PHYS, LAW_SIZE_32M, LAW_TRGT_IF_DCSR), |
||||
#endif |
||||
#ifdef CONFIG_SYS_NAND_BASE_PHYS |
||||
SET_LAW(CONFIG_SYS_NAND_BASE_PHYS, LAW_SIZE_64K, LAW_TRGT_IF_IFC), |
||||
#endif |
||||
}; |
||||
|
||||
int num_law_entries = ARRAY_SIZE(law_table); |
||||
Some files were not shown because too many files have changed in this diff Show More
Loading…
Reference in new issue