parent
b79a11cc2b
commit
0608e04da9
@ -0,0 +1,72 @@ |
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/*
|
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* (C) Copyright 2004 |
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* Klaus Heydeck, Kieback & Peter GmbH & Co KG, heydeck@kieback-peter.de. |
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* |
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* See file CREDITS for list of people who contributed to this |
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* project. |
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* |
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* This program is free software; you can redistribute it and/or |
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* modify it under the terms of the GNU General Public License as |
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* published by the Free Software Foundation; either version 2 of |
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* the License, or (at your option) any later version. |
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* |
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* This program is distributed in the hope that it will be useful, |
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* but WITHOUT ANY WARRANTY; without even the implied warranty of |
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
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* GNU General Public License for more details. |
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* |
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* You should have received a copy of the GNU General Public License |
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* along with this program; if not, write to the Free Software |
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
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* MA 02111-1307 USA |
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*/ |
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|
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#include <common.h> |
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#include <mpc8xx.h> |
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#include "kup.h" |
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int misc_init_f (void) |
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{ |
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volatile immap_t *immap = (immap_t *) CFG_IMMR; |
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volatile sysconf8xx_t *siu = &immap->im_siu_conf; |
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while (siu->sc_sipend & 0x20000000) { |
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/* printf("waiting for 5V VCC\n"); */ |
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; |
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} |
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/* RS232 / RS485 default is RS232 */ |
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immap->im_ioport.iop_padat &= ~(PA_RS485); |
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immap->im_ioport.iop_papar &= ~(PA_RS485); |
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immap->im_ioport.iop_paodr &= ~(PA_RS485); |
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immap->im_ioport.iop_padir |= (PA_RS485); |
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return (0); |
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} |
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|
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#ifdef CONFIG_IDE_LED |
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void ide_led (uchar led, uchar status) |
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{ |
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volatile immap_t *immap = (immap_t *) CFG_IMMR; |
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/* We have one led for both pcmcia slots */ |
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if (status) { /* led on */ |
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immap->im_ioport.iop_padat &= ~(PA_LED_YELLOW); |
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} else { |
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immap->im_ioport.iop_padat |= (PA_LED_YELLOW); |
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} |
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} |
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#endif |
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void poweron_key (void) |
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{ |
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volatile immap_t *immap = (immap_t *) CFG_IMMR; |
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immap->im_ioport.iop_pcpar &= ~(PC_SWITCH1); |
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immap->im_ioport.iop_pcdir &= ~(PC_SWITCH1); |
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if (immap->im_ioport.iop_pcdat & (PC_SWITCH1)) |
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setenv ("key1", "off"); |
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else |
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setenv ("key1", "on"); |
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} |
@ -0,0 +1,44 @@ |
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/*
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* (C) Copyright 2004 |
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* Klaus Heydeck, Kieback & Peter GmbH & Co KG, heydeck@kieback-peter.de. |
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* |
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* See file CREDITS for list of people who contributed to this |
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* project. |
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* |
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* This program is free software; you can redistribute it and/or |
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* modify it under the terms of the GNU General Public License as |
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* published by the Free Software Foundation; either version 2 of |
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* the License, or (at your option) any later version. |
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* |
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* This program is distributed in the hope that it will be useful, |
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* but WITHOUT ANY WARRANTY; without even the implied warranty of |
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
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* GNU General Public License for more details. |
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* |
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* You should have received a copy of the GNU General Public License |
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* along with this program; if not, write to the Free Software |
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
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* MA 02111-1307 USA |
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*/ |
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#ifndef __KUP_H |
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#define __KUP_H |
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#define PA_8 0x0080 |
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#define PA_11 0x0010 |
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#define PA_12 0x0008 |
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#define PB_14 0x00020000 |
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#define PB_17 0x00004000 |
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#define PC_9 0x0040 |
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#define PA_RS485 PA_11 /* SCC1: 0=RS232 1=RS485 */ |
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#define PA_LED_YELLOW PA_8 |
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#define BP_USB_VCC PB_14 /* VCC for USB devices 0=vcc on, 1=vcc off*/ |
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#define PB_LCD_PWM PB_17 /* PB 17 */ |
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#define PC_SWITCH1 PC_9 /* Reboot switch */ |
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extern void poweron_key (void); |
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#endif /* __KUP_H */ |
@ -0,0 +1,40 @@ |
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#
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# (C) Copyright 2000-2004
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# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
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#
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# See file CREDITS for list of people who contributed to this
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# project.
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#
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# This program is free software; you can redistribute it and/or
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# modify it under the terms of the GNU General Public License as
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# published by the Free Software Foundation; either version 2 of
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# the License, or (at your option) any later version.
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#
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# This program is distributed in the hope that it will be useful,
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# but WITHOUT ANY WARRANTY; without even the implied warranty of
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# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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# GNU General Public License for more details.
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#
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# You should have received a copy of the GNU General Public License
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# along with this program; if not, write to the Free Software
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# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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# MA 02111-1307 USA
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#
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include $(TOPDIR)/config.mk |
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LIB = lib$(BOARD).a
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OBJS = $(BOARD).o ../common/flash.o ../common/kup.o
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$(LIB): .depend $(OBJS) |
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$(AR) crv $@ $(OBJS)
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#########################################################################
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.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) |
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$(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
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sinclude .depend |
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#########################################################################
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@ -1,5 +1,5 @@ |
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#
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# (C) Copyright 2000-2002
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# (C) Copyright 2000-2004
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# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
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#
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# See file CREDITS for list of people who contributed to this
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@ -0,0 +1,174 @@ |
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/*---------------------------------------------------------------------------- */ |
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/* */ |
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/* File generated by S1D13706CFG.EXE */ |
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/* */ |
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/* Copyright (c) 2000,2001 Epson Research and Development, Inc. */ |
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/* All rights reserved. */ |
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/* */ |
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/*---------------------------------------------------------------------------- */ |
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/* Panel: 320x240x8bpp 70Hz Color Single STN 8-bit (PCLK=6.250MHz) (Format 2) */ |
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#define S1D_DISPLAY_WIDTH 320 |
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#define S1D_DISPLAY_HEIGHT 240 |
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#define S1D_DISPLAY_BPP 8 |
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#define S1D_DISPLAY_SCANLINE_BYTES 320 |
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#define S1D_PHYSICAL_VMEM_ADDR 0x800A0000L |
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#define S1D_PHYSICAL_VMEM_SIZE 0x14000L |
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#define S1D_PHYSICAL_REG_ADDR 0x80080000L |
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#define S1D_PHYSICAL_REG_SIZE 0x100 |
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#define S1D_DISPLAY_PCLK 6250 |
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#define S1D_PALETTE_SIZE 256 |
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#define S1D_REGDELAYOFF 0xFFFE |
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#define S1D_REGDELAYON 0xFFFF |
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#define S1D_WRITE_PALETTE(p,i,r,g,b) \ |
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{ \
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((volatile S1D_VALUE*)(p))[0x0A/sizeof(S1D_VALUE)] = (S1D_VALUE)((r)>>4); \
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((volatile S1D_VALUE*)(p))[0x09/sizeof(S1D_VALUE)] = (S1D_VALUE)((g)>>4); \
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((volatile S1D_VALUE*)(p))[0x08/sizeof(S1D_VALUE)] = (S1D_VALUE)((b)>>4); \
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((volatile S1D_VALUE*)(p))[0x0B/sizeof(S1D_VALUE)] = (S1D_VALUE)(i); \
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} |
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#define S1D_READ_PALETTE(p,i,r,g,b) \ |
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{ \
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((volatile S1D_VALUE*)(p))[0x0F/sizeof(S1D_VALUE)] = (S1D_VALUE)(i); \
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r = ((volatile S1D_VALUE*)(p))[0x0E/sizeof(S1D_VALUE)]; \
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g = ((volatile S1D_VALUE*)(p))[0x0D/sizeof(S1D_VALUE)]; \
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b = ((volatile S1D_VALUE*)(p))[0x0C/sizeof(S1D_VALUE)]; \
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} |
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typedef unsigned short S1D_INDEX; |
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typedef unsigned char S1D_VALUE; |
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typedef struct |
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{ |
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S1D_INDEX Index; |
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S1D_VALUE Value; |
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} S1D_REGS; |
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static S1D_REGS aS1DRegs_prelimn[] = |
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{ |
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{0x10,0x00}, /* PANEL Type Register */ |
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{0xA8,0x00}, /* GPIO Config Register 0 */ |
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{0xA9,0x80}, /* GPIO Config Register 1 */ |
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}; |
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static S1D_REGS aS1DRegs_stn[] = |
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{ |
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{0x04,0x10}, /* BUSCLK MEMCLK Config Register */ |
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{0x10,0xD0}, /* PANEL Type Register */ |
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{0x11,0x00}, /* MOD Rate Register */ |
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{0x14,0x27}, /* Horizontal Display Period Register */ |
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{0x16,0x00}, /* Horizontal Display Period Start Pos Register 0 */ |
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{0x17,0x00}, /* Horizontal Display Period Start Pos Register 1 */ |
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{0x18,0xF0}, /* Vertical Total Register 0 */ |
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{0x19,0x00}, /* Vertical Total Register 1 */ |
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{0x1C,0xEF}, /* Vertical Display Period Register 0 */ |
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{0x1D,0x00}, /* Vertical Display Period Register 1 */ |
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{0x1E,0x00}, /* Vertical Display Period Start Pos Register 0 */ |
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{0x1F,0x00}, /* Vertical Display Period Start Pos Register 1 */ |
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{0x20,0x87}, /* Horizontal Sync Pulse Width Register */ |
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{0x22,0x00}, /* Horizontal Sync Pulse Start Pos Register 0 */ |
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{0x23,0x00}, /* Horizontal Sync Pulse Start Pos Register 1 */ |
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{0x24,0x80}, /* Vertical Sync Pulse Width Register */ |
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{0x26,0x01}, /* Vertical Sync Pulse Start Pos Register 0 */ |
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{0x27,0x00}, /* Vertical Sync Pulse Start Pos Register 1 */ |
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{0x70,0x83}, /* Display Mode Register */ |
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{0x71,0x00}, /* Special Effects Register */ |
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{0x74,0x00}, /* Main Window Display Start Address Register 0 */ |
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{0x75,0x00}, /* Main Window Display Start Address Register 1 */ |
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{0x76,0x00}, /* Main Window Display Start Address Register 2 */ |
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{0x78,0x50}, /* Main Window Address Offset Register 0 */ |
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{0x79,0x00}, /* Main Window Address Offset Register 1 */ |
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{0x7C,0x00}, /* Sub Window Display Start Address Register 0 */ |
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{0x7D,0x00}, /* Sub Window Display Start Address Register 1 */ |
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{0x7E,0x00}, /* Sub Window Display Start Address Register 2 */ |
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{0x80,0x50}, /* Sub Window Address Offset Register 0 */ |
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{0x81,0x00}, /* Sub Window Address Offset Register 1 */ |
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{0x84,0x00}, /* Sub Window X Start Pos Register 0 */ |
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{0x85,0x00}, /* Sub Window X Start Pos Register 1 */ |
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{0x88,0x00}, /* Sub Window Y Start Pos Register 0 */ |
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{0x89,0x00}, /* Sub Window Y Start Pos Register 1 */ |
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{0x8C,0x4F}, /* Sub Window X End Pos Register 0 */ |
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{0x8D,0x00}, /* Sub Window X End Pos Register 1 */ |
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{0x90,0xEF}, /* Sub Window Y End Pos Register 0 */ |
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{0x91,0x00}, /* Sub Window Y End Pos Register 1 */ |
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{0xA0,0x00}, /* Power Save Config Register */ |
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{0xA1,0x00}, /* CPU Access Control Register */ |
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{0xA2,0x00}, /* Software Reset Register */ |
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{0xA3,0x00}, /* BIG Endian Support Register */ |
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{0xA4,0x00}, /* Scratch Pad Register 0 */ |
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{0xA5,0x00}, /* Scratch Pad Register 1 */ |
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{0xA8,0x01}, /* GPIO Config Register 0 */ |
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{0xA9,0x80}, /* GPIO Config Register 1 */ |
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{0xAC,0x01}, /* GPIO Status Control Register 0 */ |
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{0xAD,0x00}, /* GPIO Status Control Register 1 */ |
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{0xB0,0x10}, /* PWM CV Clock Control Register */ |
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{0xB1,0x80}, /* PWM CV Clock Config Register */ |
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{0xB2,0x00}, /* CV Clock Burst Length Register */ |
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{0xAD,0x80}, /* reset seq */ |
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{0x70,0x03}, |
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}; |
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static S1D_REGS aS1DRegs_tft[] = |
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{ |
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{0x04,0x10}, /* BUSCLK MEMCLK Config Register */ |
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{0x05,0x42}, /* PCLK Config Register */ |
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{0x10,0x61}, /* PANEL Type Register */ |
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{0x11,0x00}, /* MOD Rate Register */ |
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{0x12,0x30}, /* Horizontal Total Register */ |
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{0x14,0x27}, /* Horizontal Display Period Register */ |
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{0x16,0x11}, /* Horizontal Display Period Start Pos Register 0 */ |
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{0x17,0x00}, /* Horizontal Display Period Start Pos Register 1 */ |
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{0x18,0xFA}, /* Vertical Total Register 0 */ |
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{0x19,0x00}, /* Vertical Total Register 1 */ |
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{0x1C,0xEF}, /* Vertical Display Period Register 0 */ |
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{0x1D,0x00}, /* Vertical Display Period Register 1 */ |
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{0x1E,0x00}, /* Vertical Display Period Start Pos Register 0 */ |
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{0x1F,0x00}, /* Vertical Display Period Start Pos Register 1 */ |
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{0x20,0x07}, /* Horizontal Sync Pulse Width Register */ |
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{0x22,0x00}, /* Horizontal Sync Pulse Start Pos Register 0 */ |
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{0x23,0x00}, /* Horizontal Sync Pulse Start Pos Register 1 */ |
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{0x24,0x00}, /* Vertical Sync Pulse Width Register */ |
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{0x26,0x00}, /* Vertical Sync Pulse Start Pos Register 0 */ |
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{0x27,0x00}, /* Vertical Sync Pulse Start Pos Register 1 */ |
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{0x70,0x03}, /* Display Mode Register */ |
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{0x71,0x00}, /* Special Effects Register */ |
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{0x74,0x00}, /* Main Window Display Start Address Register 0 */ |
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{0x75,0x00}, /* Main Window Display Start Address Register 1 */ |
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{0x76,0x00}, /* Main Window Display Start Address Register 2 */ |
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{0x78,0x50}, /* Main Window Address Offset Register 0 */ |
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{0x79,0x00}, /* Main Window Address Offset Register 1 */ |
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{0x7C,0x00}, /* Sub Window Display Start Address Register 0 */ |
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{0x7D,0x00}, /* Sub Window Display Start Address Register 1 */ |
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{0x7E,0x00}, /* Sub Window Display Start Address Register 2 */ |
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{0x80,0x50}, /* Sub Window Address Offset Register 0 */ |
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{0x81,0x00}, /* Sub Window Address Offset Register 1 */ |
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{0x84,0x00}, /* Sub Window X Start Pos Register 0 */ |
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{0x85,0x00}, /* Sub Window X Start Pos Register 1 */ |
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{0x88,0x00}, /* Sub Window Y Start Pos Register 0 */ |
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{0x89,0x00}, /* Sub Window Y Start Pos Register 1 */ |
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{0x8C,0x4F}, /* Sub Window X End Pos Register 0 */ |
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{0x8D,0x00}, /* Sub Window X End Pos Register 1 */ |
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{0x90,0xEF}, /* Sub Window Y End Pos Register 0 */ |
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{0x91,0x00}, /* Sub Window Y End Pos Register 1 */ |
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{0xA0,0x00}, /* Power Save Config Register */ |
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{0xA1,0x00}, /* CPU Access Control Register */ |
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{0xA2,0x00}, /* Software Reset Register */ |
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{0xA3,0x00}, /* BIG Endian Support Register */ |
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{0xA4,0x00}, /* Scratch Pad Register 0 */ |
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{0xA5,0x00}, /* Scratch Pad Register 1 */ |
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{0xA8,0x01}, /* GPIO Config Register 0 */ |
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{0xA9,0x80}, /* GPIO Config Register 1 */ |
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{0xAC,0x01}, /* GPIO Status Control Register 0 */ |
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{0xAD,0x00}, /* GPIO Status Control Register 1 */ |
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{0xB0,0x10}, /* PWM CV Clock Control Register */ |
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{0xB1,0x80}, /* PWM CV Clock Config Register */ |
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{0xB2,0x00}, /* CV Clock Burst Length Register */ |
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{0xAD,0x80}, /* reset seq */ |
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{0x70,0x03}, |
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}; |
@ -1,5 +1,5 @@ |
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/* |
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* (C) Copyright 2000-2002 |
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* (C) Copyright 2000-2004 |
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* Wolfgang Denk, DENX Software Engineering, wd@denx.de. |
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* |
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* See file CREDITS for list of people who contributed to this |
@ -0,0 +1,40 @@ |
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#
|
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# (C) Copyright 2000-2004
|
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# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
|
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#
|
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# See file CREDITS for list of people who contributed to this
|
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# project.
|
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#
|
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# This program is free software; you can redistribute it and/or
|
||||
# modify it under the terms of the GNU General Public License as
|
||||
# published by the Free Software Foundation; either version 2 of
|
||||
# the License, or (at your option) any later version.
|
||||
#
|
||||
# This program is distributed in the hope that it will be useful,
|
||||
# but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
# GNU General Public License for more details.
|
||||
#
|
||||
# You should have received a copy of the GNU General Public License
|
||||
# along with this program; if not, write to the Free Software
|
||||
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
# MA 02111-1307 USA
|
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#
|
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|
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include $(TOPDIR)/config.mk |
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|
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LIB = lib$(BOARD).a
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|
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OBJS = $(BOARD).o ../common/flash.o ../common/kup.o usb.o
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|
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$(LIB): .depend $(OBJS) |
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$(AR) crv $@ $(OBJS)
|
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|
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#########################################################################
|
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|
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.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) |
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$(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
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|
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sinclude .depend |
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|
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#########################################################################
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@ -0,0 +1,28 @@ |
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#
|
||||
# (C) Copyright 2000-2004
|
||||
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
|
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#
|
||||
# See file CREDITS for list of people who contributed to this
|
||||
# project.
|
||||
#
|
||||
# This program is free software; you can redistribute it and/or
|
||||
# modify it under the terms of the GNU General Public License as
|
||||
# published by the Free Software Foundation; either version 2 of
|
||||
# the License, or (at your option) any later version.
|
||||
#
|
||||
# This program is distributed in the hope that it will be useful,
|
||||
# but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
# GNU General Public License for more details.
|
||||
#
|
||||
# You should have received a copy of the GNU General Public License
|
||||
# along with this program; if not, write to the Free Software
|
||||
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
# MA 02111-1307 USA
|
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#
|
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|
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#
|
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# KUP4X board
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#
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|
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TEXT_BASE = 0x40000000
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@ -0,0 +1,311 @@ |
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/*
|
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* (C) Copyright 2000-2004 |
||||
* Wolfgang Denk, DENX Software Engineering, wd@denx.de. |
||||
* Klaus Heydeck, Kieback & Peter GmbH & Co KG, heydeck@kieback-peter.de |
||||
* |
||||
* See file CREDITS for list of people who contributed to this |
||||
* project. |
||||
* |
||||
* This program is free software; you can redistribute it and/or |
||||
* modify it under the terms of the GNU General Public License as |
||||
* published by the Free Software Foundation; either version 2 of |
||||
* the License, or (at your option) any later version. |
||||
* |
||||
* This program is distributed in the hope that it will be useful, |
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of |
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
||||
* GNU General Public License for more details. |
||||
* |
||||
* You should have received a copy of the GNU General Public License |
||||
* along with this program; if not, write to the Free Software |
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
||||
* MA 02111-1307 USA |
||||
*/ |
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|
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#include <common.h> |
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#include <mpc8xx.h> |
||||
#include "../common/kup.h" |
||||
#ifdef CONFIG_KUP4K_LOGO |
||||
/* #include "s1d13706.h" */ |
||||
#endif |
||||
|
||||
#define KUP4X_USB |
||||
|
||||
|
||||
typedef struct { |
||||
volatile unsigned char *VmemAddr; |
||||
volatile unsigned char *RegAddr; |
||||
} FB_INFO_S1D13xxx; |
||||
|
||||
/* ------------------------------------------------------------------------- */ |
||||
|
||||
int usb_init_kup4x (void); |
||||
|
||||
|
||||
#ifdef CONFIG_KUP4K_LOGO |
||||
void lcd_logo (bd_t * bd); |
||||
#endif |
||||
|
||||
/* ------------------------------------------------------------------------- */ |
||||
|
||||
#define _NOT_USED_ 0xFFFFFFFF |
||||
|
||||
const uint sdram_table[] = { |
||||
/*
|
||||
* Single Read. (Offset 0 in UPMA RAM) |
||||
*/ |
||||
0x1F07FC04, 0xEEAEFC04, 0x11ADFC04, 0xEFBBBC00, |
||||
0x1FF77C47, /* last */ |
||||
|
||||
/*
|
||||
* SDRAM Initialization (offset 5 in UPMA RAM) |
||||
* |
||||
* This is no UPM entry point. The following definition uses |
||||
* the remaining space to establish an initialization |
||||
* sequence, which is executed by a RUN command. |
||||
* |
||||
*/ |
||||
0x1FF77C35, 0xEFEABC34, 0x1FB57C35, /* last */ |
||||
|
||||
/*
|
||||
* Burst Read. (Offset 8 in UPMA RAM) |
||||
*/ |
||||
0x1F07FC04, 0xEEAEFC04, 0x10ADFC04, 0xF0AFFC00, |
||||
0xF0AFFC00, 0xF1AFFC00, 0xEFBBBC00, 0x1FF77C47, /* last */ |
||||
_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, |
||||
_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, |
||||
|
||||
/*
|
||||
* Single Write. (Offset 18 in UPMA RAM) |
||||
*/ |
||||
0x1F27FC04, 0xEEAEBC00, 0x01B93C04, 0x1FF77C47, /* last */ |
||||
_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, |
||||
|
||||
/*
|
||||
* Burst Write. (Offset 20 in UPMA RAM) |
||||
*/ |
||||
0x1F07FC04, 0xEEAEBC00, 0x10AD7C00, 0xF0AFFC00, |
||||
0xF0AFFC00, 0xE1BBBC04, 0x1FF77C47, /* last */ |
||||
_NOT_USED_, |
||||
_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, |
||||
_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, |
||||
|
||||
/*
|
||||
* Refresh (Offset 30 in UPMA RAM) |
||||
*/ |
||||
0x1FF5FC84, 0xFFFFFC04, 0xFFFFFC04, 0xFFFFFC04, |
||||
0xFFFFFC84, 0xFFFFFC07, /* last */ |
||||
_NOT_USED_, _NOT_USED_, |
||||
_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, |
||||
|
||||
/*
|
||||
* Exception. (Offset 3c in UPMA RAM) |
||||
*/ |
||||
0x7FFFFC07, /* last */ |
||||
_NOT_USED_, _NOT_USED_, _NOT_USED_, |
||||
}; |
||||
|
||||
/* ------------------------------------------------------------------------- */ |
||||
|
||||
/*
|
||||
* Check Board Identity: |
||||
*/ |
||||
|
||||
int checkboard (void) |
||||
{ |
||||
volatile immap_t *immap = (immap_t *) CFG_IMMR; |
||||
volatile memctl8xx_t *memctl = &immap->im_memctl; |
||||
uchar *latch, rev, mod; |
||||
|
||||
/*
|
||||
* Init ChipSelect #4 (CAN + HW-Latch) |
||||
*/ |
||||
memctl->memc_or4 = 0xFFFF8926; |
||||
memctl->memc_br4 = 0x90000401; |
||||
|
||||
latch = (uchar *) 0x90000200; |
||||
rev = (*latch & 0xF8) >> 3; |
||||
mod = (*latch & 0x03); |
||||
printf ("Board: KUP4X Rev %d.%d SN: %s\n", rev, mod, |
||||
getenv ("ethaddr")); |
||||
return (0); |
||||
} |
||||
|
||||
/* ------------------------------------------------------------------------- */ |
||||
|
||||
long int initdram (int board_type) |
||||
{ |
||||
volatile immap_t *immap = (immap_t *) CFG_IMMR; |
||||
volatile memctl8xx_t *memctl = &immap->im_memctl; |
||||
long int size_b0 = 0; |
||||
long int size_b1 = 0; |
||||
long int size_b2 = 0; |
||||
long int size_b3 = 0; |
||||
|
||||
upmconfig (UPMA, (uint *) sdram_table, |
||||
sizeof (sdram_table) / sizeof (uint)); |
||||
/*
|
||||
* Preliminary prescaler for refresh (depends on number of |
||||
* banks): This value is selected for four cycles every 62.4 us |
||||
* with two SDRAM banks or four cycles every 31.2 us with one |
||||
* bank. It will be adjusted after memory sizing. |
||||
*/ |
||||
memctl->memc_mptpr = CFG_MPTPR; |
||||
|
||||
memctl->memc_mar = 0x00000088; |
||||
|
||||
/*
|
||||
* Map controller banks 1 and 2 to the SDRAM banks 2 and 3 at |
||||
* preliminary addresses - these have to be modified after the |
||||
* SDRAM size has been determined. |
||||
*/ |
||||
/* memctl->memc_or1 = CFG_OR1_PRELIM; */ |
||||
/* memctl->memc_br1 = CFG_BR1_PRELIM; */ |
||||
|
||||
/* memctl->memc_or2 = CFG_OR2_PRELIM; */ |
||||
/* memctl->memc_br2 = CFG_BR2_PRELIM; */ |
||||
|
||||
memctl->memc_mamr = CFG_MAMR & (~(MAMR_PTAE)); /* no refresh yet */ |
||||
|
||||
udelay (200); |
||||
|
||||
/* perform SDRAM initializsation sequence */ |
||||
|
||||
memctl->memc_mcr = 0x80002105; /* SDRAM bank 0 */ |
||||
udelay (1); |
||||
memctl->memc_mcr = 0x80002830; /* SDRAM bank 0 - execute twice */ |
||||
udelay (1); |
||||
memctl->memc_mcr = 0x80002106; /* SDRAM bank 0 - RUN MRS Pattern from loc 6 */ |
||||
udelay (1); |
||||
|
||||
memctl->memc_mcr = 0x80004105; /* SDRAM bank 1 */ |
||||
udelay (1); |
||||
memctl->memc_mcr = 0x80004830; /* SDRAM bank 1 - execute twice */ |
||||
udelay (1); |
||||
memctl->memc_mcr = 0x80004106; /* SDRAM bank 1 - RUN MRS Pattern from loc 6 */ |
||||
udelay (1); |
||||
|
||||
memctl->memc_mcr = 0x80006105; /* SDRAM bank 2 */ |
||||
udelay (1); |
||||
memctl->memc_mcr = 0x80006830; /* SDRAM bank 2 - execute twice */ |
||||
udelay (1); |
||||
memctl->memc_mcr = 0x80006106; /* SDRAM bank 2 - RUN MRS Pattern from loc 6 */ |
||||
udelay (1); |
||||
|
||||
memctl->memc_mcr = 0x8000C105; /* SDRAM bank 2 */ |
||||
udelay (1); |
||||
memctl->memc_mcr = 0x8000C830; /* SDRAM bank 2 - execute twice */ |
||||
udelay (1); |
||||
memctl->memc_mcr = 0x8000C106; /* SDRAM bank 2 - RUN MRS Pattern from loc 6 */ |
||||
udelay (1); |
||||
|
||||
memctl->memc_mamr |= MAMR_PTAE; /* enable refresh */ |
||||
udelay (1000); |
||||
#if 0 /* 4 x 8MB */
|
||||
size_b0 = 0x00800000; |
||||
size_b1 = 0x00800000; |
||||
size_b2 = 0x00800000; |
||||
size_b3 = 0x00800000; |
||||
memctl->memc_mptpr = CFG_MPTPR; |
||||
udelay (1000); |
||||
memctl->memc_or1 = 0xFF800A00; |
||||
memctl->memc_br1 = 0x00000081; |
||||
memctl->memc_or2 = 0xFF000A00; |
||||
memctl->memc_br2 = 0x00800081; |
||||
memctl->memc_or3 = 0xFE000A00; |
||||
memctl->memc_br3 = 0x01000081; |
||||
memctl->memc_or6 = 0xFE000A00; |
||||
memctl->memc_br6 = 0x01800081; |
||||
#else /* 4 x 16 MB */ |
||||
size_b0 = 0x01000000; |
||||
size_b1 = 0x01000000; |
||||
size_b2 = 0x01000000; |
||||
size_b3 = 0x01000000; |
||||
memctl->memc_mptpr = CFG_MPTPR; |
||||
udelay (1000); |
||||
memctl->memc_or1 = 0xFF000A00; |
||||
memctl->memc_br1 = 0x00000081; |
||||
memctl->memc_or2 = 0xFE000A00; |
||||
memctl->memc_br2 = 0x01000081; |
||||
memctl->memc_or3 = 0xFD000A00; |
||||
memctl->memc_br3 = 0x02000081; |
||||
memctl->memc_or6 = 0xFC000A00; |
||||
memctl->memc_br6 = 0x03000081; |
||||
#endif |
||||
udelay (10000); |
||||
|
||||
return (size_b0 + size_b1 + size_b2 + size_b3); |
||||
} |
||||
|
||||
/* ------------------------------------------------------------------------- */ |
||||
|
||||
/*
|
||||
* Check memory range for valid RAM. A simple memory test determines |
||||
* the actually available RAM size between addresses `base' and |
||||
* `base + maxsize'. Some (not all) hardware errors are detected: |
||||
* - short between address lines |
||||
* - short between data lines |
||||
*/ |
||||
#if 0 |
||||
static long int dram_size (long int mamr_value, long int *base, |
||||
long int maxsize) |
||||
{ |
||||
volatile immap_t *immap = (immap_t *) CFG_IMMR; |
||||
volatile memctl8xx_t *memctl = &immap->im_memctl; |
||||
volatile long int *addr; |
||||
ulong cnt, val; |
||||
ulong save[32]; /* to make test non-destructive */ |
||||
unsigned char i = 0; |
||||
|
||||
memctl->memc_mamr = mamr_value; |
||||
|
||||
for (cnt = maxsize / sizeof (long); cnt > 0; cnt >>= 1) { |
||||
addr = base + cnt; /* pointer arith! */ |
||||
|
||||
save[i++] = *addr; |
||||
*addr = ~cnt; |
||||
} |
||||
|
||||
/* write 0 to base address */ |
||||
addr = base; |
||||
save[i] = *addr; |
||||
*addr = 0; |
||||
|
||||
/* check at base address */ |
||||
if ((val = *addr) != 0) { |
||||
*addr = save[i]; |
||||
return (0); |
||||
} |
||||
|
||||
for (cnt = 1; cnt <= maxsize / sizeof (long); cnt <<= 1) { |
||||
addr = base + cnt; /* pointer arith! */ |
||||
|
||||
val = *addr; |
||||
*addr = save[--i]; |
||||
|
||||
if (val != (~cnt)) { |
||||
return (cnt * sizeof (long)); |
||||
} |
||||
} |
||||
return (maxsize); |
||||
} |
||||
#endif |
||||
|
||||
int misc_init_r (void) |
||||
{ |
||||
volatile immap_t *immap = (immap_t *) CFG_IMMR; |
||||
|
||||
#ifdef CONFIG_IDE_LED |
||||
/* Configure PA8 as output port */ |
||||
immap->im_ioport.iop_padir |= 0x80; |
||||
immap->im_ioport.iop_paodr |= 0x80; |
||||
immap->im_ioport.iop_papar &= ~0x80; |
||||
immap->im_ioport.iop_padat |= 0x80; /* turn it off */ |
||||
#endif |
||||
#ifdef KUP4X_USB |
||||
usb_init_kup4x (); |
||||
#endif |
||||
setenv ("hw", "4x"); |
||||
poweron_key (); |
||||
return (0); |
||||
} |
@ -0,0 +1,141 @@ |
||||
/* |
||||
* (C) Copyright 2000-2004 |
||||
* Wolfgang Denk, DENX Software Engineering, wd@denx.de. |
||||
* |
||||
* See file CREDITS for list of people who contributed to this |
||||
* project. |
||||
* |
||||
* This program is free software; you can redistribute it and/or |
||||
* modify it under the terms of the GNU General Public License as |
||||
* published by the Free Software Foundation; either version 2 of |
||||
* the License, or (at your option) any later version. |
||||
* |
||||
* This program is distributed in the hope that it will be useful, |
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of |
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
||||
* GNU General Public License for more details. |
||||
* |
||||
* You should have received a copy of the GNU General Public License |
||||
* along with this program; if not, write to the Free Software |
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
||||
* MA 02111-1307 USA |
||||
*/ |
||||
|
||||
OUTPUT_ARCH(powerpc) |
||||
SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib); |
||||
/* Do we need any of these for elf? |
||||
__DYNAMIC = 0; */ |
||||
SECTIONS |
||||
{ |
||||
/* Read-only sections, merged into text segment: */ |
||||
. = + SIZEOF_HEADERS; |
||||
.interp : { *(.interp) } |
||||
.hash : { *(.hash) } |
||||
.dynsym : { *(.dynsym) } |
||||
.dynstr : { *(.dynstr) } |
||||
.rel.text : { *(.rel.text) } |
||||
.rela.text : { *(.rela.text) } |
||||
.rel.data : { *(.rel.data) } |
||||
.rela.data : { *(.rela.data) } |
||||
.rel.rodata : { *(.rel.rodata) } |
||||
.rela.rodata : { *(.rela.rodata) } |
||||
.rel.got : { *(.rel.got) } |
||||
.rela.got : { *(.rela.got) } |
||||
.rel.ctors : { *(.rel.ctors) } |
||||
.rela.ctors : { *(.rela.ctors) } |
||||
.rel.dtors : { *(.rel.dtors) } |
||||
.rela.dtors : { *(.rela.dtors) } |
||||
.rel.bss : { *(.rel.bss) } |
||||
.rela.bss : { *(.rela.bss) } |
||||
.rel.plt : { *(.rel.plt) } |
||||
.rela.plt : { *(.rela.plt) } |
||||
.init : { *(.init) } |
||||
.plt : { *(.plt) } |
||||
.text : |
||||
{ |
||||
/* WARNING - the following is hand-optimized to fit within */ |
||||
/* the sector layout of our flash chips! XXX FIXME XXX */ |
||||
|
||||
cpu/mpc8xx/start.o (.text) |
||||
/* |
||||
cpu/mpc8xx/start.o (.text) |
||||
common/dlmalloc.o (.text) |
||||
lib_ppc/ppcstring.o (.text) |
||||
lib_generic/vsprintf.o (.text) |
||||
lib_generic/crc32.o (.text) |
||||
lib_generic/zlib.o (.text) |
||||
|
||||
. = env_offset; |
||||
common/environment.o(.text) |
||||
*/ |
||||
|
||||
*(.text) |
||||
*(.fixup) |
||||
*(.got1) |
||||
} |
||||
_etext = .; |
||||
PROVIDE (etext = .); |
||||
.rodata : |
||||
{ |
||||
*(.rodata) |
||||
*(.rodata1) |
||||
*(.rodata.str1.4) |
||||
} |
||||
.fini : { *(.fini) } =0 |
||||
.ctors : { *(.ctors) } |
||||
.dtors : { *(.dtors) } |
||||
|
||||
/* Read-write section, merged into data segment: */ |
||||
. = (. + 0x00FF) & 0xFFFFFF00; |
||||
_erotext = .; |
||||
PROVIDE (erotext = .); |
||||
.reloc : |
||||
{ |
||||
*(.got) |
||||
_GOT2_TABLE_ = .; |
||||
*(.got2) |
||||
_FIXUP_TABLE_ = .; |
||||
*(.fixup) |
||||
} |
||||
__got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2; |
||||
__fixup_entries = (. - _FIXUP_TABLE_)>>2; |
||||
|
||||
.data : |
||||
{ |
||||
*(.data) |
||||
*(.data1) |
||||
*(.sdata) |
||||
*(.sdata2) |
||||
*(.dynamic) |
||||
CONSTRUCTORS |
||||
} |
||||
_edata = .; |
||||
PROVIDE (edata = .); |
||||
|
||||
__u_boot_cmd_start = .; |
||||
.u_boot_cmd : { *(.u_boot_cmd) } |
||||
__u_boot_cmd_end = .; |
||||
|
||||
|
||||
__start___ex_table = .; |
||||
__ex_table : { *(__ex_table) } |
||||
__stop___ex_table = .; |
||||
|
||||
. = ALIGN(256); |
||||
__init_begin = .; |
||||
.text.init : { *(.text.init) } |
||||
.data.init : { *(.data.init) } |
||||
. = ALIGN(256); |
||||
__init_end = .; |
||||
|
||||
__bss_start = .; |
||||
.bss : |
||||
{ |
||||
*(.sbss) *(.scommon) |
||||
*(.dynbss) |
||||
*(.bss) |
||||
*(COMMON) |
||||
} |
||||
_end = . ; |
||||
PROVIDE (end = .); |
||||
} |
@ -0,0 +1,135 @@ |
||||
/* |
||||
* (C) Copyright 2000-2004 |
||||
* Wolfgang Denk, DENX Software Engineering, wd@denx.de. |
||||
* |
||||
* See file CREDITS for list of people who contributed to this |
||||
* project. |
||||
* |
||||
* This program is free software; you can redistribute it and/or |
||||
* modify it under the terms of the GNU General Public License as |
||||
* published by the Free Software Foundation; either version 2 of |
||||
* the License, or (at your option) any later version. |
||||
* |
||||
* This program is distributed in the hope that it will be useful, |
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of |
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
||||
* GNU General Public License for more details. |
||||
* |
||||
* You should have received a copy of the GNU General Public License |
||||
* along with this program; if not, write to the Free Software |
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
||||
* MA 02111-1307 USA |
||||
*/ |
||||
|
||||
OUTPUT_ARCH(powerpc) |
||||
SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib); |
||||
/* Do we need any of these for elf? |
||||
__DYNAMIC = 0; */ |
||||
SECTIONS |
||||
{ |
||||
/* Read-only sections, merged into text segment: */ |
||||
. = + SIZEOF_HEADERS; |
||||
.interp : { *(.interp) } |
||||
.hash : { *(.hash) } |
||||
.dynsym : { *(.dynsym) } |
||||
.dynstr : { *(.dynstr) } |
||||
.rel.text : { *(.rel.text) } |
||||
.rela.text : { *(.rela.text) } |
||||
.rel.data : { *(.rel.data) } |
||||
.rela.data : { *(.rela.data) } |
||||
.rel.rodata : { *(.rel.rodata) } |
||||
.rela.rodata : { *(.rela.rodata) } |
||||
.rel.got : { *(.rel.got) } |
||||
.rela.got : { *(.rela.got) } |
||||
.rel.ctors : { *(.rel.ctors) } |
||||
.rela.ctors : { *(.rela.ctors) } |
||||
.rel.dtors : { *(.rel.dtors) } |
||||
.rela.dtors : { *(.rela.dtors) } |
||||
.rel.bss : { *(.rel.bss) } |
||||
.rela.bss : { *(.rela.bss) } |
||||
.rel.plt : { *(.rel.plt) } |
||||
.rela.plt : { *(.rela.plt) } |
||||
.init : { *(.init) } |
||||
.plt : { *(.plt) } |
||||
.text : |
||||
{ |
||||
/* WARNING - the following is hand-optimized to fit within */ |
||||
/* the sector layout of our flash chips! XXX FIXME XXX */ |
||||
|
||||
cpu/mpc8xx/start.o (.text) |
||||
common/dlmalloc.o (.text) |
||||
lib_generic/vsprintf.o (.text) |
||||
lib_generic/crc32.o (.text) |
||||
|
||||
. = env_offset; |
||||
common/environment.o(.text) |
||||
|
||||
*(.text) |
||||
*(.fixup) |
||||
*(.got1) |
||||
} |
||||
_etext = .; |
||||
PROVIDE (etext = .); |
||||
.rodata : |
||||
{ |
||||
*(.rodata) |
||||
*(.rodata1) |
||||
} |
||||
.fini : { *(.fini) } =0 |
||||
.ctors : { *(.ctors) } |
||||
.dtors : { *(.dtors) } |
||||
|
||||
/* Read-write section, merged into data segment: */ |
||||
. = (. + 0x0FFF) & 0xFFFFF000; |
||||
_erotext = .; |
||||
PROVIDE (erotext = .); |
||||
.reloc : |
||||
{ |
||||
*(.got) |
||||
_GOT2_TABLE_ = .; |
||||
*(.got2) |
||||
_FIXUP_TABLE_ = .; |
||||
*(.fixup) |
||||
} |
||||
__got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2; |
||||
__fixup_entries = (. - _FIXUP_TABLE_)>>2; |
||||
|
||||
.data : |
||||
{ |
||||
*(.data) |
||||
*(.data1) |
||||
*(.sdata) |
||||
*(.sdata2) |
||||
*(.dynamic) |
||||
CONSTRUCTORS |
||||
} |
||||
_edata = .; |
||||
PROVIDE (edata = .); |
||||
|
||||
__u_boot_cmd_start = .; |
||||
.u_boot_cmd : { *(.u_boot_cmd) } |
||||
__u_boot_cmd_end = .; |
||||
|
||||
|
||||
__start___ex_table = .; |
||||
__ex_table : { *(__ex_table) } |
||||
__stop___ex_table = .; |
||||
|
||||
. = ALIGN(4096); |
||||
__init_begin = .; |
||||
.text.init : { *(.text.init) } |
||||
.data.init : { *(.data.init) } |
||||
. = ALIGN(4096); |
||||
__init_end = .; |
||||
|
||||
__bss_start = .; |
||||
.bss : |
||||
{ |
||||
*(.sbss) *(.scommon) |
||||
*(.dynbss) |
||||
*(.bss) |
||||
*(COMMON) |
||||
} |
||||
_end = . ; |
||||
PROVIDE (end = .); |
||||
} |
@ -0,0 +1,81 @@ |
||||
/*
|
||||
* (C) Copyright 2004 |
||||
* Klaus Heydeck, Kieback & Peter GmbH & Co KG, heydeck@kieback-peter.de |
||||
* |
||||
* See file CREDITS for list of people who contributed to this |
||||
* project. |
||||
* |
||||
* This program is free software; you can redistribute it and/or |
||||
* modify it under the terms of the GNU General Public License as |
||||
* published by the Free Software Foundation; either version 2 of |
||||
* the License, or (at your option) any later version. |
||||
* |
||||
* This program is distributed in the hope that it will be useful, |
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of |
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
||||
* GNU General Public License for more details. |
||||
* |
||||
* You should have received a copy of the GNU General Public License |
||||
* along with this program; if not, write to the Free Software |
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
||||
* MA 02111-1307 USA |
||||
*/ |
||||
|
||||
#include <common.h> |
||||
#include <mpc8xx.h> |
||||
#include "../common/kup.h" |
||||
|
||||
|
||||
#define SL811_ADR (0x50000000) |
||||
#define SL811_DAT (0x50000001) |
||||
|
||||
|
||||
static void sl811_write_index_data (__u8 index, __u8 data) |
||||
{ |
||||
*(volatile unsigned char *) (SL811_ADR) = index; |
||||
__asm__ ("eieio"); |
||||
*(volatile unsigned char *) (SL811_DAT) = data; |
||||
__asm__ ("eieio"); |
||||
} |
||||
|
||||
static __u8 sl811_read_index_data (__u8 index) |
||||
{ |
||||
__u8 data; |
||||
|
||||
*(volatile unsigned char *) (SL811_ADR) = index; |
||||
__asm__ ("eieio"); |
||||
data = *(volatile unsigned char *) (SL811_DAT); |
||||
__asm__ ("eieio"); |
||||
return (data); |
||||
} |
||||
|
||||
int usb_init_kup4x (void) |
||||
{ |
||||
volatile immap_t *immap = (immap_t *) CFG_IMMR; |
||||
volatile memctl8xx_t *memctl = &immap->im_memctl; |
||||
int i; |
||||
unsigned char tmp; |
||||
|
||||
memctl = &immap->im_memctl; |
||||
memctl->memc_or7 = 0xFFFF8726; |
||||
memctl->memc_br7 = 0x50000401; /* start at 0x50000000 */ |
||||
/* BP 14 low = USB ON */ |
||||
immap->im_cpm.cp_pbdat &= ~(BP_USB_VCC); |
||||
/* PB 14 nomal port */ |
||||
immap->im_cpm.cp_pbpar &= ~(BP_USB_VCC); |
||||
/* output */ |
||||
immap->im_cpm.cp_pbdir |= (BP_USB_VCC); |
||||
|
||||
puts ("USB: "); |
||||
|
||||
for (i = 0x10; i < 0xff; i++) { |
||||
sl811_write_index_data (i, i); |
||||
tmp = (sl811_read_index_data (i)); |
||||
if (tmp != i) { |
||||
printf ("SL811 compare error index=0x%02x read=0x%02x\n", i, tmp); |
||||
return (-1); |
||||
} |
||||
} |
||||
printf ("SL811 ready\n"); |
||||
return (0); |
||||
} |
@ -1,113 +0,0 @@ |
||||
/*---------------------------------------------------------------------------- */ |
||||
/* */ |
||||
/* File generated by S1D13706CFG.EXE */ |
||||
/* */ |
||||
/* Copyright (c) 2000,2001 Epson Research and Development, Inc. */ |
||||
/* All rights reserved. */ |
||||
/* */ |
||||
/*---------------------------------------------------------------------------- */ |
||||
|
||||
/* Panel: 320x240x8bpp 70Hz Color Single STN 8-bit (PCLK=6.250MHz) (Format 2) */ |
||||
|
||||
#define S1D_DISPLAY_WIDTH 320 |
||||
#define S1D_DISPLAY_HEIGHT 240 |
||||
#define S1D_DISPLAY_BPP 8 |
||||
#define S1D_DISPLAY_SCANLINE_BYTES 320 |
||||
#define S1D_PHYSICAL_VMEM_ADDR 0x800A0000L |
||||
#define S1D_PHYSICAL_VMEM_SIZE 0x14000L |
||||
#define S1D_PHYSICAL_REG_ADDR 0x80080000L |
||||
#define S1D_PHYSICAL_REG_SIZE 0x100 |
||||
#define S1D_DISPLAY_PCLK 6250 |
||||
#define S1D_PALETTE_SIZE 256 |
||||
#define S1D_REGDELAYOFF 0xFFFE |
||||
#define S1D_REGDELAYON 0xFFFF |
||||
|
||||
#define S1D_WRITE_PALETTE(p,i,r,g,b) \ |
||||
{ \
|
||||
((volatile S1D_VALUE*)(p))[0x0A/sizeof(S1D_VALUE)] = (S1D_VALUE)((r)>>4); \
|
||||
((volatile S1D_VALUE*)(p))[0x09/sizeof(S1D_VALUE)] = (S1D_VALUE)((g)>>4); \
|
||||
((volatile S1D_VALUE*)(p))[0x08/sizeof(S1D_VALUE)] = (S1D_VALUE)((b)>>4); \
|
||||
((volatile S1D_VALUE*)(p))[0x0B/sizeof(S1D_VALUE)] = (S1D_VALUE)(i); \
|
||||
} |
||||
|
||||
#define S1D_READ_PALETTE(p,i,r,g,b) \ |
||||
{ \
|
||||
((volatile S1D_VALUE*)(p))[0x0F/sizeof(S1D_VALUE)] = (S1D_VALUE)(i); \
|
||||
r = ((volatile S1D_VALUE*)(p))[0x0E/sizeof(S1D_VALUE)]; \
|
||||
g = ((volatile S1D_VALUE*)(p))[0x0D/sizeof(S1D_VALUE)]; \
|
||||
b = ((volatile S1D_VALUE*)(p))[0x0C/sizeof(S1D_VALUE)]; \
|
||||
} |
||||
|
||||
typedef unsigned short S1D_INDEX; |
||||
typedef unsigned char S1D_VALUE; |
||||
|
||||
|
||||
typedef struct |
||||
{ |
||||
S1D_INDEX Index; |
||||
S1D_VALUE Value; |
||||
} S1D_REGS; |
||||
|
||||
static S1D_REGS aS1DRegs[] = |
||||
{ |
||||
{0x04,0x10}, /* BUSCLK MEMCLK Config Register */ |
||||
#if 0 |
||||
{0x05,0x32}, /* PCLK Config Register */ |
||||
#endif |
||||
{0x10,0xD0}, /* PANEL Type Register */ |
||||
{0x11,0x00}, /* MOD Rate Register */ |
||||
#if 0 |
||||
{0x12,0x34}, /* Horizontal Total Register */ |
||||
#endif |
||||
{0x14,0x27}, /* Horizontal Display Period Register */ |
||||
{0x16,0x00}, /* Horizontal Display Period Start Pos Register 0 */ |
||||
{0x17,0x00}, /* Horizontal Display Period Start Pos Register 1 */ |
||||
{0x18,0xF0}, /* Vertical Total Register 0 */ |
||||
{0x19,0x00}, /* Vertical Total Register 1 */ |
||||
{0x1C,0xEF}, /* Vertical Display Period Register 0 */ |
||||
{0x1D,0x00}, /* Vertical Display Period Register 1 */ |
||||
{0x1E,0x00}, /* Vertical Display Period Start Pos Register 0 */ |
||||
{0x1F,0x00}, /* Vertical Display Period Start Pos Register 1 */ |
||||
{0x20,0x87}, /* Horizontal Sync Pulse Width Register */ |
||||
{0x22,0x00}, /* Horizontal Sync Pulse Start Pos Register 0 */ |
||||
{0x23,0x00}, /* Horizontal Sync Pulse Start Pos Register 1 */ |
||||
{0x24,0x80}, /* Vertical Sync Pulse Width Register */ |
||||
{0x26,0x01}, /* Vertical Sync Pulse Start Pos Register 0 */ |
||||
{0x27,0x00}, /* Vertical Sync Pulse Start Pos Register 1 */ |
||||
{0x70,0x83}, /* Display Mode Register */ |
||||
{0x71,0x00}, /* Special Effects Register */ |
||||
{0x74,0x00}, /* Main Window Display Start Address Register 0 */ |
||||
{0x75,0x00}, /* Main Window Display Start Address Register 1 */ |
||||
{0x76,0x00}, /* Main Window Display Start Address Register 2 */ |
||||
{0x78,0x50}, /* Main Window Address Offset Register 0 */ |
||||
{0x79,0x00}, /* Main Window Address Offset Register 1 */ |
||||
{0x7C,0x00}, /* Sub Window Display Start Address Register 0 */ |
||||
{0x7D,0x00}, /* Sub Window Display Start Address Register 1 */ |
||||
{0x7E,0x00}, /* Sub Window Display Start Address Register 2 */ |
||||
{0x80,0x50}, /* Sub Window Address Offset Register 0 */ |
||||
{0x81,0x00}, /* Sub Window Address Offset Register 1 */ |
||||
{0x84,0x00}, /* Sub Window X Start Pos Register 0 */ |
||||
{0x85,0x00}, /* Sub Window X Start Pos Register 1 */ |
||||
{0x88,0x00}, /* Sub Window Y Start Pos Register 0 */ |
||||
{0x89,0x00}, /* Sub Window Y Start Pos Register 1 */ |
||||
{0x8C,0x4F}, /* Sub Window X End Pos Register 0 */ |
||||
{0x8D,0x00}, /* Sub Window X End Pos Register 1 */ |
||||
{0x90,0xEF}, /* Sub Window Y End Pos Register 0 */ |
||||
{0x91,0x00}, /* Sub Window Y End Pos Register 1 */ |
||||
{0xA0,0x00}, /* Power Save Config Register */ |
||||
{0xA1,0x00}, /* CPU Access Control Register */ |
||||
{0xA2,0x00}, /* Software Reset Register */ |
||||
{0xA3,0x00}, /* BIG Endian Support Register */ |
||||
{0xA4,0x00}, /* Scratch Pad Register 0 */ |
||||
{0xA5,0x00}, /* Scratch Pad Register 1 */ |
||||
{0xA8,0x01}, /* GPIO Config Register 0 */ |
||||
{0xA9,0x80}, /* GPIO Config Register 1 */ |
||||
{0xAC,0x01}, /* GPIO Status Control Register 0 */ |
||||
{0xAD,0x00}, /* GPIO Status Control Register 1 */ |
||||
{0xB0,0x10}, /* PWM CV Clock Control Register */ |
||||
{0xB1,0x80}, /* PWM CV Clock Config Register */ |
||||
{0xB2,0x00}, /* CV Clock Burst Length Register */ |
||||
{0xB3,0xA0}, /* PWM Clock Duty Cycle Register */ |
||||
{0xAD,0x80}, /* reset seq */ |
||||
{0x70,0x03}, /* */ |
||||
}; |
@ -0,0 +1,389 @@ |
||||
/*
|
||||
* (C) Copyright 2000-2004 |
||||
* Wolfgang Denk, DENX Software Engineering, wd@denx.de. |
||||
* Klaus Heydeck, Kieback & Peter GmbH & Co KG, heydeck@kieback-peter.de |
||||
* |
||||
* See file CREDITS for list of people who contributed to this |
||||
* project. |
||||
* |
||||
* This program is free software; you can redistribute it and/or |
||||
* modify it under the terms of the GNU General Public License as |
||||
* published by the Free Software Foundation; either version 2 of |
||||
* the License, or (at your option) any later version. |
||||
* |
||||
* This program is distributed in the hope that it will be useful, |
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of |
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
||||
* GNU General Public License for more details. |
||||
* |
||||
* You should have received a copy of the GNU General Public License |
||||
* along with this program; if not, write to the Free Software |
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
||||
* MA 02111-1307 USA |
||||
*/ |
||||
|
||||
/*
|
||||
* board/config.h - configuration options, board specific |
||||
* Derived from ../tqm8xx/tqm8xx.c |
||||
*/ |
||||
|
||||
#ifndef __CONFIG_H |
||||
#define __CONFIG_H |
||||
|
||||
/*
|
||||
* High Level Configuration Options |
||||
* (easy to change) |
||||
*/ |
||||
|
||||
#define CONFIG_MPC859T 1 /* This is a MPC859T CPU */ |
||||
#define CONFIG_KUP4X 1 /* ...on a KUP4X module */ |
||||
|
||||
#define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */ |
||||
#undef CONFIG_8xx_CONS_SMC2 |
||||
#undef CONFIG_8xx_CONS_NONE |
||||
#define CONFIG_BAUDRATE 115200 /* console baudrate */ |
||||
#if 0 |
||||
#define CONFIG_BOOTDELAY -1 /* autoboot disabled */ |
||||
#else |
||||
#define CONFIG_BOOTDELAY 1 /* autoboot after 1 second */ |
||||
#endif |
||||
|
||||
#define CONFIG_CLOCKS_IN_MHZ 1 /* clocks passsed to Linux in MHz */ |
||||
|
||||
#define CONFIG_BOARD_TYPES 1 /* support board types */ |
||||
|
||||
#define CFG_8XX_FACT 8 /* Multiply by 8 */ |
||||
#define CFG_8XX_XIN 16000000 /* 16 MHz in */ |
||||
|
||||
|
||||
#define MPC8XX_HZ ((CFG_8XX_XIN) * (CFG_8XX_FACT)) |
||||
|
||||
/* should ALWAYS define this, measure_gclk in speed.c is unreliable */ |
||||
/* in general, we always know this for FADS+new ADS anyway */ |
||||
#define CONFIG_8xx_GCLK_FREQ MPC8XX_HZ |
||||
|
||||
|
||||
#undef CONFIG_BOOTARGS |
||||
|
||||
|
||||
#define CONFIG_EXTRA_ENV_SETTINGS \ |
||||
"slot_a_boot=setenv bootargs root=/dev/hda2 ip=off;" \
|
||||
"run addhw;diskboot 200000 0:1;bootm 200000\0" \
|
||||
"slot_b_boot=setenv bootargs root=/dev/hda2 ip=off;" \
|
||||
"run addhw;diskboot 200000 2:1;bootm 200000\0" \
|
||||
"nfs_boot=dhcp;run nfsargs addip addhw;bootm 200000\0" \
|
||||
"panic_boot=echo No Bootdevice !!! reset\0" \
|
||||
"nfsargs=setenv bootargs root=/dev/nfs rw nfsroot=$(serverip):$(rootpath)\0" \
|
||||
"ramargs=setenv bootargs root=/dev/ram rw\0" \
|
||||
"addip=setenv bootargs $(bootargs) ip=$(ipaddr):$(serverip):$(gatewayip)" \
|
||||
":$(netmask):$(hostname):$(netdev):off\0" \
|
||||
"addhw=setenv bootargs $(bootargs) hw=$(hw) key1=$(key1) panic=1\0" \
|
||||
"netdev=eth0\0" \
|
||||
"silent=1\0" \
|
||||
"load=tftp 200000 bootloader-4x.bitmap;tftp 100000 bootloader-4x.bin\0" \
|
||||
"update=protect off 1:0-5;era 1:0-5;cp.b 100000 40000000 $(filesize);" \
|
||||
"cp.b 200000 40040000 14000\0" |
||||
|
||||
#define CONFIG_BOOTCOMMAND \ |
||||
"run slot_a_boot;run nfs_boot;run panic_boot" |
||||
|
||||
|
||||
#define CONFIG_MISC_INIT_R 1 |
||||
#define CONFIG_MISC_INIT_F 1 |
||||
|
||||
#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ |
||||
#undef CFG_LOADS_BAUD_CHANGE /* don't allow baudrate change */ |
||||
|
||||
#undef CONFIG_WATCHDOG /* watchdog disabled */ |
||||
|
||||
#define CONFIG_STATUS_LED 1 /* Status LED enabled */ |
||||
|
||||
#undef CONFIG_CAN_DRIVER /* CAN Driver support disabled */ |
||||
|
||||
#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT | CONFIG_BOOTP_BOOTFILESIZE) |
||||
|
||||
#define CONFIG_MAC_PARTITION |
||||
#define CONFIG_DOS_PARTITION |
||||
|
||||
#define CONFIG_HARD_I2C |
||||
#define CFG_I2C_SPEED 40000 |
||||
#define CFG_I2C_SLAVE 0x7F |
||||
|
||||
#define CONFIG_ETHADDR 00:0B:64:80:00:00 /* our OUI from IEEE */ |
||||
#undef CONFIG_KUP4K_LOGO |
||||
|
||||
/* Define to allow the user to overwrite serial and ethaddr */ |
||||
#define CONFIG_ENV_OVERWRITE |
||||
|
||||
#define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \ |
||||
CFG_CMD_DHCP | \
|
||||
CFG_CMD_I2C | \
|
||||
CFG_CMD_IDE ) |
||||
|
||||
/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ |
||||
#include <cmd_confdefs.h> |
||||
|
||||
/*
|
||||
* Miscellaneous configurable options |
||||
*/ |
||||
#define CFG_LONGHELP /* undef to save memory */ |
||||
#define CFG_PROMPT "=> " /* Monitor Command Prompt */ |
||||
#if (CONFIG_COMMANDS & CFG_CMD_KGDB) |
||||
#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ |
||||
#else |
||||
#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ |
||||
#endif |
||||
#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ |
||||
#define CFG_MAXARGS 16 /* max number of command args */ |
||||
#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ |
||||
|
||||
#define CFG_MEMTEST_START 0x000400000 /* memtest works on */ |
||||
#define CFG_MEMTEST_END 0x003C00000 /* 4 ... 60 MB in DRAM */ |
||||
#define CFG_LOAD_ADDR 0x200000 /* default load address */ |
||||
|
||||
#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */ |
||||
|
||||
#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 115200 } |
||||
|
||||
#define CFG_CONSOLE_INFO_QUIET 1 |
||||
|
||||
/*
|
||||
* Low Level Configuration Settings |
||||
* (address mappings, register initial values, etc.) |
||||
* You should know what you are doing if you make changes here. |
||||
*/ |
||||
/*-----------------------------------------------------------------------
|
||||
* Internal Memory Mapped Register |
||||
*/ |
||||
#define CFG_IMMR 0xFFF00000 |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Definitions for initial stack pointer and data area (in DPRAM) |
||||
*/ |
||||
#define CFG_INIT_RAM_ADDR CFG_IMMR |
||||
#define CFG_INIT_RAM_END 0x2F00 /* End of used area in DPRAM */ |
||||
#define CFG_GBL_DATA_SIZE 64 /* size in bytes reserved for initial data */ |
||||
#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) |
||||
#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Start addresses for the final memory configuration |
||||
* (Set up by the startup code) |
||||
* Please note that CFG_SDRAM_BASE _must_ start at 0 |
||||
*/ |
||||
#define CFG_SDRAM_BASE 0x00000000 |
||||
#define CFG_FLASH_BASE 0x40000000 |
||||
#define CFG_MONITOR_LEN (192 << 10) /* Reserve 256 kB for Monitor */ |
||||
#define CFG_MONITOR_BASE CFG_FLASH_BASE |
||||
#define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ |
||||
|
||||
/*
|
||||
* For booting Linux, the board info and command line data |
||||
* have to be in the first 8 MB of memory, since this is |
||||
* the maximum mapped by the Linux kernel during initialization. |
||||
*/ |
||||
#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* FLASH organization |
||||
*/ |
||||
#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */ |
||||
#define CFG_MAX_FLASH_SECT 19 /* max number of sectors on one chip */ |
||||
|
||||
#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ |
||||
#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ |
||||
|
||||
#define CFG_ENV_IS_IN_FLASH 1 |
||||
#define CFG_ENV_OFFSET 0x30000 /* Offset of Environment Sector */ |
||||
#define CFG_ENV_SIZE 0x1000 /* Total Size of Environment Sector */ |
||||
#define CFG_ENV_SECT_SIZE 0x10000 |
||||
|
||||
/* Address and size of Redundant Environment Sector */ |
||||
#if 0 |
||||
#define CFG_ENV_OFFSET_REDUND (CFG_ENV_OFFSET+CFG_ENV_SIZE) |
||||
#define CFG_ENV_SIZE_REDUND (CFG_ENV_SIZE) |
||||
#endif |
||||
/*-----------------------------------------------------------------------
|
||||
* Hardware Information Block |
||||
*/ |
||||
#if 0 |
||||
#define CFG_HWINFO_OFFSET 0x0003FFC0 /* offset of HW Info block */ |
||||
#define CFG_HWINFO_SIZE 0x00000040 /* size of HW Info block */ |
||||
#define CFG_HWINFO_MAGIC 0x54514D38 /* 'TQM8' */ |
||||
#endif |
||||
/*-----------------------------------------------------------------------
|
||||
* Cache Configuration |
||||
*/ |
||||
#define CFG_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */ |
||||
#if (CONFIG_COMMANDS & CFG_CMD_KGDB) |
||||
#define CFG_CACHELINE_SHIFT 4 /* log base 2 of the above value */ |
||||
#endif |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* SYPCR - System Protection Control 11-9 |
||||
* SYPCR can only be written once after reset! |
||||
*----------------------------------------------------------------------- |
||||
* Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze |
||||
*/ |
||||
#if defined(CONFIG_WATCHDOG) |
||||
#define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \ |
||||
SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP) |
||||
#else |
||||
#define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP) |
||||
#endif |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* SIUMCR - SIU Module Configuration 11-6 |
||||
*----------------------------------------------------------------------- |
||||
* PCMCIA config., multi-function pin tri-state |
||||
*/ |
||||
#define CFG_SIUMCR (SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC00) |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* TBSCR - Time Base Status and Control 11-26 |
||||
*----------------------------------------------------------------------- |
||||
* Clear Reference Interrupt Status, Timebase freezing enabled |
||||
*/ |
||||
#define CFG_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF) |
||||
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* PISCR - Periodic Interrupt Status and Control 11-31 |
||||
*----------------------------------------------------------------------- |
||||
* Clear Periodic Interrupt Status, Interrupt Timer freezing enabled |
||||
*/ |
||||
#define CFG_PISCR (PISCR_PS | PISCR_PITF) |
||||
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* PLPRCR - PLL, Low-Power, and Reset Control Register 15-30 |
||||
*----------------------------------------------------------------------- |
||||
* set the PLL, the low-power modes and the reset control (15-29) |
||||
*/ |
||||
#define CFG_PLPRCR ((CFG_8XX_FACT << PLPRCR_MFI_SHIFT) | \ |
||||
PLPRCR_SPLSS | PLPRCR_TEXPS) |
||||
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* SCCR - System Clock and reset Control Register 15-27 |
||||
*----------------------------------------------------------------------- |
||||
* Set clock output, timebase and RTC source and divider, |
||||
* power management and some other internal clocks |
||||
*/ |
||||
#define SCCR_MASK SCCR_EBDF00 |
||||
#define CFG_SCCR (SCCR_TBS | SCCR_EBDF01 | \ |
||||
SCCR_COM00 | SCCR_DFSYNC00 | SCCR_DFBRG00 | \
|
||||
SCCR_DFNL000 | SCCR_DFNH000 | SCCR_DFLCD000 | \
|
||||
SCCR_DFALCD00) |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* PCMCIA stuff |
||||
*----------------------------------------------------------------------- |
||||
* |
||||
*/ |
||||
|
||||
/* KUP4K use both slots, SLOT_A as "primary". */ |
||||
#define CONFIG_PCMCIA_SLOT_A 1 |
||||
|
||||
#define CFG_PCMCIA_MEM_ADDR (0xE0000000) |
||||
#define CFG_PCMCIA_MEM_SIZE ( 64 << 20 ) |
||||
#define CFG_PCMCIA_DMA_ADDR (0xE4000000) |
||||
#define CFG_PCMCIA_DMA_SIZE ( 64 << 20 ) |
||||
#define CFG_PCMCIA_ATTRB_ADDR (0xE8000000) |
||||
#define CFG_PCMCIA_ATTRB_SIZE ( 64 << 20 ) |
||||
#define CFG_PCMCIA_IO_ADDR (0xEC000000) |
||||
#define CFG_PCMCIA_IO_SIZE ( 64 << 20 ) |
||||
|
||||
#define PCMCIA_SOCKETS_NO 1 |
||||
#define PCMCIA_MEM_WIN_NO 8 |
||||
/*-----------------------------------------------------------------------
|
||||
* IDE/ATA stuff (Supports IDE harddisk on PCMCIA Adapter) |
||||
*----------------------------------------------------------------------- |
||||
*/ |
||||
|
||||
#define CONFIG_IDE_8xx_PCCARD 1 /* Use IDE with PC Card Adapter */ |
||||
|
||||
#undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */ |
||||
#define CONFIG_IDE_LED 1 /* LED for ide supported */ |
||||
#undef CONFIG_IDE_RESET /* reset for ide not supported */ |
||||
|
||||
#define CFG_IDE_MAXBUS 1 |
||||
#define CFG_IDE_MAXDEVICE 2 |
||||
|
||||
#define CFG_ATA_IDE0_OFFSET 0x0000 |
||||
|
||||
#define CFG_ATA_IDE1_OFFSET (4 * CFG_PCMCIA_MEM_SIZE) |
||||
|
||||
#define CFG_ATA_BASE_ADDR CFG_PCMCIA_MEM_ADDR |
||||
|
||||
/* Offset for data I/O */ |
||||
#define CFG_ATA_DATA_OFFSET (CFG_PCMCIA_MEM_SIZE + 0x320) |
||||
|
||||
/* Offset for normal register accesses */ |
||||
#define CFG_ATA_REG_OFFSET (2 * CFG_PCMCIA_MEM_SIZE + 0x320) |
||||
|
||||
/* Offset for alternate registers */ |
||||
#define CFG_ATA_ALT_OFFSET 0x0100 |
||||
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* |
||||
*----------------------------------------------------------------------- |
||||
* |
||||
*/ |
||||
#define CFG_DER 0 |
||||
|
||||
/*
|
||||
* Init Memory Controller: |
||||
* |
||||
* BR0/1 and OR0/1 (FLASH) |
||||
*/ |
||||
#define FLASH_BASE0_PRELIM 0x40000000 /* FLASH bank #0 */ |
||||
|
||||
/* used to re-map FLASH both when starting from SRAM or FLASH:
|
||||
* restrict access enough to keep SRAM working (if any) |
||||
* but not too much to meddle with FLASH accesses |
||||
*/ |
||||
#define CFG_REMAP_OR_AM 0x80000000 /* OR addr mask */ |
||||
#define CFG_PRELIM_OR_AM 0xE0000000 /* OR addr mask */ |
||||
|
||||
/*
|
||||
* FLASH timing: |
||||
*/ |
||||
#define CFG_OR_TIMING_FLASH (OR_ACS_DIV1 | OR_TRLX | OR_CSNT_SAM | \ |
||||
OR_SCY_2_CLK | OR_EHTR | OR_BI) |
||||
|
||||
#define CFG_OR0_REMAP (CFG_REMAP_OR_AM | CFG_OR_TIMING_FLASH) |
||||
#define CFG_OR0_PRELIM (CFG_PRELIM_OR_AM | CFG_OR_TIMING_FLASH) |
||||
#define CFG_BR0_PRELIM ((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_PS_16 | BR_V ) |
||||
|
||||
|
||||
/* SDRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care) */ |
||||
#define CFG_OR_TIMING_SDRAM 0x00000A00 |
||||
|
||||
|
||||
#define CFG_MPTPR 0x400 |
||||
|
||||
/*
|
||||
* MAMR settings for SDRAM |
||||
*/ |
||||
#define CFG_MAMR 0x80802114 |
||||
|
||||
|
||||
/*
|
||||
* Internal Definitions |
||||
* |
||||
* Boot Flags |
||||
*/ |
||||
#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ |
||||
#define BOOTFLAG_WARM 0x02 /* Software reboot */ |
||||
|
||||
|
||||
#define CONFIG_AUTOBOOT_KEYED /* use key strings to stop autoboot */ |
||||
#if 0 |
||||
#define CONFIG_AUTOBOOT_PROMPT "Boote in %d Sekunden - stop mit \"2\"\n" |
||||
#endif |
||||
#define CONFIG_AUTOBOOT_STOP_STR "." /* easy to stop for now */ |
||||
#define CONFIG_SILENT_CONSOLE 1 |
||||
|
||||
#endif /* __CONFIG_H */ |
Loading…
Reference in new issue