These files are taken verbatim from the Linux kernel 4.17 Signed-off-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Stefan Roese <sr@denx.de>lime2-spi
Chris Packham
7 years ago
committed by
Stefan Roese
parent
f2d0f5e7ab
commit
060c85d41c
@ -0,0 +1,88 @@ |
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// SPDX-License-Identifier: GPL-2.0 |
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/ { |
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mbus@f1000000 { |
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pciec: pcie@82000000 { |
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compatible = "marvell,kirkwood-pcie"; |
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status = "disabled"; |
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device_type = "pci"; |
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|
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#address-cells = <3>; |
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#size-cells = <2>; |
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bus-range = <0x00 0xff>; |
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|
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ranges = |
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<0x82000000 0 0x40000 MBUS_ID(0xf0, 0x01) 0x40000 0 0x00002000 |
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0x82000000 0x1 0 MBUS_ID(0x04, 0xe8) 0 1 0 /* Port 0.0 MEM */ |
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0x81000000 0x1 0 MBUS_ID(0x04, 0xe0) 0 1 0 /* Port 0.0 IO */>; |
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|
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pcie0: pcie@1,0 { |
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device_type = "pci"; |
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assigned-addresses = <0x82000800 0 0x00040000 0 0x2000>; |
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reg = <0x0800 0 0 0 0>; |
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#address-cells = <3>; |
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#size-cells = <2>; |
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#interrupt-cells = <1>; |
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ranges = <0x82000000 0 0 0x82000000 0x1 0 1 0 |
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0x81000000 0 0 0x81000000 0x1 0 1 0>; |
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bus-range = <0x00 0xff>; |
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interrupt-map-mask = <0 0 0 0>; |
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interrupt-map = <0 0 0 0 &intc 9>; |
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marvell,pcie-port = <0>; |
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marvell,pcie-lane = <0>; |
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clocks = <&gate_clk 2>; |
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status = "disabled"; |
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}; |
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}; |
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}; |
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|
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ocp@f1000000 { |
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pinctrl: pin-controller@10000 { |
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compatible = "marvell,88f6192-pinctrl"; |
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|
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pmx_sata0: pmx-sata0 { |
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marvell,pins = "mpp5", "mpp21", "mpp23"; |
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marvell,function = "sata0"; |
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}; |
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pmx_sata1: pmx-sata1 { |
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marvell,pins = "mpp4", "mpp20", "mpp22"; |
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marvell,function = "sata1"; |
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}; |
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pmx_sdio: pmx-sdio { |
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marvell,pins = "mpp12", "mpp13", "mpp14", |
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"mpp15", "mpp16", "mpp17"; |
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marvell,function = "sdio"; |
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}; |
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}; |
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|
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rtc: rtc@10300 { |
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compatible = "marvell,kirkwood-rtc", "marvell,orion-rtc"; |
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reg = <0x10300 0x20>; |
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interrupts = <53>; |
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clocks = <&gate_clk 7>; |
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}; |
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|
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sata: sata@80000 { |
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compatible = "marvell,orion-sata"; |
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reg = <0x80000 0x5000>; |
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interrupts = <21>; |
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clocks = <&gate_clk 14>, <&gate_clk 15>; |
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clock-names = "0", "1"; |
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phys = <&sata_phy0>, <&sata_phy1>; |
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phy-names = "port0", "port1"; |
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status = "disabled"; |
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}; |
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|
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sdio: mvsdio@90000 { |
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compatible = "marvell,orion-sdio"; |
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reg = <0x90000 0x200>; |
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interrupts = <28>; |
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clocks = <&gate_clk 4>; |
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bus-width = <4>; |
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cap-sdio-irq; |
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cap-sd-highspeed; |
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cap-mmc-highspeed; |
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status = "disabled"; |
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}; |
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}; |
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}; |
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@ -0,0 +1,90 @@ |
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// SPDX-License-Identifier: GPL-2.0 |
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/ { |
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mbus@f1000000 { |
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pciec: pcie@82000000 { |
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compatible = "marvell,kirkwood-pcie"; |
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status = "disabled"; |
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device_type = "pci"; |
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|
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#address-cells = <3>; |
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#size-cells = <2>; |
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bus-range = <0x00 0xff>; |
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ranges = |
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<0x82000000 0 0x40000 MBUS_ID(0xf0, 0x01) 0x40000 0 0x00002000 |
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0x82000000 0x1 0 MBUS_ID(0x04, 0xe8) 0 1 0 /* Port 0.0 MEM */ |
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0x81000000 0x1 0 MBUS_ID(0x04, 0xe0) 0 1 0 /* Port 0.0 IO */>; |
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|
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pcie0: pcie@1,0 { |
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device_type = "pci"; |
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assigned-addresses = <0x82000800 0 0x00040000 0 0x2000>; |
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reg = <0x0800 0 0 0 0>; |
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#address-cells = <3>; |
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#size-cells = <2>; |
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#interrupt-cells = <1>; |
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ranges = <0x82000000 0 0 0x82000000 0x1 0 1 0 |
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0x81000000 0 0 0x81000000 0x1 0 1 0>; |
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bus-range = <0x00 0xff>; |
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interrupt-map-mask = <0 0 0 0>; |
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interrupt-map = <0 0 0 0 &intc 9>; |
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marvell,pcie-port = <0>; |
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marvell,pcie-lane = <0>; |
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clocks = <&gate_clk 2>; |
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status = "disabled"; |
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}; |
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}; |
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}; |
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|
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ocp@f1000000 { |
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pinctrl: pin-controller@10000 { |
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compatible = "marvell,88f6281-pinctrl"; |
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pmx_sata0: pmx-sata0 { |
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marvell,pins = "mpp5", "mpp21", "mpp23"; |
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marvell,function = "sata0"; |
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}; |
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pmx_sata1: pmx-sata1 { |
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marvell,pins = "mpp4", "mpp20", "mpp22"; |
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marvell,function = "sata1"; |
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}; |
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pmx_sdio: pmx-sdio { |
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marvell,pins = "mpp12", "mpp13", "mpp14", |
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"mpp15", "mpp16", "mpp17"; |
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marvell,function = "sdio"; |
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}; |
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}; |
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|
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rtc: rtc@10300 { |
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compatible = "marvell,kirkwood-rtc", "marvell,orion-rtc"; |
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reg = <0x10300 0x20>; |
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interrupts = <53>; |
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clocks = <&gate_clk 7>; |
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}; |
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|
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sata: sata@80000 { |
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compatible = "marvell,orion-sata"; |
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reg = <0x80000 0x5000>; |
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interrupts = <21>; |
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clocks = <&gate_clk 14>, <&gate_clk 15>; |
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clock-names = "0", "1"; |
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phys = <&sata_phy0>, <&sata_phy1>; |
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phy-names = "port0", "port1"; |
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status = "disabled"; |
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}; |
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sdio: mvsdio@90000 { |
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compatible = "marvell,orion-sdio"; |
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reg = <0x90000 0x200>; |
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interrupts = <28>; |
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clocks = <&gate_clk 4>; |
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pinctrl-0 = <&pmx_sdio>; |
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pinctrl-names = "default"; |
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bus-width = <4>; |
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cap-sdio-irq; |
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cap-sd-highspeed; |
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cap-mmc-highspeed; |
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status = "disabled"; |
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}; |
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}; |
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}; |
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@ -0,0 +1,53 @@ |
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// SPDX-License-Identifier: GPL-2.0 |
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/ { |
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mbus@f1000000 { |
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pciec: pcie@82000000 { |
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compatible = "marvell,kirkwood-pcie"; |
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status = "disabled"; |
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device_type = "pci"; |
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|
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#address-cells = <3>; |
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#size-cells = <2>; |
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bus-range = <0x00 0xff>; |
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ranges = |
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<0x82000000 0 0x40000 MBUS_ID(0xf0, 0x01) 0x40000 0 0x00002000 |
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0x82000000 0x1 0 MBUS_ID(0x04, 0xe8) 0 1 0 /* Port 0.0 MEM */ |
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0x81000000 0x1 0 MBUS_ID(0x04, 0xe0) 0 1 0 /* Port 0.0 IO */>; |
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pcie0: pcie@1,0 { |
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device_type = "pci"; |
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assigned-addresses = <0x82000800 0 0x00040000 0 0x2000>; |
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reg = <0x0800 0 0 0 0>; |
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#address-cells = <3>; |
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#size-cells = <2>; |
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#interrupt-cells = <1>; |
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ranges = <0x82000000 0 0 0x82000000 0x1 0 1 0 |
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0x81000000 0 0 0x81000000 0x1 0 1 0>; |
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bus-range = <0x00 0xff>; |
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interrupt-map-mask = <0 0 0 0>; |
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interrupt-map = <0 0 0 0 &intc 9>; |
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marvell,pcie-port = <0>; |
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marvell,pcie-lane = <0>; |
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clocks = <&gate_clk 2>; |
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status = "disabled"; |
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}; |
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}; |
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}; |
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ocp@f1000000 { |
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pinctrl: pin-controller@10000 { |
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compatible = "marvell,98dx4122-pinctrl"; |
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}; |
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}; |
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}; |
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&sata_phy0 { |
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status = "disabled"; |
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}; |
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&sata_phy1 { |
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status = "disabled"; |
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}; |
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@ -0,0 +1,393 @@ |
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// SPDX-License-Identifier: GPL-2.0 |
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/include/ "skeleton.dtsi" |
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#include <dt-bindings/input/input.h> |
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#include <dt-bindings/gpio/gpio.h> |
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#define MBUS_ID(target,attributes) (((target) << 24) | ((attributes) << 16)) |
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/ { |
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compatible = "marvell,kirkwood"; |
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interrupt-parent = <&intc>; |
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cpus { |
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#address-cells = <1>; |
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#size-cells = <0>; |
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cpu@0 { |
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device_type = "cpu"; |
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compatible = "marvell,feroceon"; |
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reg = <0>; |
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clocks = <&core_clk 1>, <&core_clk 3>, <&gate_clk 11>; |
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clock-names = "cpu_clk", "ddrclk", "powersave"; |
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}; |
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}; |
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aliases { |
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gpio0 = &gpio0; |
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gpio1 = &gpio1; |
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i2c0 = &i2c0; |
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}; |
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mbus@f1000000 { |
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compatible = "marvell,kirkwood-mbus", "simple-bus"; |
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#address-cells = <2>; |
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#size-cells = <1>; |
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/* If a board file needs to change this ranges it must replace it completely */ |
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ranges = <MBUS_ID(0xf0, 0x01) 0 0xf1000000 0x100000 /* internal-regs */ |
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MBUS_ID(0x01, 0x2f) 0 0xf4000000 0x10000 /* nand flash */ |
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MBUS_ID(0x03, 0x01) 0 0xf5000000 0x10000 /* crypto sram */ |
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>; |
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controller = <&mbusc>; |
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pcie-mem-aperture = <0xe0000000 0x10000000>; /* 256 MiB memory space */ |
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pcie-io-aperture = <0xf2000000 0x100000>; /* 1 MiB I/O space */ |
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nand: nand@12f { |
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#address-cells = <1>; |
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#size-cells = <1>; |
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cle = <0>; |
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ale = <1>; |
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bank-width = <1>; |
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compatible = "marvell,orion-nand"; |
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reg = <MBUS_ID(0x01, 0x2f) 0 0x400>; |
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chip-delay = <25>; |
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/* set partition map and/or chip-delay in board dts */ |
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clocks = <&gate_clk 7>; |
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pinctrl-0 = <&pmx_nand>; |
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pinctrl-names = "default"; |
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status = "disabled"; |
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}; |
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crypto_sram: sa-sram@301 { |
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compatible = "mmio-sram"; |
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reg = <MBUS_ID(0x03, 0x01) 0x0 0x800>; |
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clocks = <&gate_clk 17>; |
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#address-cells = <1>; |
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#size-cells = <1>; |
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}; |
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}; |
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ocp@f1000000 { |
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compatible = "simple-bus"; |
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ranges = <0x00000000 0xf1000000 0x0100000>; |
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#address-cells = <1>; |
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#size-cells = <1>; |
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pinctrl: pin-controller@10000 { |
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/* set compatible property in SoC file */ |
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reg = <0x10000 0x20>; |
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pmx_ge1: pmx-ge1 { |
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marvell,pins = "mpp20", "mpp21", "mpp22", "mpp23", |
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"mpp24", "mpp25", "mpp26", "mpp27", |
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"mpp30", "mpp31", "mpp32", "mpp33"; |
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marvell,function = "ge1"; |
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}; |
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pmx_nand: pmx-nand { |
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marvell,pins = "mpp0", "mpp1", "mpp2", "mpp3", |
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"mpp4", "mpp5", "mpp18", "mpp19"; |
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marvell,function = "nand"; |
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}; |
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/* |
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* Default SPI0 pinctrl setting with CSn on mpp0, |
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* overwrite marvell,pins on board level if required. |
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*/ |
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pmx_spi: pmx-spi { |
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marvell,pins = "mpp0", "mpp1", "mpp2", "mpp3"; |
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marvell,function = "spi"; |
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}; |
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pmx_twsi0: pmx-twsi0 { |
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marvell,pins = "mpp8", "mpp9"; |
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marvell,function = "twsi0"; |
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}; |
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|
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/* |
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* Default UART pinctrl setting without RTS/CTS, |
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* overwrite marvell,pins on board level if required. |
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*/ |
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pmx_uart0: pmx-uart0 { |
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marvell,pins = "mpp10", "mpp11"; |
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marvell,function = "uart0"; |
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}; |
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pmx_uart1: pmx-uart1 { |
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marvell,pins = "mpp13", "mpp14"; |
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marvell,function = "uart1"; |
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}; |
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}; |
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core_clk: core-clocks@10030 { |
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compatible = "marvell,kirkwood-core-clock"; |
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reg = <0x10030 0x4>; |
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#clock-cells = <1>; |
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}; |
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|
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spi0: spi@10600 { |
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compatible = "marvell,orion-spi"; |
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#address-cells = <1>; |
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#size-cells = <0>; |
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cell-index = <0>; |
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interrupts = <23>; |
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reg = <0x10600 0x28>; |
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clocks = <&gate_clk 7>; |
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pinctrl-0 = <&pmx_spi>; |
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pinctrl-names = "default"; |
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status = "disabled"; |
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}; |
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|
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gpio0: gpio@10100 { |
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compatible = "marvell,orion-gpio"; |
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#gpio-cells = <2>; |
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gpio-controller; |
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reg = <0x10100 0x40>; |
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ngpios = <32>; |
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interrupt-controller; |
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#interrupt-cells = <2>; |
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interrupts = <35>, <36>, <37>, <38>; |
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clocks = <&gate_clk 7>; |
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}; |
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|
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gpio1: gpio@10140 { |
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compatible = "marvell,orion-gpio"; |
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#gpio-cells = <2>; |
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gpio-controller; |
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reg = <0x10140 0x40>; |
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ngpios = <18>; |
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interrupt-controller; |
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#interrupt-cells = <2>; |
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interrupts = <39>, <40>, <41>; |
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clocks = <&gate_clk 7>; |
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}; |
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|
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i2c0: i2c@11000 { |
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compatible = "marvell,mv64xxx-i2c"; |
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reg = <0x11000 0x20>; |
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#address-cells = <1>; |
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#size-cells = <0>; |
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interrupts = <29>; |
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clock-frequency = <100000>; |
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clocks = <&gate_clk 7>; |
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pinctrl-0 = <&pmx_twsi0>; |
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pinctrl-names = "default"; |
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status = "disabled"; |
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}; |
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|
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uart0: serial@12000 { |
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compatible = "ns16550a"; |
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reg = <0x12000 0x100>; |
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reg-shift = <2>; |
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interrupts = <33>; |
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clocks = <&gate_clk 7>; |
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pinctrl-0 = <&pmx_uart0>; |
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pinctrl-names = "default"; |
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status = "disabled"; |
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}; |
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|
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uart1: serial@12100 { |
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compatible = "ns16550a"; |
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reg = <0x12100 0x100>; |
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reg-shift = <2>; |
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interrupts = <34>; |
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clocks = <&gate_clk 7>; |
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pinctrl-0 = <&pmx_uart1>; |
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pinctrl-names = "default"; |
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status = "disabled"; |
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}; |
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|
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mbusc: mbus-controller@20000 { |
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compatible = "marvell,mbus-controller"; |
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reg = <0x20000 0x80>, <0x1500 0x20>; |
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}; |
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|
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sysc: system-controller@20000 { |
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compatible = "marvell,orion-system-controller"; |
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reg = <0x20000 0x120>; |
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}; |
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|
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bridge_intc: bridge-interrupt-ctrl@20110 { |
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compatible = "marvell,orion-bridge-intc"; |
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interrupt-controller; |
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#interrupt-cells = <1>; |
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reg = <0x20110 0x8>; |
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interrupts = <1>; |
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marvell,#interrupts = <6>; |
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}; |
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|
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gate_clk: clock-gating-control@2011c { |
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compatible = "marvell,kirkwood-gating-clock"; |
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reg = <0x2011c 0x4>; |
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clocks = <&core_clk 0>; |
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#clock-cells = <1>; |
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}; |
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|
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l2: l2-cache@20128 { |
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compatible = "marvell,kirkwood-cache"; |
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reg = <0x20128 0x4>; |
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}; |
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|
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intc: main-interrupt-ctrl@20200 { |
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compatible = "marvell,orion-intc"; |
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interrupt-controller; |
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#interrupt-cells = <1>; |
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reg = <0x20200 0x10>, <0x20210 0x10>; |
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}; |
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|
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timer: timer@20300 { |
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compatible = "marvell,orion-timer"; |
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reg = <0x20300 0x20>; |
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interrupt-parent = <&bridge_intc>; |
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interrupts = <1>, <2>; |
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clocks = <&core_clk 0>; |
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}; |
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|
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wdt: watchdog-timer@20300 { |
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compatible = "marvell,orion-wdt"; |
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reg = <0x20300 0x28>, <0x20108 0x4>; |
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interrupt-parent = <&bridge_intc>; |
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interrupts = <3>; |
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clocks = <&gate_clk 7>; |
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status = "okay"; |
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}; |
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|
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cesa: crypto@30000 { |
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compatible = "marvell,kirkwood-crypto"; |
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reg = <0x30000 0x10000>; |
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reg-names = "regs"; |
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interrupts = <22>; |
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clocks = <&gate_clk 17>; |
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marvell,crypto-srams = <&crypto_sram>; |
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marvell,crypto-sram-size = <0x800>; |
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status = "okay"; |
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}; |
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|
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usb0: ehci@50000 { |
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compatible = "marvell,orion-ehci"; |
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reg = <0x50000 0x1000>; |
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interrupts = <19>; |
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clocks = <&gate_clk 3>; |
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status = "okay"; |
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}; |
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|
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dma0: xor@60800 { |
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compatible = "marvell,orion-xor"; |
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reg = <0x60800 0x100 |
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0x60A00 0x100>; |
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status = "okay"; |
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clocks = <&gate_clk 8>; |
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|
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xor00 { |
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interrupts = <5>; |
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dmacap,memcpy; |
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dmacap,xor; |
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}; |
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xor01 { |
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interrupts = <6>; |
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dmacap,memcpy; |
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dmacap,xor; |
||||
dmacap,memset; |
||||
}; |
||||
}; |
||||
|
||||
dma1: xor@60900 { |
||||
compatible = "marvell,orion-xor"; |
||||
reg = <0x60900 0x100 |
||||
0x60B00 0x100>; |
||||
status = "okay"; |
||||
clocks = <&gate_clk 16>; |
||||
|
||||
xor00 { |
||||
interrupts = <7>; |
||||
dmacap,memcpy; |
||||
dmacap,xor; |
||||
}; |
||||
xor01 { |
||||
interrupts = <8>; |
||||
dmacap,memcpy; |
||||
dmacap,xor; |
||||
dmacap,memset; |
||||
}; |
||||
}; |
||||
|
||||
eth0: ethernet-controller@72000 { |
||||
compatible = "marvell,kirkwood-eth"; |
||||
#address-cells = <1>; |
||||
#size-cells = <0>; |
||||
reg = <0x72000 0x4000>; |
||||
clocks = <&gate_clk 0>; |
||||
marvell,tx-checksum-limit = <1600>; |
||||
status = "disabled"; |
||||
|
||||
eth0port: ethernet0-port@0 { |
||||
compatible = "marvell,kirkwood-eth-port"; |
||||
reg = <0>; |
||||
interrupts = <11>; |
||||
/* overwrite MAC address in bootloader */ |
||||
local-mac-address = [00 00 00 00 00 00]; |
||||
/* set phy-handle property in board file */ |
||||
}; |
||||
}; |
||||
|
||||
mdio: mdio-bus@72004 { |
||||
compatible = "marvell,orion-mdio"; |
||||
#address-cells = <1>; |
||||
#size-cells = <0>; |
||||
reg = <0x72004 0x84>; |
||||
interrupts = <46>; |
||||
clocks = <&gate_clk 0>; |
||||
status = "disabled"; |
||||
|
||||
/* add phy nodes in board file */ |
||||
}; |
||||
|
||||
eth1: ethernet-controller@76000 { |
||||
compatible = "marvell,kirkwood-eth"; |
||||
#address-cells = <1>; |
||||
#size-cells = <0>; |
||||
reg = <0x76000 0x4000>; |
||||
clocks = <&gate_clk 19>; |
||||
marvell,tx-checksum-limit = <1600>; |
||||
pinctrl-0 = <&pmx_ge1>; |
||||
pinctrl-names = "default"; |
||||
status = "disabled"; |
||||
|
||||
eth1port: ethernet1-port@0 { |
||||
compatible = "marvell,kirkwood-eth-port"; |
||||
reg = <0>; |
||||
interrupts = <15>; |
||||
/* overwrite MAC address in bootloader */ |
||||
local-mac-address = [00 00 00 00 00 00]; |
||||
/* set phy-handle property in board file */ |
||||
}; |
||||
}; |
||||
|
||||
sata_phy0: sata-phy@82000 { |
||||
compatible = "marvell,mvebu-sata-phy"; |
||||
reg = <0x82000 0x0334>; |
||||
clocks = <&gate_clk 14>; |
||||
clock-names = "sata"; |
||||
#phy-cells = <0>; |
||||
status = "ok"; |
||||
}; |
||||
|
||||
sata_phy1: sata-phy@84000 { |
||||
compatible = "marvell,mvebu-sata-phy"; |
||||
reg = <0x84000 0x0334>; |
||||
clocks = <&gate_clk 15>; |
||||
clock-names = "sata"; |
||||
#phy-cells = <0>; |
||||
status = "ok"; |
||||
}; |
||||
|
||||
audio0: audio-controller@a0000 { |
||||
compatible = "marvell,kirkwood-audio"; |
||||
#sound-dai-cells = <0>; |
||||
reg = <0xa0000 0x2210>; |
||||
interrupts = <24>; |
||||
clocks = <&gate_clk 9>; |
||||
clock-names = "internal"; |
||||
status = "disabled"; |
||||
}; |
||||
}; |
||||
}; |
||||
Loading…
Reference in new issue