omap1510inn is orphan and has been for years now. Reove it and, as it was the only arm925t target, also remove arm925t support. Update doc/README.scrapyard accordingly. Signed-off-by: Albert ARIBAUD <albert.u.boot@aribaud.net>master
Albert ARIBAUD
11 years ago
parent
ddd025bb6e
commit
0610a16cf2
@ -1,34 +0,0 @@ |
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#
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# (C) Copyright 2000-2006
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# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
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#
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# SPDX-License-Identifier: GPL-2.0+
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#
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include $(TOPDIR)/config.mk |
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LIB = $(obj)lib$(CPU).o
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START = start.o
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COBJS += cpu.o
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COBJS += omap925.o
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COBJS += timer.o
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SRCS := $(START:.o=.S) $(SOBJS:.o=.S) $(COBJS:.o=.c)
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OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS))
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START := $(addprefix $(obj),$(START))
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all: $(obj).depend $(START) $(LIB) |
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$(LIB): $(OBJS) |
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$(call cmd_link_o_target, $(OBJS))
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#########################################################################
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# defines $(obj).depend target
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include $(SRCTREE)/rules.mk |
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sinclude $(obj).depend |
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#########################################################################
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@ -1,15 +0,0 @@ |
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#
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# (C) Copyright 2002
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# Gary Jennejohn, DENX Software Engineering, <garyj@denx.de>
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#
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# SPDX-License-Identifier: GPL-2.0+
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#
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PLATFORM_CPPFLAGS += -march=armv4
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# =========================================================================
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#
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# Supply options according to compiler version
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#
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# =========================================================================
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PF_RELFLAGS_SLB_AT := $(call cc-option,-mshort-load-bytes,$(call cc-option,-malignment-traps,))
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PLATFORM_RELFLAGS += $(PF_RELFLAGS_SLB_AT)
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@ -1,50 +0,0 @@ |
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/*
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* (C) Copyright 2002 |
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* Sysgo Real-Time Solutions, GmbH <www.elinos.com> |
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* Marius Groeger <mgroeger@sysgo.de> |
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* |
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* (C) Copyright 2002 |
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* Gary Jennejohn, DENX Software Engineering, <garyj@denx.de> |
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* |
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* SPDX-License-Identifier: GPL-2.0+ |
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*/ |
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/*
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* CPU specific code |
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*/ |
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#include <common.h> |
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#include <command.h> |
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#include <arm925t.h> |
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#include <asm/system.h> |
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static void cache_flush(void); |
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int cleanup_before_linux (void) |
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{ |
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/*
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* this function is called just before we call linux |
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* it prepares the processor for linux |
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* |
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* we turn off caches etc ... |
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*/ |
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disable_interrupts (); |
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/* turn off I/D-cache */ |
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icache_disable(); |
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dcache_disable(); |
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/* flush I/D-cache */ |
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cache_flush(); |
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return 0; |
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} |
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/* flush I/D-cache */ |
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static void cache_flush (void) |
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{ |
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unsigned long i = 0; |
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asm ("mcr p15, 0, %0, c7, c7, 0": :"r" (i)); |
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} |
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@ -1,23 +0,0 @@ |
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/*
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* (C) Copyright 2003 |
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* Texas Instruments <www.ti.com> |
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* |
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* SPDX-License-Identifier: GPL-2.0+ |
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*/ |
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#include <common.h> |
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#include <command.h> |
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#include <arm925t.h> |
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#define MIF_CONFIG_REG 0xFFFECC0C |
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#define FLASH_GLOBAL_CTRL_NWP 1 |
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void archflashwp (void *archdata, int wp) |
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{ |
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ulong *fgc = (ulong *) MIF_CONFIG_REG; |
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if (wp == 1) |
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*fgc &= ~FLASH_GLOBAL_CTRL_NWP; |
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else |
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*fgc |= FLASH_GLOBAL_CTRL_NWP; |
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} |
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@ -1,382 +0,0 @@ |
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/* |
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* armboot - Startup Code for ARM925 CPU-core |
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* |
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* Copyright (c) 2003 Texas Instruments |
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* |
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* ----- Adapted for OMAP1510 from ARM920 code ------ |
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* |
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* Copyright (c) 2001 Marius Gröger <mag@sysgo.de>
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* Copyright (c) 2002 Alex Züpke <azu@sysgo.de>
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* Copyright (c) 2002 Gary Jennejohn <garyj@denx.de>
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* Copyright (c) 2003 Richard Woodruff <r-woodruff2@ti.com>
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* Copyright (c) 2003 Kshitij <kshitij@ti.com>
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* |
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* SPDX-License-Identifier: GPL-2.0+ |
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*/ |
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#include <asm-offsets.h> |
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#include <config.h> |
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#include <version.h> |
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/* |
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************************************************************************* |
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* |
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* Jump vector table as in table 3.1 in [1] |
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* |
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************************************************************************* |
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*/ |
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.globl _start
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_start: b reset |
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ldr pc, _undefined_instruction |
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ldr pc, _software_interrupt |
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ldr pc, _prefetch_abort |
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ldr pc, _data_abort |
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ldr pc, _not_used |
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ldr pc, _irq |
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ldr pc, _fiq |
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_undefined_instruction: .word undefined_instruction |
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_software_interrupt: .word software_interrupt |
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_prefetch_abort: .word prefetch_abort |
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_data_abort: .word data_abort |
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_not_used: .word not_used |
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_irq: .word irq |
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_fiq: .word fiq |
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.balignl 16,0xdeadbeef |
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/* |
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************************************************************************* |
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* |
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* Startup Code (reset vector) |
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* |
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* do important init only if we don't start from memory! |
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* setup Memory and board specific bits prior to relocation. |
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* relocate armboot to ram |
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* setup stack |
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* |
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************************************************************************* |
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*/ |
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.globl _TEXT_BASE
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_TEXT_BASE: |
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#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_TEXT_BASE) |
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.word CONFIG_SPL_TEXT_BASE
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#else |
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.word CONFIG_SYS_TEXT_BASE
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#endif |
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/* |
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* These are defined in the board-specific linker script. |
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* Subtracting _start from them lets the linker put their |
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* relative position in the executable instead of leaving |
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* them null. |
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*/ |
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.globl _bss_start_ofs
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_bss_start_ofs: |
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.word __bss_start - _start |
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.globl _bss_end_ofs
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_bss_end_ofs: |
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.word __bss_end - _start |
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.globl _end_ofs
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_end_ofs: |
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.word _end - _start |
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#ifdef CONFIG_USE_IRQ |
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/* IRQ stack memory (calculated at run-time) */ |
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.globl IRQ_STACK_START
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IRQ_STACK_START: |
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.word 0x0badc0de
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/* IRQ stack memory (calculated at run-time) */ |
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.globl FIQ_STACK_START
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FIQ_STACK_START: |
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.word 0x0badc0de
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#endif |
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/* IRQ stack memory (calculated at run-time) + 8 bytes */ |
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.globl IRQ_STACK_START_IN
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IRQ_STACK_START_IN: |
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.word 0x0badc0de
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/* |
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* the actual reset code |
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*/ |
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reset: |
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/* |
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* set the cpu to SVC32 mode |
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*/ |
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mrs r0,cpsr |
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bic r0,r0,#0x1f |
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orr r0,r0,#0xd3 |
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msr cpsr,r0 |
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/* |
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* Set up 925T mode |
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*/ |
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mov r1, #0x81 /* Set ARM925T configuration. */ |
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mcr p15, 0, r1, c15, c1, 0 /* Write ARM925T configuration register. */ |
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/* |
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* turn off the watchdog, unlock/diable sequence |
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*/ |
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mov r1, #0xF5 |
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ldr r0, =WDTIM_MODE |
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strh r1, [r0] |
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mov r1, #0xA0 |
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strh r1, [r0] |
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/* |
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* mask all IRQs by setting all bits in the INTMR - default |
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*/ |
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mov r1, #0xffffffff |
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ldr r0, =REG_IHL1_MIR |
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str r1, [r0] |
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ldr r0, =REG_IHL2_MIR |
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str r1, [r0] |
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/* |
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* wait for dpll to lock |
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*/ |
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ldr r0, =CK_DPLL1 |
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mov r1, #0x10 |
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strh r1, [r0] |
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poll1: |
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ldrh r1, [r0] |
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ands r1, r1, #0x01 |
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beq poll1 |
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/* |
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* we do sys-critical inits only at reboot, |
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* not when booting from ram! |
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*/ |
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#ifndef CONFIG_SKIP_LOWLEVEL_INIT |
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bl cpu_init_crit |
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#endif |
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bl _main |
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/*------------------------------------------------------------------------------*/ |
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.globl c_runtime_cpu_setup
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c_runtime_cpu_setup: |
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mov pc, lr |
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/* |
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************************************************************************* |
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* |
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* CPU_init_critical registers |
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* |
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* setup important registers |
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* setup memory timing |
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* |
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************************************************************************* |
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*/ |
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cpu_init_crit: |
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/* |
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* flush v4 I/D caches |
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*/ |
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mov r0, #0 |
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mcr p15, 0, r0, c7, c7, 0 /* flush v3/v4 cache */ |
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mcr p15, 0, r0, c8, c7, 0 /* flush v4 TLB */ |
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/* |
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* disable MMU stuff and caches |
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*/ |
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mrc p15, 0, r0, c1, c0, 0 |
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bic r0, r0, #0x00002300 @ clear bits 13, 9:8 (--V- --RS)
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bic r0, r0, #0x00000087 @ clear bits 7, 2:0 (B--- -CAM)
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orr r0, r0, #0x00000002 @ set bit 2 (A) Align
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orr r0, r0, #0x00001000 @ set bit 12 (I) I-Cache
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mcr p15, 0, r0, c1, c0, 0 |
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/* |
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* Go setup Memory and board specific bits prior to relocation. |
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*/ |
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mov ip, lr /* perserve link reg across call */ |
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bl lowlevel_init /* go setup pll,mux,memory */ |
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mov lr, ip /* restore link */ |
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mov pc, lr /* back to my caller */ |
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/* |
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************************************************************************* |
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* |
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* Interrupt handling |
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* |
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************************************************************************* |
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*/ |
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@
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@ IRQ stack frame.
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@
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#define S_FRAME_SIZE 72 |
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#define S_OLD_R0 68 |
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#define S_PSR 64 |
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#define S_PC 60 |
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#define S_LR 56 |
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#define S_SP 52 |
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#define S_IP 48 |
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#define S_FP 44 |
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#define S_R10 40 |
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#define S_R9 36 |
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#define S_R8 32 |
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#define S_R7 28 |
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#define S_R6 24 |
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#define S_R5 20 |
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#define S_R4 16 |
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#define S_R3 12 |
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#define S_R2 8 |
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#define S_R1 4 |
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#define S_R0 0 |
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#define MODE_SVC 0x13 |
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#define I_BIT 0x80 |
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/* |
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* use bad_save_user_regs for abort/prefetch/undef/swi ... |
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* use irq_save_user_regs / irq_restore_user_regs for IRQ/FIQ handling |
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*/ |
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.macro bad_save_user_regs
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sub sp, sp, #S_FRAME_SIZE @ carve out a frame on current user stack |
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stmia sp, {r0 - r12} @ Save user registers (now in svc mode) r0-r12
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ldr r2, IRQ_STACK_START_IN |
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ldmia r2, {r2 - r3} @ get values for "aborted" pc and cpsr (into parm regs)
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add r0, sp, #S_FRAME_SIZE @ grab pointer to old stack |
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add r5, sp, #S_SP |
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mov r1, lr |
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stmia r5, {r0 - r3} @ save sp_SVC, lr_SVC, pc, cpsr
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mov r0, sp @ save current stack into r0 (param register)
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.endm |
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.macro irq_save_user_regs
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sub sp, sp, #S_FRAME_SIZE |
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stmia sp, {r0 - r12} @ Calling r0-r12
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add r8, sp, #S_PC @ !!!! R8 NEEDS to be saved !!!! a reserved stack spot would be good. |
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stmdb r8, {sp, lr}^ @ Calling SP, LR
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str lr, [r8, #0] @ Save calling PC
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mrs r6, spsr |
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str r6, [r8, #4] @ Save CPSR
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str r0, [r8, #8] @ Save OLD_R0
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mov r0, sp |
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.endm |
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.macro irq_restore_user_regs
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ldmia sp, {r0 - lr}^ @ Calling r0 - lr
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mov r0, r0 |
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ldr lr, [sp, #S_PC] @ Get PC |
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add sp, sp, #S_FRAME_SIZE |
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subs pc, lr, #4 @ return & move spsr_svc into cpsr
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.endm |
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.macro get_bad_stack
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ldr r13, IRQ_STACK_START_IN |
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str lr, [r13] @ save caller lr in position 0 of saved stack
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mrs lr, spsr @ get the spsr
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str lr, [r13, #4] @ save spsr in position 1 of saved stack
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mov r13, #MODE_SVC @ prepare SVC-Mode |
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@ msr spsr_c, r13
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msr spsr, r13 @ switch modes, make sure moves will execute
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mov lr, pc @ capture return pc
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movs pc, lr @ jump to next instruction & switch modes.
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.endm |
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.macro get_irq_stack @ setup IRQ stack
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ldr sp, IRQ_STACK_START |
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.endm |
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.macro get_fiq_stack @ setup FIQ stack
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ldr sp, FIQ_STACK_START |
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.endm |
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/* |
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* exception handlers |
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*/ |
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.align 5
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undefined_instruction: |
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get_bad_stack |
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bad_save_user_regs |
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bl do_undefined_instruction |
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.align 5
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software_interrupt: |
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get_bad_stack |
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bad_save_user_regs |
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bl do_software_interrupt |
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.align 5
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prefetch_abort: |
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get_bad_stack |
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bad_save_user_regs |
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bl do_prefetch_abort |
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.align 5
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data_abort: |
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get_bad_stack |
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bad_save_user_regs |
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bl do_data_abort |
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.align 5
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not_used: |
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get_bad_stack |
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bad_save_user_regs |
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bl do_not_used |
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#ifdef CONFIG_USE_IRQ |
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.align 5
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irq: |
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get_irq_stack |
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irq_save_user_regs |
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bl do_irq |
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irq_restore_user_regs |
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.align 5
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fiq: |
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get_fiq_stack |
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/* someone ought to write a more effiction fiq_save_user_regs */ |
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irq_save_user_regs |
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bl do_fiq |
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irq_restore_user_regs |
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#else |
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.align 5
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irq: |
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get_bad_stack |
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bad_save_user_regs |
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bl do_irq |
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.align 5
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fiq: |
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get_bad_stack |
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bad_save_user_regs |
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bl do_fiq |
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#endif |
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.align 5
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.globl reset_cpu
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reset_cpu: |
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ldr r1, rstctl1 /* get clkm1 reset ctl */ |
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mov r3, #0x3 /* dsp_en + arm_rst = global reset */ |
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strh r3, [r1] /* force reset */ |
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mov r0, r0 |
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_loop_forever: |
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b _loop_forever |
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rstctl1: |
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.word 0xfffece10
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@ -1,104 +0,0 @@ |
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/*
|
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* (C) Copyright 2009 |
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* 2N Telekomunikace, <www.2n.cz> |
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* |
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* (C) Copyright 2003 |
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* Texas Instruments, <www.ti.com> |
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* |
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* (C) Copyright 2002 |
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* Sysgo Real-Time Solutions, GmbH <www.elinos.com> |
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* Marius Groeger <mgroeger@sysgo.de> |
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* |
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* (C) Copyright 2002 |
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* Sysgo Real-Time Solutions, GmbH <www.elinos.com> |
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* Alex Zuepke <azu@sysgo.de> |
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* |
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* (C) Copyright 2002 |
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* Gary Jennejohn, DENX Software Engineering, <garyj@denx.de> |
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* |
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* SPDX-License-Identifier: GPL-2.0+
|
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*/ |
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|
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#include <common.h> |
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#include <arm925t.h> |
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#include <configs/omap1510.h> |
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#include <asm/io.h> |
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|
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#define TIMER_LOAD_VAL 0xffffffff |
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#define TIMER_CLOCK (CONFIG_SYS_CLK_FREQ / (2 << CONFIG_SYS_PTV)) |
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|
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static uint32_t timestamp; |
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static uint32_t lastdec; |
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|
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/* nothing really to do with interrupts, just starts up a counter. */ |
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int timer_init (void) |
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{ |
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/* Start the decrementer ticking down from 0xffffffff */ |
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__raw_writel(TIMER_LOAD_VAL, CONFIG_SYS_TIMERBASE + LOAD_TIM); |
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__raw_writel(MPUTIM_ST | MPUTIM_AR | MPUTIM_CLOCK_ENABLE | |
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(CONFIG_SYS_PTV << MPUTIM_PTV_BIT), |
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CONFIG_SYS_TIMERBASE + CNTL_TIMER); |
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|
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/* init the timestamp and lastdec value */ |
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lastdec = __raw_readl(CONFIG_SYS_TIMERBASE + READ_TIM) / |
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(TIMER_CLOCK / CONFIG_SYS_HZ); |
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timestamp = 0; /* start "advancing" time stamp from 0 */ |
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return 0; |
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} |
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|
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/*
|
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* timer without interrupts |
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*/ |
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ulong get_timer (ulong base) |
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{ |
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return get_timer_masked () - base; |
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} |
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|
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/* delay x useconds AND preserve advance timestamp value */ |
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void __udelay (unsigned long usec) |
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{ |
||||
int32_t tmo = usec * (TIMER_CLOCK / 1000) / 1000; |
||||
uint32_t now, last = __raw_readl(CONFIG_SYS_TIMERBASE + READ_TIM); |
||||
|
||||
while (tmo > 0) { |
||||
now = __raw_readl(CONFIG_SYS_TIMERBASE + READ_TIM); |
||||
if (last < now) /* count down timer underflow */ |
||||
tmo -= TIMER_LOAD_VAL - now + last; |
||||
else |
||||
tmo -= last - now; |
||||
last = now; |
||||
} |
||||
} |
||||
|
||||
ulong get_timer_masked (void) |
||||
{ |
||||
uint32_t now = __raw_readl(CONFIG_SYS_TIMERBASE + READ_TIM) / |
||||
(TIMER_CLOCK / CONFIG_SYS_HZ); |
||||
if (lastdec < now) /* count down timer underflow */ |
||||
timestamp += TIMER_LOAD_VAL / (TIMER_CLOCK / CONFIG_SYS_HZ) - |
||||
now + lastdec; |
||||
else |
||||
timestamp += lastdec - now; |
||||
lastdec = now; |
||||
|
||||
return timestamp; |
||||
} |
||||
|
||||
/*
|
||||
* This function is derived from PowerPC code (read timebase as long long). |
||||
* On ARM it just returns the timer value. |
||||
*/ |
||||
unsigned long long get_ticks(void) |
||||
{ |
||||
return get_timer(0); |
||||
} |
||||
|
||||
/*
|
||||
* This function is derived from PowerPC code (timebase clock frequency). |
||||
* On ARM it returns the number of timer ticks per second. |
||||
*/ |
||||
ulong get_tbclk (void) |
||||
{ |
||||
return CONFIG_SYS_HZ; |
||||
} |
||||
@ -1,29 +0,0 @@ |
||||
#
|
||||
# (C) Copyright 2000-2006
|
||||
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
|
||||
#
|
||||
# SPDX-License-Identifier: GPL-2.0+
|
||||
#
|
||||
|
||||
include $(TOPDIR)/config.mk |
||||
|
||||
LIB = $(obj)lib$(BOARD).o
|
||||
|
||||
COBJS := omap1510innovator.o
|
||||
SOBJS := lowlevel_init.o
|
||||
|
||||
SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
|
||||
OBJS := $(addprefix $(obj),$(COBJS))
|
||||
SOBJS := $(addprefix $(obj),$(SOBJS))
|
||||
|
||||
$(LIB): $(obj).depend $(OBJS) $(SOBJS) |
||||
$(call cmd_link_o_target, $(OBJS) $(SOBJS))
|
||||
|
||||
#########################################################################
|
||||
|
||||
# defines $(obj).depend target
|
||||
include $(SRCTREE)/rules.mk |
||||
|
||||
sinclude $(obj).depend |
||||
|
||||
#########################################################################
|
||||
@ -1,25 +0,0 @@ |
||||
#
|
||||
# (C) Copyright 2002
|
||||
# Gary Jennejohn, DENX Software Engineering, <garyj@denx.de>
|
||||
# David Mueller, ELSOFT AG, <d.mueller@elsoft.ch>
|
||||
#
|
||||
# (C) Copyright 2003
|
||||
# Texas Instruments, <www.ti.com>
|
||||
# Kshitij Gupta <Kshitij@ti.com>
|
||||
#
|
||||
# TI Innovator board with OMAP1510 (ARM925T) cpu
|
||||
# see http://www.ti.com/ for more information on Texas Insturments
|
||||
#
|
||||
# Innovator has 1 bank of 256 MB SDRAM
|
||||
# Physical Address:
|
||||
# 1000'0000 to 2000'0000
|
||||
#
|
||||
#
|
||||
# Linux-Kernel is expected to be at 1000'8000, entry 1000'8000 (mem base + reserved)
|
||||
#
|
||||
# we load ourself to 1108'0000
|
||||
#
|
||||
#
|
||||
|
||||
|
||||
CONFIG_SYS_TEXT_BASE = 0x11080000
|
||||
@ -1,380 +0,0 @@ |
||||
/* |
||||
* Board specific setup info |
||||
* |
||||
* (C) Copyright 2003 |
||||
* Texas Instruments, <www.ti.com> |
||||
* |
||||
* -- Some bits of code used from rrload's head_OMAP1510.s -- |
||||
* Copyright (C) 2002 RidgeRun, Inc. |
||||
* |
||||
* SPDX-License-Identifier: GPL-2.0+ |
||||
*/ |
||||
|
||||
#include <config.h> |
||||
#include <version.h> |
||||
|
||||
#if defined(CONFIG_OMAP1510) |
||||
#include <./configs/omap1510.h> |
||||
#endif |
||||
|
||||
#define OMAP1510_CLKS ((1<<EN_XORPCK)|(1<<EN_PERCK)|(1<<EN_TIMCK)|(1<<EN_GPIOCK)) |
||||
|
||||
|
||||
_TEXT_BASE: |
||||
.word CONFIG_SYS_TEXT_BASE /* sdram load addr from config.mk */ |
||||
|
||||
.globl lowlevel_init
|
||||
lowlevel_init: |
||||
|
||||
/* |
||||
* Configure 1510 pins functions to match our board. |
||||
*/ |
||||
ldr r0, REG_PULL_DWN_CTRL_0 |
||||
ldr r1, VAL_PULL_DWN_CTRL_0 |
||||
str r1, [r0] |
||||
ldr r0, REG_PULL_DWN_CTRL_1 |
||||
ldr r1, VAL_PULL_DWN_CTRL_1 |
||||
str r1, [r0] |
||||
ldr r0, REG_PULL_DWN_CTRL_2 |
||||
ldr r1, VAL_PULL_DWN_CTRL_2 |
||||
str r1, [r0] |
||||
ldr r0, REG_PULL_DWN_CTRL_3 |
||||
ldr r1, VAL_PULL_DWN_CTRL_3 |
||||
str r1, [r0] |
||||
ldr r0, REG_FUNC_MUX_CTRL_4 |
||||
ldr r1, VAL_FUNC_MUX_CTRL_4 |
||||
str r1, [r0] |
||||
ldr r0, REG_FUNC_MUX_CTRL_5 |
||||
ldr r1, VAL_FUNC_MUX_CTRL_5 |
||||
str r1, [r0] |
||||
ldr r0, REG_FUNC_MUX_CTRL_6 |
||||
ldr r1, VAL_FUNC_MUX_CTRL_6 |
||||
str r1, [r0] |
||||
ldr r0, REG_FUNC_MUX_CTRL_7 |
||||
ldr r1, VAL_FUNC_MUX_CTRL_7 |
||||
str r1, [r0] |
||||
ldr r0, REG_FUNC_MUX_CTRL_8 |
||||
ldr r1, VAL_FUNC_MUX_CTRL_8 |
||||
str r1, [r0] |
||||
ldr r0, REG_FUNC_MUX_CTRL_9 |
||||
ldr r1, VAL_FUNC_MUX_CTRL_9 |
||||
str r1, [r0] |
||||
ldr r0, REG_FUNC_MUX_CTRL_A |
||||
ldr r1, VAL_FUNC_MUX_CTRL_A |
||||
str r1, [r0] |
||||
ldr r0, REG_FUNC_MUX_CTRL_B |
||||
ldr r1, VAL_FUNC_MUX_CTRL_B |
||||
str r1, [r0] |
||||
ldr r0, REG_FUNC_MUX_CTRL_C |
||||
ldr r1, VAL_FUNC_MUX_CTRL_C |
||||
str r1, [r0] |
||||
ldr r0, REG_FUNC_MUX_CTRL_D |
||||
ldr r1, VAL_FUNC_MUX_CTRL_D |
||||
str r1, [r0] |
||||
ldr r0, REG_VOLTAGE_CTRL_0 |
||||
ldr r1, VAL_VOLTAGE_CTRL_0 |
||||
str r1, [r0] |
||||
ldr r0, REG_TEST_DBG_CTRL_0 |
||||
ldr r1, VAL_TEST_DBG_CTRL_0 |
||||
str r1, [r0] |
||||
ldr r0, REG_MOD_CONF_CTRL_0 |
||||
ldr r1, VAL_MOD_CONF_CTRL_0 |
||||
str r1, [r0] |
||||
|
||||
/* Move to 1510 mode */ |
||||
ldr r0, REG_COMP_MODE_CTRL_0 |
||||
ldr r1, VAL_COMP_MODE_CTRL_0 |
||||
str r1, [r0] |
||||
|
||||
/* Set up Traffic Ctlr*/ |
||||
ldr r0, REG_TC_IMIF_PRIO |
||||
mov r1, #0x0 |
||||
str r1, [r0] |
||||
ldr r0, REG_TC_EMIFS_PRIO |
||||
str r1, [r0] |
||||
ldr r0, REG_TC_EMIFF_PRIO |
||||
str r1, [r0] |
||||
|
||||
ldr r0, REG_TC_EMIFS_CONFIG |
||||
ldr r1, [r0] |
||||
bic r1, r1, #0x08 /* clear the global power-down enable PDE bit */ |
||||
bic r1, r1, #0x01 /* write protect flash by clearing the WP bit */ |
||||
str r1, [r0] /* EMIFS GlB Configuration. (value 0x12 most likely) */ |
||||
|
||||
/* Setup some clock domains */ |
||||
ldr r1, =OMAP1510_CLKS |
||||
ldr r0, REG_ARM_IDLECT2 |
||||
strh r1, [r0] /* CLKM, Clock domain control. */ |
||||
|
||||
mov r1, #0x01 /* PER_EN bit */ |
||||
ldr r0, REG_ARM_RSTCT2 |
||||
strh r1, [r0] /* CLKM; Peripheral reset. */
|
||||
|
||||
/* Set CLKM to Sync-Scalable */ |
||||
/* I supposidly need to enable the dsp clock before switching */ |
||||
mov r1, #0x1000 |
||||
ldr r0, REG_ARM_SYSST |
||||
strh r1, [r0] |
||||
mov r0, #0x400 |
||||
1: |
||||
subs r0, r0, #0x1 /* wait for any bubbles to finish */ |
||||
bne 1b |
||||
|
||||
ldr r1, VAL_ARM_CKCTL /* use 12Mhz ref, PER must be <= 50Mhz so /2 */ |
||||
ldr r0, REG_ARM_CKCTL |
||||
strh r1, [r0] |
||||
|
||||
/* setup DPLL 1 */ |
||||
ldr r1, VAL_DPLL1_CTL |
||||
ldr r0, REG_DPLL1_CTL |
||||
strh r1, [r0] |
||||
ands r1, r1, #0x10 /* Check if PLL is enabled. */ |
||||
beq lock_end /* Do not look for lock if BYPASS selected */ |
||||
2: |
||||
ldrh r1, [r0] |
||||
ands r1, r1, #0x01 /* Check the LOCK bit. */ |
||||
beq 2b /* ...loop until bit goes hi. */ |
||||
lock_end: |
||||
|
||||
/* Set memory timings corresponding to the new clock speed */ |
||||
|
||||
/* Check execution location to determine current execution location |
||||
* and branch to appropriate initialization code. |
||||
*/ |
||||
mov r0, #0x10000000 /* Load physical SDRAM base. */ |
||||
mov r1, pc /* Get current execution location. */ |
||||
/* Zero all but top 6 bits of PC, as they alone detect whether an |
||||
* address is in the range 0x1000:0000-0x13ff:ffff, the 64M sized |
||||
* valid range for SDRAM on the OMAP 1510/5910. |
||||
*/ |
||||
and r1, r1, #0xfc000000 |
||||
cmp r1, r0 /* Compare. */ |
||||
beq skip_sdram /* Skip over EMIF-fast initialization |
||||
* if running from SDRAM. |
||||
*/ |
||||
|
||||
/* |
||||
* Delay for SDRAM initialization. |
||||
*/ |
||||
mov r3, #0x1800 /* value should be checked */ |
||||
3: |
||||
subs r3, r3, #0x1 /* Decrement count */ |
||||
bne 3b |
||||
|
||||
/* |
||||
* Set SDRAM control values. Disable refresh before MRS command. |
||||
*/ |
||||
ldr r0, VAL_TC_EMIFF_SDRAM_CONFIG /* get good value */ |
||||
bic r3, r0, #0xC /* (BIT3|BIT2) ulConfig with auto-refresh disabled. */ |
||||
orr r3, r3, #0x8000000 /* (BIT27) Disable CLK when Power down or Self-Refresh */ |
||||
orr r3, r3, #0x4000000 /* BIT26 Power Down Enable */ |
||||
ldr r2, REG_TC_EMIFF_SDRAM_CONFIG /* Point to configuration register. */ |
||||
str r3, [r2] /* Store the passed value with AR disabled. */ |
||||
|
||||
ldr r1, VAL_TC_EMIFF_MRS /* get MRS value */ |
||||
ldr r2, REG_TC_EMIFF_MRS /* Point to MRS register. */ |
||||
str r1, [r2] /* Store the passed value.*/ |
||||
|
||||
ldr r2, REG_TC_EMIFF_SDRAM_CONFIG /* Point to configuration register. */ |
||||
str r0, [r2] /* Store the passed value. */ |
||||
|
||||
/* |
||||
* Delay for SDRAM initialization. |
||||
*/ |
||||
mov r3, #0x1800 |
||||
4: |
||||
subs r3, r3, #1 /* Decrement count. */ |
||||
bne 4b |
||||
|
||||
skip_sdram: |
||||
|
||||
/* slow interface */ |
||||
ldr r1, VAL_TC_EMIFS_CS0_CONFIG |
||||
ldr r0, REG_TC_EMIFS_CS0_CONFIG |
||||
str r1, [r0] /* Chip Select 0 */ |
||||
ldr r1, VAL_TC_EMIFS_CS1_CONFIG |
||||
ldr r0, REG_TC_EMIFS_CS1_CONFIG |
||||
str r1, [r0] /* Chip Select 1 */ |
||||
ldr r1, VAL_TC_EMIFS_CS2_CONFIG |
||||
ldr r0, REG_TC_EMIFS_CS2_CONFIG |
||||
str r1, [r0] /* Chip Select 2 */ |
||||
ldr r1, VAL_TC_EMIFS_CS3_CONFIG |
||||
ldr r0, REG_TC_EMIFS_CS3_CONFIG |
||||
str r1, [r0] /* Chip Select 3 */ |
||||
|
||||
/* Next, Enable the RS232 Line Drivers in the FPGA. */ |
||||
/* Also, power on the audio CODEC's amplifier here, */ |
||||
/* which will make a noise on the audio output. */ |
||||
/* This is done here instead of in the kernel so there */ |
||||
/* isn't a loud popping noise at the start of each */ |
||||
/* song. */ |
||||
/* Also, disable the CODEC's clocks. */ |
||||
/* omap1510-HelenP1 [specific] */ |
||||
|
||||
ldr r0, REG_FPGA_POWER |
||||
mov r1, #0 |
||||
ldr r2, REG_FPGA_DIP_SWITCH |
||||
ldrb r3, [r2] |
||||
cmp r3, #0x8 |
||||
movne r1, #0x62 /* Enable the RS232 Line Drivers in the EPLD */ |
||||
strb r1, [r0] |
||||
ldr r0, REG_FPGA_AUDIO |
||||
mov r1, #0x0 /* Disable sound driver (CODEC clocks) */ |
||||
strb r1, [r0] |
||||
|
||||
/* back to arch calling code */ |
||||
mov pc, lr |
||||
|
||||
/* the literal pools origin */ |
||||
.ltorg |
||||
|
||||
/* OMAP configuration registers */ |
||||
REG_FUNC_MUX_CTRL_0: /* 32 bits */ |
||||
.word 0xfffe1000
|
||||
REG_FUNC_MUX_CTRL_1: /* 32 bits */ |
||||
.word 0xfffe1004
|
||||
REG_FUNC_MUX_CTRL_2: /* 32 bits */ |
||||
.word 0xfffe1008
|
||||
REG_COMP_MODE_CTRL_0: /* 32 bits */ |
||||
.word 0xfffe100c
|
||||
REG_FUNC_MUX_CTRL_3: /* 32 bits */ |
||||
.word 0xfffe1010
|
||||
REG_FUNC_MUX_CTRL_4: /* 32 bits */ |
||||
.word 0xfffe1014
|
||||
REG_FUNC_MUX_CTRL_5: /* 32 bits */ |
||||
.word 0xfffe1018
|
||||
REG_FUNC_MUX_CTRL_6: /* 32 bits */ |
||||
.word 0xfffe101c
|
||||
REG_FUNC_MUX_CTRL_7: /* 32 bits */ |
||||
.word 0xfffe1020
|
||||
REG_FUNC_MUX_CTRL_8: /* 32 bits */ |
||||
.word 0xfffe1024
|
||||
REG_FUNC_MUX_CTRL_9: /* 32 bits */ |
||||
.word 0xfffe1028
|
||||
REG_FUNC_MUX_CTRL_A: /* 32 bits */ |
||||
.word 0xfffe102C
|
||||
REG_FUNC_MUX_CTRL_B: /* 32 bits */ |
||||
.word 0xfffe1030
|
||||
REG_FUNC_MUX_CTRL_C: /* 32 bits */ |
||||
.word 0xfffe1034
|
||||
REG_FUNC_MUX_CTRL_D: /* 32 bits */ |
||||
.word 0xfffe1038
|
||||
REG_PULL_DWN_CTRL_0: /* 32 bits */ |
||||
.word 0xfffe1040
|
||||
REG_PULL_DWN_CTRL_1: /* 32 bits */ |
||||
.word 0xfffe1044
|
||||
REG_PULL_DWN_CTRL_2: /* 32 bits */ |
||||
.word 0xfffe1048
|
||||
REG_PULL_DWN_CTRL_3: /* 32 bits */ |
||||
.word 0xfffe104c
|
||||
REG_VOLTAGE_CTRL_0: /* 32 bits */ |
||||
.word 0xfffe1060
|
||||
REG_TEST_DBG_CTRL_0: /* 32 bits */ |
||||
.word 0xfffe1070
|
||||
REG_MOD_CONF_CTRL_0: /* 32 bits */ |
||||
.word 0xfffe1080
|
||||
REG_TC_IMIF_PRIO: /* 32 bits */ |
||||
.word 0xfffecc00
|
||||
REG_TC_EMIFS_PRIO: /* 32 bits */ |
||||
.word 0xfffecc04
|
||||
REG_TC_EMIFF_PRIO: /* 32 bits */ |
||||
.word 0xfffecc08
|
||||
REG_TC_EMIFS_CONFIG: /* 32 bits */ |
||||
.word 0xfffecc0c
|
||||
REG_TC_EMIFS_CS0_CONFIG: /* 32 bits */ |
||||
.word 0xfffecc10
|
||||
REG_TC_EMIFS_CS1_CONFIG: /* 32 bits */ |
||||
.word 0xfffecc14
|
||||
REG_TC_EMIFS_CS2_CONFIG: /* 32 bits */ |
||||
.word 0xfffecc18
|
||||
REG_TC_EMIFS_CS3_CONFIG: /* 32 bits */ |
||||
.word 0xfffecc1c
|
||||
REG_TC_EMIFF_SDRAM_CONFIG: /* 32 bits */ |
||||
.word 0xfffecc20
|
||||
REG_TC_EMIFF_MRS: /* 32 bits */ |
||||
.word 0xfffecc24
|
||||
/* MPU clock/reset/power mode control registers */ |
||||
REG_ARM_CKCTL: /* 16 bits */ |
||||
.word 0xfffece00
|
||||
REG_ARM_IDLECT2: /* 16 bits */ |
||||
.word 0xfffece08
|
||||
REG_ARM_RSTCT2: /* 16 bits */ |
||||
.word 0xfffece14
|
||||
REG_ARM_SYSST: /* 16 bits */ |
||||
.word 0xfffece18
|
||||
/* DPLL control registers */ |
||||
REG_DPLL1_CTL: /* 16 bits */ |
||||
.word 0xfffecf00
|
||||
/* identification code register */ |
||||
REG_IDCODE: /* 32 bits */ |
||||
.word 0xfffed404
|
||||
|
||||
/* Innovator specific */ |
||||
REG_FPGA_LED_DIGIT: /* 8 bits (not used on Innovator) */ |
||||
.word 0x08000003
|
||||
REG_FPGA_POWER: /* 8 bits */ |
||||
.word 0x08000005
|
||||
REG_FPGA_AUDIO: /* 8 bits (not used on Innovator) */ |
||||
.word 0x0800000c
|
||||
REG_FPGA_DIP_SWITCH: /* 8 bits (not used on Innovator) */ |
||||
.word 0x0800000e
|
||||
|
||||
VAL_COMP_MODE_CTRL_0: |
||||
.word 0x0000eaef
|
||||
VAL_FUNC_MUX_CTRL_4: |
||||
.word 0x00000000
|
||||
VAL_FUNC_MUX_CTRL_5: |
||||
.word 0x00000000
|
||||
VAL_FUNC_MUX_CTRL_6: |
||||
.word 0x00000001
|
||||
VAL_FUNC_MUX_CTRL_7: |
||||
.word 0x00000000
|
||||
VAL_FUNC_MUX_CTRL_8: |
||||
.word 0x10001200
|
||||
VAL_FUNC_MUX_CTRL_9: |
||||
.word 0x01201012
|
||||
VAL_FUNC_MUX_CTRL_A: |
||||
.word 0x00000248
|
||||
VAL_FUNC_MUX_CTRL_B: |
||||
.word 0x00000248
|
||||
VAL_FUNC_MUX_CTRL_C: |
||||
.word 0x09000000
|
||||
VAL_FUNC_MUX_CTRL_D: |
||||
.word 0x00000000
|
||||
VAL_PULL_DWN_CTRL_0: |
||||
.word 0x11a10000
|
||||
VAL_PULL_DWN_CTRL_1: |
||||
.word 0x2e047fff
|
||||
VAL_PULL_DWN_CTRL_2: |
||||
.word 0xffd603a6
|
||||
VAL_PULL_DWN_CTRL_3: |
||||
.word 0x00003e03
|
||||
VAL_VOLTAGE_CTRL_0: |
||||
.word 0x00000007
|
||||
VAL_TEST_DBG_CTRL_0: |
||||
/* See Errata 4.13, This works around a SRAM bug, for chips below ES2.5 . |
||||
* This slows down internal SRAM accesses. |
||||
*/ |
||||
.word 0x00000007
|
||||
VAL_MOD_CONF_CTRL_0: |
||||
.word 0x0b000008
|
||||
VAL_ARM_CKCTL: |
||||
.word 0x010f
|
||||
VAL_DPLL1_CTL: |
||||
.word 0x2710
|
||||
VAL_TC_EMIFS_CS1_CONFIG_PRELIM: |
||||
.word 0x00001149
|
||||
VAL_TC_EMIFS_CS2_CONFIG_PRELIM: |
||||
.word 0x00004158
|
||||
VAL_TC_EMIFS_CS0_CONFIG: |
||||
.word 0x002130b0
|
||||
VAL_TC_EMIFS_CS1_CONFIG: |
||||
.word 0x0000f559
|
||||
VAL_TC_EMIFS_CS2_CONFIG: |
||||
.word 0x000055f0
|
||||
VAL_TC_EMIFS_CS3_CONFIG: |
||||
.word 0x00003331
|
||||
VAL_TC_EMIFF_SDRAM_CONFIG: |
||||
.word 0x010290fc
|
||||
VAL_TC_EMIFF_MRS: |
||||
.word 0x00000027
|
||||
@ -1,125 +0,0 @@ |
||||
/*
|
||||
* (C) Copyright 2002 |
||||
* Sysgo Real-Time Solutions, GmbH <www.elinos.com> |
||||
* Marius Groeger <mgroeger@sysgo.de> |
||||
* |
||||
* (C) Copyright 2002 |
||||
* David Mueller, ELSOFT AG, <d.mueller@elsoft.ch> |
||||
* |
||||
* (C) Copyright 2003 |
||||
* Texas Instruments, <www.ti.com> |
||||
* Kshitij Gupta <Kshitij@ti.com> |
||||
* |
||||
* SPDX-License-Identifier: GPL-2.0+ |
||||
*/ |
||||
|
||||
#include <common.h> |
||||
#include <netdev.h> |
||||
|
||||
DECLARE_GLOBAL_DATA_PTR; |
||||
|
||||
static void flash__init (void); |
||||
static void ether__init (void); |
||||
|
||||
static inline void delay (unsigned long loops) |
||||
{ |
||||
__asm__ volatile ("1:\n" |
||||
"subs %0, %1, #1\n" |
||||
"bne 1b":"=r" (loops):"0" (loops)); |
||||
} |
||||
|
||||
/*
|
||||
* Miscellaneous platform dependent initialisations |
||||
*/ |
||||
|
||||
int board_init (void) |
||||
{ |
||||
/* arch number of OMAP 1510-Board */ |
||||
gd->bd->bi_arch_number = MACH_TYPE_OMAP_INNOVATOR; |
||||
|
||||
/* adress of boot parameters */ |
||||
gd->bd->bi_boot_params = 0x10000100; |
||||
|
||||
/* kk - this speeds up your boot a quite a bit. However to make it
|
||||
* work, you need make sure your kernel startup flush bug is fixed. |
||||
* ... rkw ... |
||||
*/ |
||||
icache_enable (); |
||||
|
||||
flash__init (); |
||||
ether__init (); |
||||
return 0; |
||||
} |
||||
|
||||
|
||||
int misc_init_r (void) |
||||
{ |
||||
/* volatile ushort *gdir = (ushort *) (GPIO_DIR_CONTROL_REG); */ |
||||
/* volatile ushort *mdir = (ushort *) (MPUIO_DIR_CONTROL_REG); */ |
||||
|
||||
/* setup gpio direction to match board (no floats!) */ |
||||
/**gdir = 0xCFF9; */ |
||||
/**mdir = 0x103F; */ |
||||
|
||||
return (0); |
||||
} |
||||
|
||||
/******************************
|
||||
Routine: |
||||
Description: |
||||
******************************/ |
||||
static void flash__init (void) |
||||
{ |
||||
#define CS0_CHIP_SELECT_REG 0xfffecc10 |
||||
#define CS3_CHIP_SELECT_REG 0xfffecc1c |
||||
#define EMIFS_GlB_Config_REG 0xfffecc0c |
||||
|
||||
{ |
||||
unsigned int regval; |
||||
|
||||
regval = *((volatile unsigned int *) EMIFS_GlB_Config_REG); |
||||
regval = regval | 0x0001; /* Turn off write protection for flash devices. */ |
||||
if (regval & 0x0002) { |
||||
regval = regval & 0xfffd; /* Swap CS0 and CS3 so that flash is visible at 0x0 and eeprom at 0x0c000000. */ |
||||
/* If, instead, you want to reference flash at 0x0c000000, then it seemed the following were necessary. */ |
||||
/* *((volatile unsigned int *)CS0_CHIP_SELECT_REG) = 0x202090; / * Overrides head.S setting of 0x212090 */ |
||||
/* *((volatile unsigned int *)CS3_CHIP_SELECT_REG) = 0x202090; / * Let's flash chips be fully functional. */ |
||||
} |
||||
*((volatile unsigned int *) EMIFS_GlB_Config_REG) = regval; |
||||
} |
||||
} |
||||
|
||||
|
||||
/******************************
|
||||
Routine: |
||||
Description: |
||||
******************************/ |
||||
static void ether__init (void) |
||||
{ |
||||
#define ETH_CONTROL_REG 0x0800000b |
||||
/* take the Ethernet controller out of reset and wait
|
||||
* for the EEPROM load to complete. |
||||
*/ |
||||
*((volatile unsigned char *) ETH_CONTROL_REG) &= ~0x01; |
||||
udelay (3); |
||||
} |
||||
|
||||
|
||||
int dram_init (void) |
||||
{ |
||||
gd->bd->bi_dram[0].start = PHYS_SDRAM_1; |
||||
gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE; |
||||
|
||||
return 0; |
||||
} |
||||
|
||||
#ifdef CONFIG_CMD_NET |
||||
int board_eth_init(bd_t *bis) |
||||
{ |
||||
int rc = 0; |
||||
#ifdef CONFIG_LAN91C96 |
||||
rc = lan91c96_initialize(0, CONFIG_LAN91C96_BASE); |
||||
#endif |
||||
return rc; |
||||
} |
||||
#endif |
||||
@ -1,11 +0,0 @@ |
||||
/************************************************
|
||||
* NAME : arm925t.h |
||||
* Version : 23 June 2003 * |
||||
************************************************/ |
||||
|
||||
#ifndef __ARM925T_H__ |
||||
#define __ARM925T_H__ |
||||
|
||||
void archflashwp(void *archdata, int wp); |
||||
|
||||
#endif /*__ARM925T_H__*/ |
||||
@ -1,166 +0,0 @@ |
||||
/*
|
||||
* (C) Copyright 2003 |
||||
* Texas Instruments. |
||||
* Kshitij Gupta <kshitij@ti.com> |
||||
* Configuation settings for the TI OMAP Innovator board. |
||||
* |
||||
* SPDX-License-Identifier: GPL-2.0+
|
||||
*/ |
||||
|
||||
#ifndef __CONFIG_H |
||||
#define __CONFIG_H |
||||
|
||||
/*
|
||||
* High Level Configuration Options |
||||
* (easy to change) |
||||
*/ |
||||
#define CONFIG_ARM925T 1 /* This is an arm925t CPU */ |
||||
#define CONFIG_OMAP 1 /* in a TI OMAP core */ |
||||
#define CONFIG_OMAP1510 1 /* which is in a 1510 (helen) */ |
||||
#define CONFIG_INNOVATOROMAP1510 1 /* a Innovator Board */ |
||||
|
||||
/* input clock of PLL */ |
||||
#define CONFIG_SYS_CLK_FREQ 12000000 /* the OMAP1510 Innovator has 12MHz input clock */ |
||||
|
||||
#define CONFIG_MISC_INIT_R |
||||
|
||||
#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */ |
||||
#define CONFIG_SETUP_MEMORY_TAGS 1 |
||||
#define CONFIG_INITRD_TAG 1 |
||||
|
||||
/*
|
||||
* Size of malloc() pool |
||||
*/ |
||||
#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 128*1024) |
||||
|
||||
/*
|
||||
* Hardware drivers |
||||
*/ |
||||
/*
|
||||
#define CONFIG_DRIVER_SMC9196 |
||||
#define CONFIG_SMC9196_BASE 0x08000300 |
||||
#define CONFIG_SMC9196_EXT_PHY |
||||
*/ |
||||
#define CONFIG_LAN91C96 |
||||
#define CONFIG_LAN91C96_BASE 0x08000300 |
||||
#define CONFIG_LAN91C96_EXT_PHY |
||||
|
||||
/*
|
||||
* NS16550 Configuration |
||||
*/ |
||||
#define CONFIG_SYS_NS16550 |
||||
#define CONFIG_SYS_NS16550_SERIAL |
||||
#define CONFIG_SYS_NS16550_REG_SIZE (-4) |
||||
#define CONFIG_SYS_NS16550_CLK (CONFIG_SYS_CLK_FREQ) /* can be 12M/32Khz or 48Mhz */ |
||||
#define CONFIG_SYS_NS16550_COM1 0xfffb0000 /* uart1, bluetooth uart on helen */ |
||||
|
||||
/*
|
||||
* select serial console configuration |
||||
*/ |
||||
#define CONFIG_SERIAL1 1 /* we use SERIAL 1 on OMAP1510 Innovator */ |
||||
|
||||
/* allow to overwrite serial and ethaddr */ |
||||
#define CONFIG_ENV_OVERWRITE |
||||
|
||||
#define CONFIG_ENV_OVERWRITE |
||||
#define CONFIG_CONS_INDEX 1 |
||||
#define CONFIG_BAUDRATE 115200 |
||||
|
||||
/*
|
||||
* Command line configuration. |
||||
*/ |
||||
#include <config_cmd_default.h> |
||||
|
||||
#define CONFIG_CMD_DHCP |
||||
|
||||
|
||||
/*
|
||||
* BOOTP options |
||||
*/ |
||||
#define CONFIG_BOOTP_SUBNETMASK |
||||
#define CONFIG_BOOTP_GATEWAY |
||||
#define CONFIG_BOOTP_HOSTNAME |
||||
#define CONFIG_BOOTP_BOOTPATH |
||||
|
||||
|
||||
#include <configs/omap1510.h> |
||||
|
||||
#define CONFIG_BOOTDELAY 3 |
||||
#define CONFIG_BOOTARGS "console=ttyS0,115200n8 noinitrd root=/dev/nfs ip=bootp" |
||||
#define CONFIG_BOOTCOMMAND "bootp;tftp;bootm" |
||||
#define CONFIG_SYS_AUTOLOAD "n" /* No autoload */ |
||||
|
||||
#if defined(CONFIG_CMD_KGDB) |
||||
#define CONFIG_KGDB_BAUDRATE 115200 /* speed to run kgdb serial port */ |
||||
/* what's this ? it's not used anywhere */ |
||||
#define CONFIG_KGDB_SER_INDEX 1 /* which serial port to use */ |
||||
#endif |
||||
|
||||
/*
|
||||
* Miscellaneous configurable options |
||||
*/ |
||||
#define CONFIG_SYS_LONGHELP /* undef to save memory */ |
||||
#define CONFIG_SYS_PROMPT "OMAP1510 Innovator # " /* Monitor Command Prompt */ |
||||
#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ |
||||
#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ |
||||
#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ |
||||
#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ |
||||
|
||||
#define CONFIG_SYS_MEMTEST_START 0x10000000 /* memtest works on */ |
||||
#define CONFIG_SYS_MEMTEST_END 0x12000000 /* 32 MB in DRAM */ |
||||
|
||||
#define CONFIG_SYS_LOAD_ADDR 0x10000000 /* default load address */ |
||||
|
||||
/* The 1510 has 3 timers, they can be driven by the RefClk (12MHz) or by DPLL1.
|
||||
* This time is further subdivided by a local divisor. |
||||
*/ |
||||
#define CONFIG_SYS_TIMERBASE OMAP1510_TIMER1_BASE /* use timer 1 */ |
||||
#define CONFIG_SYS_PTV 2 /* Divisor: 2^(PTV+1) => 8 */ |
||||
#define CONFIG_SYS_HZ 1000 |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Physical Memory Map |
||||
*/ |
||||
#define CONFIG_NR_DRAM_BANKS 1 /* we have 1 bank of DRAM */ |
||||
#define PHYS_SDRAM_1 0x10000000 /* SDRAM Bank #1 */ |
||||
#define PHYS_SDRAM_1_SIZE 0x02000000 /* 32 MB */ |
||||
|
||||
#define PHYS_FLASH_1 0x00000000 /* Flash Bank #1 */ |
||||
|
||||
#define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1 |
||||
|
||||
#define PHYS_SRAM 0x20000000 |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* FLASH and environment organization |
||||
*/ |
||||
#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max number of memory banks */ |
||||
#define PHYS_FLASH_SIZE 0x01000000 /* 16MB */ |
||||
#define PHYS_FLASH_SECT_SIZE (128*1024) /* Size of a sector (128kB) */ |
||||
#define CONFIG_SYS_MAX_FLASH_SECT (128) /* max number of sectors on one chip */ |
||||
#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + PHYS_FLASH_SECT_SIZE) |
||||
#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE /* Monitor at beginning of flash */ |
||||
#define CONFIG_SYS_MONITOR_LEN PHYS_FLASH_SECT_SIZE /* Reserve 1 sector */ |
||||
#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE + PHYS_FLASH_SIZE } |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* FLASH driver setup |
||||
*/ |
||||
#define CONFIG_SYS_FLASH_CFI 1 /* Flash memory is CFI compliant */ |
||||
#define CONFIG_FLASH_CFI_DRIVER 1 /* Use drivers/mtd/cfi_flash.c */ |
||||
#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 /* Use buffered writes (~10x faster) */ |
||||
#define CONFIG_SYS_FLASH_PROTECTION 1 /* Use hardware sector protection */ |
||||
|
||||
/* timeout values are in ticks */ |
||||
#define CONFIG_SYS_FLASH_ERASE_TOUT (20*CONFIG_SYS_HZ) /* Timeout for Flash Erase */ |
||||
#define CONFIG_SYS_FLASH_WRITE_TOUT (20*CONFIG_SYS_HZ) /* Timeout for Flash Write */ |
||||
|
||||
#define CONFIG_ENV_IS_IN_FLASH 1 |
||||
#define CONFIG_ENV_SECT_SIZE PHYS_FLASH_SECT_SIZE /* Total Size of Environment Sector */ |
||||
#define CONFIG_ENV_SIZE CONFIG_ENV_SECT_SIZE |
||||
#define CONFIG_ENV_OFFSET ( CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN ) /* Environment after Monitor */ |
||||
|
||||
#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 |
||||
#define CONFIG_SYS_INIT_SP_ADDR PHYS_SRAM |
||||
|
||||
#endif /* __CONFIG_H */ |
||||
Loading…
Reference in new issue