parent
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0621f6f9d3
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/*
|
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* (C) Copyright 2003-2004 |
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* Gary Jennejohn, DENX Software Engineering, gj@denx.de. |
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* Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com |
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* |
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* See file CREDITS for list of people who contributed to this |
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* project. |
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* |
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* This program is free software; you can redistribute it and/or |
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* modify it under the terms of the GNU General Public License as |
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* published by the Free Software Foundation; either version 2 of |
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* the License, or (at your option) any later version. |
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* |
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* This program is distributed in the hope that it will be useful, |
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* but WITHOUT ANY WARRANTY; without even the implied warranty of |
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
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* GNU General Public License for more details. |
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* |
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* You should have received a copy of the GNU General Public License |
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* along with this program; if not, write to the Free Software |
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
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* MA 02111-1307 USA |
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*/ |
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#include <common.h> |
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#include <command.h> |
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#include <image.h> |
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#include <asm/byteorder.h> |
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#include <linux/mtd/nand.h> |
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#include <fat.h> |
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#include "auto_update.h" |
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#ifdef CONFIG_AUTO_UPDATE |
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#if !(CONFIG_COMMANDS & CFG_CMD_FAT) |
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#error "must define CFG_CMD_FAT" |
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#endif |
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extern au_image_t au_image[]; |
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extern int N_AU_IMAGES; |
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#define AU_DEBUG |
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#undef AU_DEBUG |
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#undef debug |
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#ifdef AU_DEBUG |
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#define debug(fmt,args...) printf (fmt ,##args) |
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#else |
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#define debug(fmt,args...) |
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#endif /* AU_DEBUG */ |
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|
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#define LOAD_ADDR ((unsigned char *)0x100000) /* where to load files into memory */ |
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#define MAX_LOADSZ 0x1e00000 |
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|
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/* externals */ |
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extern int fat_register_device(block_dev_desc_t *, int); |
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extern int file_fat_detectfs(void); |
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extern long file_fat_read(const char *, void *, unsigned long); |
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long do_fat_read (const char *filename, void *buffer, unsigned long maxsize, int dols); |
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#ifdef CONFIG_VFD |
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extern int trab_vfd (ulong); |
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extern int transfer_pic(unsigned char, unsigned char *, int, int); |
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#endif |
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extern int flash_sect_erase(ulong, ulong); |
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extern int flash_sect_protect (int, ulong, ulong); |
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extern int flash_write (uchar *, ulong, ulong); |
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/* change char* to void* to shutup the compiler */ |
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extern block_dev_desc_t *get_dev (char*, int); |
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|
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#if (CONFIG_COMMANDS & CFG_CMD_NAND) |
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/* references to names in cmd_nand.c */ |
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#define NANDRW_READ 0x01 |
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#define NANDRW_WRITE 0x00 |
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#define NANDRW_JFFS2 0x02 |
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#define NANDRW_JFFS2_SKIP 0x04 |
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extern struct nand_chip nand_dev_desc[]; |
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extern int nand_rw(struct nand_chip* nand, int cmd, size_t start, size_t len, |
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size_t * retlen, u_char * buf); |
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extern int nand_erase(struct nand_chip* nand, size_t ofs, size_t len, int clean); |
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#endif /* (CONFIG_COMMANDS & CFG_CMD_NAND) */ |
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extern block_dev_desc_t ide_dev_desc[CFG_IDE_MAXDEVICE]; |
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int au_check_cksum_valid(int i, long nbytes) |
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{ |
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image_header_t *hdr; |
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unsigned long checksum; |
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hdr = (image_header_t *)LOAD_ADDR; |
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if ((au_image[i].type == AU_FIRMWARE) && (au_image[i].size != ntohl(hdr->ih_size))) { |
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printf ("Image %s has wrong size\n", au_image[i].name); |
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return -1; |
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} |
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if (nbytes != (sizeof(*hdr) + ntohl(hdr->ih_size))) { |
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printf ("Image %s bad total SIZE\n", au_image[i].name); |
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return -1; |
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} |
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/* check the data CRC */ |
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checksum = ntohl(hdr->ih_dcrc); |
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if (crc32 (0, (char *)(LOAD_ADDR + sizeof(*hdr)), ntohl(hdr->ih_size)) |
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!= checksum) { |
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printf ("Image %s bad data checksum\n", au_image[i].name); |
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return -1; |
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} |
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return 0; |
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} |
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int au_check_header_valid(int i, long nbytes) |
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{ |
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image_header_t *hdr; |
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unsigned long checksum; |
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hdr = (image_header_t *)LOAD_ADDR; |
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/* check the easy ones first */ |
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#undef CHECK_VALID_DEBUG |
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#ifdef CHECK_VALID_DEBUG |
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printf("magic %#x %#x ", ntohl(hdr->ih_magic), IH_MAGIC); |
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printf("arch %#x %#x ", hdr->ih_arch, IH_CPU_PPC); |
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printf("size %#x %#lx ", ntohl(hdr->ih_size), nbytes); |
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printf("type %#x %#x ", hdr->ih_type, IH_TYPE_KERNEL); |
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#endif |
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if (nbytes < sizeof(*hdr)) |
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{ |
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printf ("Image %s bad header SIZE\n", au_image[i].name); |
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return -1; |
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} |
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if (ntohl(hdr->ih_magic) != IH_MAGIC || hdr->ih_arch != IH_CPU_PPC) |
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{ |
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printf ("Image %s bad MAGIC or ARCH\n", au_image[i].name); |
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return -1; |
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} |
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/* check the hdr CRC */ |
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checksum = ntohl(hdr->ih_hcrc); |
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hdr->ih_hcrc = 0; |
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if (crc32 (0, (char *)hdr, sizeof(*hdr)) != checksum) { |
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printf ("Image %s bad header checksum\n", au_image[i].name); |
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return -1; |
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} |
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hdr->ih_hcrc = htonl(checksum); |
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/* check the type - could do this all in one gigantic if() */ |
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if ((au_image[i].type == AU_FIRMWARE) && (hdr->ih_type != IH_TYPE_FIRMWARE)) { |
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printf ("Image %s wrong type\n", au_image[i].name); |
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return -1; |
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} |
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if ((au_image[i].type == AU_SCRIPT) && (hdr->ih_type != IH_TYPE_SCRIPT)) { |
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printf ("Image %s wrong type\n", au_image[i].name); |
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return -1; |
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} |
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/* recycle checksum */ |
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checksum = ntohl(hdr->ih_size); |
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#if 0 /* test-only */
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/* for kernel and app the image header must also fit into flash */ |
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if (idx != IDX_DISK) |
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checksum += sizeof(*hdr); |
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/* check the size does not exceed space in flash. HUSH scripts */ |
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/* all have ausize[] set to 0 */ |
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if ((ausize[idx] != 0) && (ausize[idx] < checksum)) { |
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printf ("Image %s is bigger than FLASH\n", au_image[i].name); |
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return -1; |
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} |
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#endif |
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return 0; |
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} |
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int au_do_update(int i, long sz) |
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{ |
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image_header_t *hdr; |
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char *addr; |
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long start, end; |
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int off, rc; |
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uint nbytes; |
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int k; |
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#if (CONFIG_COMMANDS & CFG_CMD_NAND) |
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int total; |
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#endif |
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hdr = (image_header_t *)LOAD_ADDR; |
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switch (au_image[i].type) { |
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case AU_SCRIPT: |
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printf("Executing script %s\n", au_image[i].name); |
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/* execute a script */ |
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if (hdr->ih_type == IH_TYPE_SCRIPT) { |
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addr = (char *)((char *)hdr + sizeof(*hdr)); |
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/* stick a NULL at the end of the script, otherwise */ |
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/* parse_string_outer() runs off the end. */ |
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addr[ntohl(hdr->ih_size)] = 0; |
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addr += 8; |
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/*
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* Replace cr/lf with ; |
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*/ |
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k = 0; |
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while (addr[k] != 0) { |
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if ((addr[k] == 10) || (addr[k] == 13)) { |
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addr[k] = ';'; |
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} |
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k++; |
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} |
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run_command(addr, 0); |
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return 0; |
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} |
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break; |
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case AU_FIRMWARE: |
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case AU_NOR: |
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case AU_NAND: |
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start = au_image[i].start; |
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end = au_image[i].start + au_image[i].size - 1; |
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/* unprotect the address range */ |
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/* this assumes that ONLY the firmware is protected! */ |
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if (au_image[i].type == AU_FIRMWARE) { |
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flash_sect_protect(0, start, end); |
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} |
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/*
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* erase the address range. |
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*/ |
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if (au_image[i].type != AU_NAND) { |
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printf("Updating NOR FLASH with image %s\n", au_image[i].name); |
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debug ("flash_sect_erase(%lx, %lx);\n", start, end); |
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flash_sect_erase(start, end); |
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} else { |
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#if (CONFIG_COMMANDS & CFG_CMD_NAND) |
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printf("Updating NAND FLASH with image %s\n", au_image[i].name); |
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debug ("nand_erase(%lx, %lx);\n", start, end); |
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rc = nand_erase (nand_dev_desc, start, end - start + 1, 0); |
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debug ("nand_erase returned %x\n", rc); |
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#endif |
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} |
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udelay(10000); |
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/* strip the header - except for the kernel and ramdisk */ |
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if (au_image[i].type != AU_FIRMWARE) { |
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addr = (char *)hdr; |
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off = sizeof(*hdr); |
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nbytes = sizeof(*hdr) + ntohl(hdr->ih_size); |
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} else { |
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addr = (char *)((char *)hdr + sizeof(*hdr)); |
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off = 0; |
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nbytes = ntohl(hdr->ih_size); |
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} |
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/*
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* copy the data from RAM to FLASH |
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*/ |
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if (au_image[i].type != AU_NAND) { |
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debug ("flash_write(%p, %lx %x)\n", addr, start, nbytes); |
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rc = flash_write(addr, start, nbytes); |
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} else { |
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#if (CONFIG_COMMANDS & CFG_CMD_NAND) |
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debug ("nand_rw(%p, %lx %x)\n", addr, start, nbytes); |
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rc = nand_rw(nand_dev_desc, NANDRW_WRITE | NANDRW_JFFS2, |
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start, nbytes, &total, addr); |
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debug ("nand_rw: ret=%x total=%d nbytes=%d\n", rc, total, nbytes); |
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#endif |
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} |
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if (rc != 0) { |
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printf("Flashing failed due to error %d\n", rc); |
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return -1; |
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} |
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/*
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* check the dcrc of the copy |
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*/ |
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if (au_image[i].type != AU_NAND) { |
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rc = crc32 (0, (char *)(start + off), ntohl(hdr->ih_size)); |
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} else { |
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#if (CONFIG_COMMANDS & CFG_CMD_NAND) |
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rc = nand_rw(nand_dev_desc, NANDRW_READ | NANDRW_JFFS2 | NANDRW_JFFS2_SKIP, |
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start, nbytes, &total, addr); |
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rc = crc32 (0, (char *)(addr + off), ntohl(hdr->ih_size)); |
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#endif |
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} |
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if (rc != ntohl(hdr->ih_dcrc)) { |
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printf ("Image %s Bad Data Checksum After COPY\n", au_image[i].name); |
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return -1; |
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} |
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/* protect the address range */ |
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/* this assumes that ONLY the firmware is protected! */ |
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if (au_image[i].type == AU_FIRMWARE) { |
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flash_sect_protect(1, start, end); |
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} |
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break; |
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default: |
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printf("Wrong image type selected!\n"); |
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} |
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return 0; |
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} |
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static void process_macros (const char *input, char *output) |
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{ |
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char c, prev; |
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const char *varname_start = NULL; |
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int inputcnt = strlen (input); |
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int outputcnt = CFG_CBSIZE; |
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int state = 0; /* 0 = waiting for '$' */ |
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/* 1 = waiting for '(' or '{' */ |
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/* 2 = waiting for ')' or '}' */ |
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/* 3 = waiting for ''' */ |
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#ifdef DEBUG_PARSER |
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char *output_start = output; |
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printf ("[PROCESS_MACROS] INPUT len %d: \"%s\"\n", strlen(input), input); |
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#endif |
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prev = '\0'; /* previous character */ |
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while (inputcnt && outputcnt) { |
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c = *input++; |
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inputcnt--; |
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if (state!=3) { |
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/* remove one level of escape characters */ |
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if ((c == '\\') && (prev != '\\')) { |
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if (inputcnt-- == 0) |
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break; |
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prev = c; |
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c = *input++; |
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} |
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} |
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switch (state) { |
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case 0: /* Waiting for (unescaped) $ */ |
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if ((c == '\'') && (prev != '\\')) { |
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state = 3; |
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break; |
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} |
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if ((c == '$') && (prev != '\\')) { |
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state++; |
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} else { |
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*(output++) = c; |
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outputcnt--; |
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} |
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break; |
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case 1: /* Waiting for ( */ |
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if (c == '(' || c == '{') { |
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state++; |
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varname_start = input; |
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} else { |
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state = 0; |
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*(output++) = '$'; |
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outputcnt--; |
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if (outputcnt) { |
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*(output++) = c; |
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outputcnt--; |
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} |
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} |
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break; |
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case 2: /* Waiting for ) */ |
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if (c == ')' || c == '}') { |
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int i; |
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char envname[CFG_CBSIZE], *envval; |
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int envcnt = input-varname_start-1; /* Varname # of chars */ |
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/* Get the varname */ |
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for (i = 0; i < envcnt; i++) { |
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envname[i] = varname_start[i]; |
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} |
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envname[i] = 0; |
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/* Get its value */ |
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envval = getenv (envname); |
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/* Copy into the line if it exists */ |
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if (envval != NULL) |
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while ((*envval) && outputcnt) { |
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*(output++) = *(envval++); |
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outputcnt--; |
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} |
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/* Look for another '$' */ |
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state = 0; |
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} |
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break; |
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case 3: /* Waiting for ' */ |
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if ((c == '\'') && (prev != '\\')) { |
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state = 0; |
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} else { |
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*(output++) = c; |
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outputcnt--; |
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} |
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break; |
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} |
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prev = c; |
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} |
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if (outputcnt) |
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*output = 0; |
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#ifdef DEBUG_PARSER |
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printf ("[PROCESS_MACROS] OUTPUT len %d: \"%s\"\n", |
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strlen(output_start), output_start); |
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#endif |
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} |
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/*
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* this is called from board_init() after the hardware has been set up |
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* and is usable. That seems like a good time to do this. |
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* Right now the return value is ignored. |
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*/ |
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int do_auto_update(void) |
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{ |
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block_dev_desc_t *stor_dev; |
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long sz; |
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int i, res, cnt, old_ctrlc, got_ctrlc; |
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char buffer[32]; |
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char str[80]; |
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/*
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* Check whether a CompactFlash is inserted |
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*/ |
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if (ide_dev_desc[0].type == DEV_TYPE_UNKNOWN) { |
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return -1; /* no disk detected! */ |
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} |
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/* check whether it has a partition table */ |
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stor_dev = get_dev("ide", 0); |
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if (stor_dev == NULL) { |
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debug ("Uknown device type\n"); |
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return -1; |
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} |
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if (fat_register_device(stor_dev, 1) != 0) { |
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debug ("Unable to register ide disk 0:1 for fatls\n"); |
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return -1; |
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} |
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/*
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* Check if magic file is present |
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*/ |
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if (do_fat_read(AU_MAGIC_FILE, buffer, sizeof(buffer), LS_NO) <= 0) { |
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return -1; |
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} |
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#ifdef CONFIG_AUTO_UPDATE_SHOW |
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board_auto_update_show(1); |
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#endif |
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puts("\nAutoUpdate Disk detected! Trying to update system...\n"); |
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/* make sure that we see CTRL-C and save the old state */ |
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old_ctrlc = disable_ctrlc(0); |
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/* just loop thru all the possible files */ |
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for (i = 0; i < N_AU_IMAGES; i++) { |
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/*
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* Try to expand the environment var in the fname |
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*/ |
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process_macros(au_image[i].name, str); |
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strcpy(au_image[i].name, str); |
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printf("Reading %s ...", au_image[i].name); |
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/* just read the header */ |
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sz = do_fat_read(au_image[i].name, LOAD_ADDR, sizeof(image_header_t), LS_NO); |
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debug ("read %s sz %ld hdr %d\n", |
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au_image[i].name, sz, sizeof(image_header_t)); |
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if (sz <= 0 || sz < sizeof(image_header_t)) { |
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puts(" not found\n"); |
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continue; |
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} |
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if (au_check_header_valid(i, sz) < 0) { |
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puts(" header not valid\n"); |
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continue; |
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} |
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sz = do_fat_read(au_image[i].name, LOAD_ADDR, MAX_LOADSZ, LS_NO); |
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debug ("read %s sz %ld hdr %d\n", |
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au_image[i].name, sz, sizeof(image_header_t)); |
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if (sz <= 0 || sz <= sizeof(image_header_t)) { |
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puts(" not found\n"); |
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continue; |
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} |
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if (au_check_cksum_valid(i, sz) < 0) { |
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puts(" checksum not valid\n"); |
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continue; |
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} |
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puts(" done\n"); |
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do { |
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res = au_do_update(i, sz); |
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/* let the user break out of the loop */ |
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if (ctrlc() || had_ctrlc()) { |
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clear_ctrlc(); |
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if (res < 0) |
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got_ctrlc = 1; |
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break; |
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} |
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cnt++; |
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} while (res < 0); |
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} |
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|
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/* restore the old state */ |
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disable_ctrlc(old_ctrlc); |
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puts("AutoUpdate finished\n\n"); |
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#ifdef CONFIG_AUTO_UPDATE_SHOW |
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board_auto_update_show(0); |
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#endif |
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return 0; |
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} |
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|
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|
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int auto_update(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) |
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{ |
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do_auto_update(); |
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|
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return 0; |
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} |
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U_BOOT_CMD( |
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autoupd, 1, 1, auto_update, |
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"autoupd - Automatically update images\n", |
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NULL |
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); |
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#endif /* CONFIG_AUTO_UPDATE */ |
@ -0,0 +1,51 @@ |
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/*
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* (C) Copyright 2004 |
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* Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com |
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* |
||||
* See file CREDITS for list of people who contributed to this |
||||
* project. |
||||
* |
||||
* This program is free software; you can redistribute it and/or |
||||
* modify it under the terms of the GNU General Public License as |
||||
* published by the Free Software Foundation; either version 2 of |
||||
* the License, or (at your option) any later version. |
||||
* |
||||
* This program is distributed in the hope that it will be useful, |
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of |
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
||||
* GNU General Public License for more details. |
||||
* |
||||
* You should have received a copy of the GNU General Public License |
||||
* along with this program; if not, write to the Free Software |
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
||||
* MA 02111-1307 USA |
||||
*/ |
||||
|
||||
#ifndef _AUTO_UPDATE_H_ |
||||
#define _AUTO_UPDATE_H_ |
||||
|
||||
#define MBR_MAGIC 0x07081967 |
||||
#define MBR_MAGIC_ADDR 0x100 /* offset 0x100 should be free space */ |
||||
|
||||
#define AU_MAGIC_FILE "__auto_update" |
||||
|
||||
#define AU_SCRIPT 1 |
||||
#define AU_FIRMWARE 2 |
||||
#define AU_NOR 3 |
||||
#define AU_NAND 4 |
||||
|
||||
struct au_image_s { |
||||
char name[80]; |
||||
ulong start; |
||||
ulong size; |
||||
int type; |
||||
}; |
||||
|
||||
typedef struct au_image_s au_image_t; |
||||
|
||||
int do_auto_update(void); |
||||
#ifdef CONFIG_AUTO_UPDATE_SHOW |
||||
void board_auto_update_show(int au_active); |
||||
#endif |
||||
|
||||
#endif /* #ifndef _AUTO_UPDATE_H_ */ |
@ -0,0 +1,230 @@ |
||||
/*
|
||||
* (C) Copyright 2003-2004 |
||||
* Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com |
||||
* |
||||
* See file CREDITS for list of people who contributed to this |
||||
* project. |
||||
* |
||||
* This program is free software; you can redistribute it and/or |
||||
* modify it under the terms of the GNU General Public License as |
||||
* published by the Free Software Foundation; either version 2 of |
||||
* the License, or (at your option) any later version. |
||||
* |
||||
* This program is distributed in the hope that it will be useful, |
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of |
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
||||
* GNU General Public License for more details. |
||||
* |
||||
* You should have received a copy of the GNU General Public License |
||||
* along with this program; if not, write to the Free Software |
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
||||
* MA 02111-1307 USA |
||||
*/ |
||||
|
||||
#include "lcd.h" |
||||
|
||||
|
||||
int palette_index; |
||||
int palette_value; |
||||
|
||||
|
||||
#ifdef CFG_LCD_ENDIAN |
||||
void lcd_setup(int lcd, int config) |
||||
{ |
||||
if (lcd == 0) { |
||||
/*
|
||||
* Set endianess and reset lcd controller 0 (small) |
||||
*/ |
||||
out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_LCD0_RST); /* set reset to low */ |
||||
udelay(10); /* wait 10us */ |
||||
if (config == 1) { |
||||
out32(GPIO0_OR, in32(GPIO0_OR) | CFG_LCD_ENDIAN); /* big-endian */ |
||||
} else { |
||||
out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_LCD_ENDIAN); /* little-endian */ |
||||
} |
||||
udelay(10); /* wait 10us */ |
||||
out32(GPIO0_OR, in32(GPIO0_OR) | CFG_LCD0_RST); /* set reset to high */ |
||||
} else { |
||||
/*
|
||||
* Set endianess and reset lcd controller 1 (big) |
||||
*/ |
||||
out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_LCD1_RST); /* set reset to low */ |
||||
udelay(10); /* wait 10us */ |
||||
if (config == 1) { |
||||
out32(GPIO0_OR, in32(GPIO0_OR) | CFG_LCD_ENDIAN); /* big-endian */ |
||||
} else { |
||||
out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_LCD_ENDIAN); /* little-endian */ |
||||
} |
||||
udelay(10); /* wait 10us */ |
||||
out32(GPIO0_OR, in32(GPIO0_OR) | CFG_LCD1_RST); /* set reset to high */ |
||||
} |
||||
|
||||
/*
|
||||
* CFG_LCD_ENDIAN may also be FPGA_RESET, so set inactive |
||||
*/ |
||||
out32(GPIO0_OR, in32(GPIO0_OR) | CFG_LCD_ENDIAN); /* set reset high again */ |
||||
} |
||||
#endif /* #ifdef CFG_LCD_ENDIAN */ |
||||
|
||||
|
||||
void lcd_init(uchar *lcd_reg, uchar *lcd_mem, S1D_REGS *regs, int reg_count, |
||||
uchar *logo_bmp, ulong len) |
||||
{ |
||||
int i; |
||||
ushort s1dReg; |
||||
uchar s1dValue; |
||||
uchar *ptr; |
||||
ushort *ptr2; |
||||
ushort val; |
||||
unsigned char *dst; |
||||
int x, y; |
||||
int width, height, bpp, colors, line_size; |
||||
int header_size; |
||||
unsigned char *bmp; |
||||
unsigned char r, g, b; |
||||
BITMAPINFOHEADER *bm_info; |
||||
int reg_byte_swap; |
||||
|
||||
/*
|
||||
* Detect epson |
||||
*/ |
||||
if (lcd_reg[0] == 0x1c) { |
||||
/*
|
||||
* Big epson detected |
||||
*/ |
||||
reg_byte_swap = FALSE; |
||||
palette_index = 0x1e2; |
||||
palette_value = 0x1e4; |
||||
puts("LCD: S1D13806"); |
||||
} else if (lcd_reg[1] == 0x1c) { |
||||
/*
|
||||
* Big epson detected (with register swap bug) |
||||
*/ |
||||
reg_byte_swap = TRUE; |
||||
palette_index = 0x1e3; |
||||
palette_value = 0x1e5; |
||||
puts("LCD: S1D13806S"); |
||||
} else if (lcd_reg[0] == 0x18) { |
||||
/*
|
||||
* Small epson detected (704) |
||||
*/ |
||||
reg_byte_swap = FALSE; |
||||
palette_index = 0x15; |
||||
palette_value = 0x17; |
||||
puts("LCD: S1D13704"); |
||||
} else if (lcd_reg[0x10000] == 0x24) { |
||||
/*
|
||||
* Small epson detected (705) |
||||
*/ |
||||
reg_byte_swap = FALSE; |
||||
palette_index = 0x15; |
||||
palette_value = 0x17; |
||||
lcd_reg += 0x10000; /* add offset for 705 regs */ |
||||
puts("LCD: S1D13705"); |
||||
} else { |
||||
puts("LCD: No controller detected!\n"); |
||||
return; |
||||
} |
||||
|
||||
for (i = 0; i<reg_count; i++) { |
||||
s1dReg = regs[i].Index; |
||||
if (reg_byte_swap) { |
||||
if ((s1dReg & 0x0001) == 0) |
||||
s1dReg |= 0x0001; |
||||
else |
||||
s1dReg &= ~0x0001; |
||||
} |
||||
s1dValue = regs[i].Value; |
||||
lcd_reg[s1dReg] = s1dValue; |
||||
} |
||||
|
||||
/*
|
||||
* Decompress bmp image |
||||
*/ |
||||
dst = malloc(CFG_LCD_LOGO_MAX_SIZE); |
||||
if (gunzip(dst, CFG_LCD_LOGO_MAX_SIZE, (uchar *)logo_bmp, &len) != 0) { |
||||
return; |
||||
} |
||||
|
||||
/*
|
||||
* Check for bmp mark 'BM' |
||||
*/ |
||||
if (*(ushort *)dst != 0x424d) { |
||||
printf("LCD: Unknown image format!\n"); |
||||
free(dst); |
||||
return; |
||||
} |
||||
|
||||
/*
|
||||
* Get image info from bmp-header |
||||
*/ |
||||
bm_info = (BITMAPINFOHEADER *)(dst + 14); |
||||
bpp = LOAD_SHORT(bm_info->biBitCount); |
||||
width = LOAD_LONG(bm_info->biWidth); |
||||
height = LOAD_LONG(bm_info->biHeight); |
||||
switch (bpp) { |
||||
case 1: |
||||
colors = 1; |
||||
line_size = width >> 3; |
||||
break; |
||||
case 4: |
||||
colors = 16; |
||||
line_size = width >> 1; |
||||
break; |
||||
case 8: |
||||
colors = 256; |
||||
line_size = width; |
||||
break; |
||||
case 24: |
||||
colors = 0; |
||||
line_size = width * 3; |
||||
break; |
||||
default: |
||||
printf("LCD: Unknown bpp (%d) im image!\n", bpp); |
||||
free(dst); |
||||
return; |
||||
} |
||||
printf(" (%d*%d, %dbpp)\n", width, height, bpp); |
||||
|
||||
/*
|
||||
* Write color palette |
||||
*/ |
||||
if (colors <= 256) { |
||||
ptr = (unsigned char *)(dst + 14 + 40); |
||||
for (i=0; i<colors; i++) { |
||||
b = *ptr++; |
||||
g = *ptr++; |
||||
r = *ptr++; |
||||
ptr++; |
||||
S1D_WRITE_PALETTE(lcd_reg, i, r, g, b); |
||||
} |
||||
} |
||||
|
||||
/*
|
||||
* Write bitmap data into framebuffer |
||||
*/ |
||||
ptr = lcd_mem; |
||||
ptr2 = (ushort *)lcd_mem; |
||||
header_size = 14 + 40 + 4*colors; /* skip bmp header */ |
||||
for (y=0; y<height; y++) { |
||||
bmp = &dst[(height-1-y)*line_size + header_size]; |
||||
if (bpp == 24) { |
||||
for (x=0; x<width; x++) { |
||||
/*
|
||||
* Generate epson 16bpp fb-format from 24bpp image |
||||
*/ |
||||
b = *bmp++ >> 3; |
||||
g = *bmp++ >> 2; |
||||
r = *bmp++ >> 3; |
||||
val = ((r & 0x1f) << 11) | ((g & 0x3f) << 5) | (b & 0x1f); |
||||
*ptr2++ = val; |
||||
} |
||||
} else { |
||||
for (x=0; x<line_size; x++) { |
||||
*ptr++ = *bmp++; |
||||
} |
||||
} |
||||
} |
||||
|
||||
free(dst); |
||||
} |
@ -0,0 +1,71 @@ |
||||
/*
|
||||
* (C) Copyright 2003-2004 |
||||
* Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com |
||||
* |
||||
* See file CREDITS for list of people who contributed to this |
||||
* project. |
||||
* |
||||
* This program is free software; you can redistribute it and/or |
||||
* modify it under the terms of the GNU General Public License as |
||||
* published by the Free Software Foundation; either version 2 of |
||||
* the License, or (at your option) any later version. |
||||
* |
||||
* This program is distributed in the hope that it will be useful, |
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of |
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
||||
* GNU General Public License for more details. |
||||
* |
||||
* You should have received a copy of the GNU General Public License |
||||
* along with this program; if not, write to the Free Software |
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
||||
* MA 02111-1307 USA |
||||
*/ |
||||
|
||||
/*
|
||||
* Neutralize little endians. |
||||
*/ |
||||
#define SWAP_LONG(data) ((unsigned long) \ |
||||
(((unsigned long)(data) >> 24) | \
|
||||
((unsigned long)(data) << 24) | \
|
||||
(((unsigned long)(data) >> 8) & 0x0000ff00 ) | \
|
||||
(((unsigned long)(data) << 8) & 0x00ff0000 ))) |
||||
#define SWAP_SHORT(data) ((unsigned short) \ |
||||
(((unsigned short)(data) >> 8 ) | \
|
||||
((unsigned short)(data) << 8 ))) |
||||
#define LOAD_LONG(data) SWAP_LONG(data) |
||||
#define LOAD_SHORT(data) SWAP_SHORT(data) |
||||
|
||||
#ifndef FALSE |
||||
#define FALSE 0 |
||||
#define TRUE (!FALSE) |
||||
#endif |
||||
|
||||
#define S1D_WRITE_PALETTE(p,i,r,g,b) \ |
||||
{ \
|
||||
((volatile uchar*)(p))[palette_index] = (uchar)(i); \
|
||||
((volatile uchar*)(p))[palette_value] = (uchar)(r); \
|
||||
((volatile uchar*)(p))[palette_value] = (uchar)(g); \
|
||||
((volatile uchar*)(p))[palette_value] = (uchar)(b); \
|
||||
} |
||||
|
||||
typedef struct |
||||
{ |
||||
ushort Index; |
||||
uchar Value; |
||||
} S1D_REGS; |
||||
|
||||
typedef struct /**** BMP file info structure ****/ |
||||
{ |
||||
unsigned int biSize; /* Size of info header */ |
||||
int biWidth; /* Width of image */ |
||||
int biHeight; /* Height of image */ |
||||
unsigned short biPlanes; /* Number of color planes */ |
||||
unsigned short biBitCount; /* Number of bits per pixel */ |
||||
unsigned int biCompression; /* Type of compression to use */ |
||||
unsigned int biSizeImage; /* Size of image data */ |
||||
int biXPelsPerMeter; /* X pixels per meter */ |
||||
int biYPelsPerMeter; /* Y pixels per meter */ |
||||
unsigned int biClrUsed; /* Number of colors used */ |
||||
unsigned int biClrImportant; /* Number of important colors */ |
||||
} BITMAPINFOHEADER; |
||||
|
@ -0,0 +1,53 @@ |
||||
/*
|
||||
* |
||||
* Generic Header information generated by 13704CFG.EXE (Build 10) |
||||
* |
||||
* Copyright (c) 2000,2001 Epson Research and Development, Inc. |
||||
* All rights reserved. |
||||
* |
||||
* Panel: 320x240x4bpp 78Hz Mono 4-Bit STN, Disabled (PCLK=6.666MHz) |
||||
* |
||||
* This file defines the configuration environment and registers, |
||||
* which can be used by any software, such as display drivers. |
||||
* |
||||
* PLEASE NOTE: If you FTP this file to a non-Windows platform, make |
||||
* sure you transfer this file using ASCII, not BINARY |
||||
* mode. |
||||
* |
||||
*/ |
||||
|
||||
static S1D_REGS regs_13704_320_240_4bpp[] = |
||||
{ |
||||
{ 0x00, 0x00 }, /* Revision Code Register */ |
||||
{ 0x01, 0x04 }, /*00*/ /* Mode Register 0 Register */ |
||||
{ 0x02, 0xA4 }, /*a0*/ /* Mode Register 1 Register */ |
||||
{ 0x03, 0x83 }, /*03*/ /* Mode Register 2 Register - bit7 is LUT bypass */ |
||||
{ 0x04, 0x27 }, /* Horizontal Panel Size Register */ |
||||
{ 0x05, 0xEF }, /* Vertical Panel Size Register (LSB) */ |
||||
{ 0x06, 0x00 }, /* Vertical Panel Size Register (MSB) */ |
||||
{ 0x07, 0x00 }, /* FPLINE Start Position Register */ |
||||
{ 0x08, 0x00 }, /* Horizontal Non-Display Period Register */ |
||||
{ 0x09, 0x00 }, /* FPFRAME Start Position Register */ |
||||
{ 0x0A, 0x02 }, /* Vertical Non-Display Period Register */ |
||||
{ 0x0B, 0x00 }, /* MOD Rate Register */ |
||||
{ 0x0C, 0x00 }, /* Screen 1 Start Address Register (LSB) */ |
||||
{ 0x0D, 0x00 }, /* Screen 1 Start Address Register (MSB) */ |
||||
{ 0x0E, 0x00 }, /* Not Used */ |
||||
{ 0x0F, 0x00 }, /* Screen 2 Start Address Register (LSB) */ |
||||
{ 0x10, 0x00 }, /* Screen 2 Start Address Register (MSB) */ |
||||
{ 0x11, 0x00 }, /* Not Used */ |
||||
{ 0x12, 0x00 }, /* Memory Address Offset Register */ |
||||
{ 0x13, 0xFF }, /* Screen 1 Vertical Size Register (LSB) */ |
||||
{ 0x14, 0x03 }, /* Screen 1 Vertical Size Register (MSB) */ |
||||
{ 0x15, 0x00 }, /* Look-Up Table Address Register */ |
||||
{ 0x16, 0x00 }, /* Look-Up Table Bank Select Register */ |
||||
{ 0x17, 0x00 }, /* Look-Up Table Data Register */ |
||||
{ 0x18, 0x01 }, /* GPIO Configuration Control Register */ |
||||
{ 0x19, 0x01 }, /* GPIO Status/Control Register */ |
||||
{ 0x1A, 0x00 }, /* Scratch Pad Register */ |
||||
{ 0x1B, 0x00 }, /* SwivelView Mode Register */ |
||||
{ 0x1C, 0xA0 }, /* Line Byte Count Register */ |
||||
{ 0x1D, 0x00 }, /* Not Used */ |
||||
{ 0x1E, 0x00 }, /* Not Used */ |
||||
{ 0x1F, 0x00 }, /* Not Used */ |
||||
}; |
@ -0,0 +1,53 @@ |
||||
/*
|
||||
* |
||||
* Generic Header information generated by 13704CFG.EXE (Build 10) |
||||
* |
||||
* Copyright (c) 2000,2001 Epson Research and Development, Inc. |
||||
* All rights reserved. |
||||
* |
||||
* Panel: 320x240x8bpp 78Hz Mono 8-Bit STN, Disabled (PCLK=6.666MHz) |
||||
* |
||||
* This file defines the configuration environment and registers, |
||||
* which can be used by any software, such as display drivers. |
||||
* |
||||
* PLEASE NOTE: If you FTP this file to a non-Windows platform, make |
||||
* sure you transfer this file using ASCII, not BINARY |
||||
* mode. |
||||
* |
||||
*/ |
||||
|
||||
static S1D_REGS regs_13705_320_240_8bpp[] = |
||||
{ |
||||
{ 0x00, 0x00 }, /* Revision Code Register */ |
||||
{ 0x01, 0x23 }, /* Mode Register 0 Register */ |
||||
{ 0x02, 0xE0 }, /* Mode Register 1 Register */ |
||||
{ 0x03, 0x03 }, /* Mode Register 2 Register - bit7 is LUT bypass */ |
||||
{ 0x04, 0x27 }, /* Horizontal Panel Size Register */ |
||||
{ 0x05, 0xEF }, /* Vertical Panel Size Register (LSB) */ |
||||
{ 0x06, 0x00 }, /* Vertical Panel Size Register (MSB) */ |
||||
{ 0x07, 0x00 }, /* FPLINE Start Position Register */ |
||||
{ 0x08, 0x00 }, /* Horizontal Non-Display Period Register */ |
||||
{ 0x09, 0x01 }, /* FPFRAME Start Position Register */ |
||||
{ 0x0A, 0x02 }, /* Vertical Non-Display Period Register */ |
||||
{ 0x0B, 0x00 }, /* MOD Rate Register */ |
||||
{ 0x0C, 0x00 }, /* Screen 1 Start Address Register (LSB) */ |
||||
{ 0x0D, 0x00 }, /* Screen 1 Start Address Register (MSB) */ |
||||
{ 0x0E, 0x00 }, /* Not Used */ |
||||
{ 0x0F, 0x00 }, /* Screen 2 Start Address Register (LSB) */ |
||||
{ 0x10, 0x00 }, /* Screen 2 Start Address Register (MSB) */ |
||||
{ 0x11, 0x00 }, /* Not Used */ |
||||
{ 0x12, 0x00 }, /* Memory Address Offset Register */ |
||||
{ 0x13, 0xFF }, /* Screen 1 Vertical Size Register (LSB) */ |
||||
{ 0x14, 0x03 }, /* Screen 1 Vertical Size Register (MSB) */ |
||||
{ 0x15, 0x00 }, /* Look-Up Table Address Register */ |
||||
{ 0x16, 0x00 }, /* Look-Up Table Bank Select Register */ |
||||
{ 0x17, 0x00 }, /* Look-Up Table Data Register */ |
||||
{ 0x18, 0x01 }, /* GPIO Configuration Control Register */ |
||||
{ 0x19, 0x01 }, /* GPIO Status/Control Register */ |
||||
{ 0x1A, 0x00 }, /* Scratch Pad Register */ |
||||
{ 0x1B, 0x00 }, /* SwivelView Mode Register */ |
||||
{ 0x1C, 0xFF }, /* Line Byte Count Register */ |
||||
{ 0x1D, 0x00 }, /* Not Used */ |
||||
{ 0x1E, 0x00 }, /* Not Used */ |
||||
{ 0x1F, 0x00 }, /* Not Used */ |
||||
}; |
@ -0,0 +1,126 @@ |
||||
/*
|
||||
* |
||||
* File generated by S1D13806CFG.EXE |
||||
* |
||||
* Copyright (c) 2000,2001 Epson Research and Development, Inc. |
||||
* All rights reserved. |
||||
* |
||||
* PLEASE NOTE: If you FTP this file to a non-Windows platform, make |
||||
* sure you transfer this file using ASCII, not BINARY mode. |
||||
* |
||||
* Panel: (active) 1024x768 34Hz TFT Single 12-bit (PCLK=BUSCLK=33.333MHz) |
||||
* Memory: Embedded SDRAM (MCLK=CLKI=49.100MHz) (BUSCLK=33.333MHz) |
||||
* |
||||
*/ |
||||
|
||||
static S1D_REGS regs_13806_1024_768_8bpp[] = |
||||
{ |
||||
{0x0001,0x00}, /* Miscellaneous Register */ |
||||
{0x01FC,0x00}, /* Display Mode Register */ |
||||
{0x0004,0x00}, /* General IO Pins Configuration Register 0 */ |
||||
{0x0005,0x00}, /* General IO Pins Configuration Register 1 */ |
||||
{0x0008,0x00}, /* General IO Pins Control Register 0 */ |
||||
{0x0009,0x00}, /* General IO Pins Control Register 1 */ |
||||
{0x0010,0x00}, /* Memory Clock Configuration Register */ |
||||
{0x0014,0x01}, /* LCD Pixel Clock Configuration Register */ |
||||
{0x0018,0x00}, /* CRT/TV Pixel Clock Configuration Register */ |
||||
{0x001C,0x02}, /* MediaPlug Clock Configuration Register */ |
||||
{0x001E,0x01}, /* CPU To Memory Wait State Select Register */ |
||||
{0x0021,0x03}, /* DRAM Refresh Rate Register */ |
||||
{0x002A,0x00}, /* DRAM Timings Control Register 0 */ |
||||
{0x002B,0x01}, /* DRAM Timings Control Register 1 */ |
||||
{0x0020,0x80}, /* Memory Configuration Register */ |
||||
{0x0030,0x55}, /* Panel Type Register */ |
||||
{0x0031,0x00}, /* MOD Rate Register */ |
||||
{0x0032,0x7F}, /* LCD Horizontal Display Width Register */ |
||||
{0x0034,0x12}, /* LCD Horizontal Non-Display Period Register */ |
||||
{0x0035,0x01}, /* TFT FPLINE Start Position Register */ |
||||
{0x0036,0x0B}, /* TFT FPLINE Pulse Width Register */ |
||||
{0x0038,0xFF}, /* LCD Vertical Display Height Register 0 */ |
||||
{0x0039,0x02}, /* LCD Vertical Display Height Register 1 */ |
||||
{0x003A,0x2C}, /* LCD Vertical Non-Display Period Register */ |
||||
{0x003B,0x0A}, /* TFT FPFRAME Start Position Register */ |
||||
{0x003C,0x01}, /* TFT FPFRAME Pulse Width Register */ |
||||
{0x0040,0x03}, /* LCD Display Mode Register */ |
||||
{0x0041,0x00}, /* LCD Miscellaneous Register */ |
||||
{0x0042,0x00}, /* LCD Display Start Address Register 0 */ |
||||
{0x0043,0x00}, /* LCD Display Start Address Register 1 */ |
||||
{0x0044,0x00}, /* LCD Display Start Address Register 2 */ |
||||
{0x0046,0x00}, /* LCD Memory Address Offset Register 0 */ |
||||
{0x0047,0x02}, /* LCD Memory Address Offset Register 1 */ |
||||
{0x0048,0x00}, /* LCD Pixel Panning Register */ |
||||
{0x004A,0x00}, /* LCD Display FIFO High Threshold Control Register */ |
||||
{0x004B,0x00}, /* LCD Display FIFO Low Threshold Control Register */ |
||||
{0x0050,0x4F}, /* CRT/TV Horizontal Display Width Register */ |
||||
{0x0052,0x13}, /* CRT/TV Horizontal Non-Display Period Register */ |
||||
{0x0053,0x01}, /* CRT/TV HRTC Start Position Register */ |
||||
{0x0054,0x0B}, /* CRT/TV HRTC Pulse Width Register */ |
||||
{0x0056,0xDF}, /* CRT/TV Vertical Display Height Register 0 */ |
||||
{0x0057,0x01}, /* CRT/TV Vertical Display Height Register 1 */ |
||||
{0x0058,0x2B}, /* CRT/TV Vertical Non-Display Period Register */ |
||||
{0x0059,0x09}, /* CRT/TV VRTC Start Position Register */ |
||||
{0x005A,0x01}, /* CRT/TV VRTC Pulse Width Register */ |
||||
{0x005B,0x10}, /* TV Output Control Register */ |
||||
{0x0060,0x03}, /* CRT/TV Display Mode Register */ |
||||
{0x0062,0x00}, /* CRT/TV Display Start Address Register 0 */ |
||||
{0x0063,0x00}, /* CRT/TV Display Start Address Register 1 */ |
||||
{0x0064,0x00}, /* CRT/TV Display Start Address Register 2 */ |
||||
{0x0066,0x40}, /* CRT/TV Memory Address Offset Register 0 */ |
||||
{0x0067,0x01}, /* CRT/TV Memory Address Offset Register 1 */ |
||||
{0x0068,0x00}, /* CRT/TV Pixel Panning Register */ |
||||
{0x006A,0x00}, /* CRT/TV Display FIFO High Threshold Control Register */ |
||||
{0x006B,0x00}, /* CRT/TV Display FIFO Low Threshold Control Register */ |
||||
{0x0070,0x00}, /* LCD Ink/Cursor Control Register */ |
||||
{0x0071,0x01}, /* LCD Ink/Cursor Start Address Register */ |
||||
{0x0072,0x00}, /* LCD Cursor X Position Register 0 */ |
||||
{0x0073,0x00}, /* LCD Cursor X Position Register 1 */ |
||||
{0x0074,0x00}, /* LCD Cursor Y Position Register 0 */ |
||||
{0x0075,0x00}, /* LCD Cursor Y Position Register 1 */ |
||||
{0x0076,0x00}, /* LCD Ink/Cursor Blue Color 0 Register */ |
||||
{0x0077,0x00}, /* LCD Ink/Cursor Green Color 0 Register */ |
||||
{0x0078,0x00}, /* LCD Ink/Cursor Red Color 0 Register */ |
||||
{0x007A,0x1F}, /* LCD Ink/Cursor Blue Color 1 Register */ |
||||
{0x007B,0x3F}, /* LCD Ink/Cursor Green Color 1 Register */ |
||||
{0x007C,0x1F}, /* LCD Ink/Cursor Red Color 1 Register */ |
||||
{0x007E,0x00}, /* LCD Ink/Cursor FIFO Threshold Register */ |
||||
{0x0080,0x00}, /* CRT/TV Ink/Cursor Control Register */ |
||||
{0x0081,0x01}, /* CRT/TV Ink/Cursor Start Address Register */ |
||||
{0x0082,0x00}, /* CRT/TV Cursor X Position Register 0 */ |
||||
{0x0083,0x00}, /* CRT/TV Cursor X Position Register 1 */ |
||||
{0x0084,0x00}, /* CRT/TV Cursor Y Position Register 0 */ |
||||
{0x0085,0x00}, /* CRT/TV Cursor Y Position Register 1 */ |
||||
{0x0086,0x00}, /* CRT/TV Ink/Cursor Blue Color 0 Register */ |
||||
{0x0087,0x00}, /* CRT/TV Ink/Cursor Green Color 0 Register */ |
||||
{0x0088,0x00}, /* CRT/TV Ink/Cursor Red Color 0 Register */ |
||||
{0x008A,0x1F}, /* CRT/TV Ink/Cursor Blue Color 1 Register */ |
||||
{0x008B,0x3F}, /* CRT/TV Ink/Cursor Green Color 1 Register */ |
||||
{0x008C,0x1F}, /* CRT/TV Ink/Cursor Red Color 1 Register */ |
||||
{0x008E,0x00}, /* CRT/TV Ink/Cursor FIFO Threshold Register */ |
||||
{0x0100,0x00}, /* BitBlt Control Register 0 */ |
||||
{0x0101,0x00}, /* BitBlt Control Register 1 */ |
||||
{0x0102,0x00}, /* BitBlt ROP Code/Color Expansion Register */ |
||||
{0x0103,0x00}, /* BitBlt Operation Register */ |
||||
{0x0104,0x00}, /* BitBlt Source Start Address Register 0 */ |
||||
{0x0105,0x00}, /* BitBlt Source Start Address Register 1 */ |
||||
{0x0106,0x00}, /* BitBlt Source Start Address Register 2 */ |
||||
{0x0108,0x00}, /* BitBlt Destination Start Address Register 0 */ |
||||
{0x0109,0x00}, /* BitBlt Destination Start Address Register 1 */ |
||||
{0x010A,0x00}, /* BitBlt Destination Start Address Register 2 */ |
||||
{0x010C,0x00}, /* BitBlt Memory Address Offset Register 0 */ |
||||
{0x010D,0x00}, /* BitBlt Memory Address Offset Register 1 */ |
||||
{0x0110,0x00}, /* BitBlt Width Register 0 */ |
||||
{0x0111,0x00}, /* BitBlt Width Register 1 */ |
||||
{0x0112,0x00}, /* BitBlt Height Register 0 */ |
||||
{0x0113,0x00}, /* BitBlt Height Register 1 */ |
||||
{0x0114,0x00}, /* BitBlt Background Color Register 0 */ |
||||
{0x0115,0x00}, /* BitBlt Background Color Register 1 */ |
||||
{0x0118,0x00}, /* BitBlt Foreground Color Register 0 */ |
||||
{0x0119,0x00}, /* BitBlt Foreground Color Register 1 */ |
||||
{0x01E0,0x00}, /* Look-Up Table Mode Register */ |
||||
{0x01E2,0x00}, /* Look-Up Table Address Register */ |
||||
{0x01F0,0x10}, /* Power Save Configuration Register */ |
||||
{0x01F1,0x00}, /* Power Save Status Register */ |
||||
{0x01F4,0x00}, /* CPU-to-Memory Access Watchdog Timer Register */ |
||||
{0x01FC,0x01}, /* Display Mode Register */ |
||||
}; |
||||
|
@ -0,0 +1,126 @@ |
||||
/*
|
||||
* |
||||
* File generated by S1D13806CFG.EXE |
||||
* |
||||
* Copyright (c) 2000,2001 Epson Research and Development, Inc. |
||||
* All rights reserved. |
||||
* |
||||
* PLEASE NOTE: If you FTP this file to a non-Windows platform, make |
||||
* sure you transfer this file using ASCII, not BINARY mode. |
||||
* |
||||
* Panel: (active) 320x240 62Hz STN Single 4-bit (PCLK=CLKI2/4=6.250MHz) |
||||
* Memory: Embedded SDRAM (MCLK=CLKI=49.500MHz) (BUSCLK=33.333MHz) |
||||
* |
||||
*/ |
||||
|
||||
static S1D_REGS regs_13806_320_240_4bpp[] = |
||||
{ |
||||
{0x0001,0x00}, /* Miscellaneous Register */ |
||||
{0x01FC,0x00}, /* Display Mode Register */ |
||||
{0x0004,0x08}, /* General IO Pins Configuration Register 0 */ |
||||
{0x0005,0x08}, /* General IO Pins Configuration Register 1 */ |
||||
{0x0008,0x08}, /* General IO Pins Control Register 0 */ |
||||
{0x0009,0x00}, /* General IO Pins Control Register 1 */ |
||||
{0x0010,0x00}, /* Memory Clock Configuration Register */ |
||||
{0x0014,0x32}, /* LCD Pixel Clock Configuration Register */ |
||||
{0x0018,0x00}, /* CRT/TV Pixel Clock Configuration Register */ |
||||
{0x001C,0x02}, /* MediaPlug Clock Configuration Register */ |
||||
{0x001E,0x01}, /* CPU To Memory Wait State Select Register */ |
||||
{0x0021,0x03}, /* DRAM Refresh Rate Register */ |
||||
{0x002A,0x00}, /* DRAM Timings Control Register 0 */ |
||||
{0x002B,0x01}, /* DRAM Timings Control Register 1 */ |
||||
{0x0020,0x80}, /* Memory Configuration Register */ |
||||
{0x0030,0x00}, /* Panel Type Register */ |
||||
{0x0031,0x00}, /* MOD Rate Register */ |
||||
{0x0032,0x27}, /* LCD Horizontal Display Width Register */ |
||||
{0x0034,0x03}, /* LCD Horizontal Non-Display Period Register */ |
||||
{0x0035,0x01}, /* TFT FPLINE Start Position Register */ |
||||
{0x0036,0x0B}, /* TFT FPLINE Pulse Width Register */ |
||||
{0x0038,0xEF}, /* LCD Vertical Display Height Register 0 */ |
||||
{0x0039,0x00}, /* LCD Vertical Display Height Register 1 */ |
||||
{0x003A,0x2C}, /* LCD Vertical Non-Display Period Register */ |
||||
{0x003B,0x0A}, /* TFT FPFRAME Start Position Register */ |
||||
{0x003C,0x01}, /* TFT FPFRAME Pulse Width Register */ |
||||
{0x0040,0x02}, /* LCD Display Mode Register */ |
||||
{0x0041,0x00}, /* LCD Miscellaneous Register */ |
||||
{0x0042,0x00}, /* LCD Display Start Address Register 0 */ |
||||
{0x0043,0x00}, /* LCD Display Start Address Register 1 */ |
||||
{0x0044,0x00}, /* LCD Display Start Address Register 2 */ |
||||
{0x0046,0x50}, /* LCD Memory Address Offset Register 0 */ |
||||
{0x0047,0x00}, /* LCD Memory Address Offset Register 1 */ |
||||
{0x0048,0x00}, /* LCD Pixel Panning Register */ |
||||
{0x004A,0x00}, /* LCD Display FIFO High Threshold Control Register */ |
||||
{0x004B,0x00}, /* LCD Display FIFO Low Threshold Control Register */ |
||||
{0x0050,0x4F}, /* CRT/TV Horizontal Display Width Register */ |
||||
{0x0052,0x13}, /* CRT/TV Horizontal Non-Display Period Register */ |
||||
{0x0053,0x01}, /* CRT/TV HRTC Start Position Register */ |
||||
{0x0054,0x0B}, /* CRT/TV HRTC Pulse Width Register */ |
||||
{0x0056,0xDF}, /* CRT/TV Vertical Display Height Register 0 */ |
||||
{0x0057,0x01}, /* CRT/TV Vertical Display Height Register 1 */ |
||||
{0x0058,0x2B}, /* CRT/TV Vertical Non-Display Period Register */ |
||||
{0x0059,0x09}, /* CRT/TV VRTC Start Position Register */ |
||||
{0x005A,0x01}, /* CRT/TV VRTC Pulse Width Register */ |
||||
{0x005B,0x10}, /* TV Output Control Register */ |
||||
{0x0060,0x03}, /* CRT/TV Display Mode Register */ |
||||
{0x0062,0x00}, /* CRT/TV Display Start Address Register 0 */ |
||||
{0x0063,0x00}, /* CRT/TV Display Start Address Register 1 */ |
||||
{0x0064,0x00}, /* CRT/TV Display Start Address Register 2 */ |
||||
{0x0066,0x40}, /* CRT/TV Memory Address Offset Register 0 */ |
||||
{0x0067,0x01}, /* CRT/TV Memory Address Offset Register 1 */ |
||||
{0x0068,0x00}, /* CRT/TV Pixel Panning Register */ |
||||
{0x006A,0x00}, /* CRT/TV Display FIFO High Threshold Control Register */ |
||||
{0x006B,0x00}, /* CRT/TV Display FIFO Low Threshold Control Register */ |
||||
{0x0070,0x00}, /* LCD Ink/Cursor Control Register */ |
||||
{0x0071,0x01}, /* LCD Ink/Cursor Start Address Register */ |
||||
{0x0072,0x00}, /* LCD Cursor X Position Register 0 */ |
||||
{0x0073,0x00}, /* LCD Cursor X Position Register 1 */ |
||||
{0x0074,0x00}, /* LCD Cursor Y Position Register 0 */ |
||||
{0x0075,0x00}, /* LCD Cursor Y Position Register 1 */ |
||||
{0x0076,0x00}, /* LCD Ink/Cursor Blue Color 0 Register */ |
||||
{0x0077,0x00}, /* LCD Ink/Cursor Green Color 0 Register */ |
||||
{0x0078,0x00}, /* LCD Ink/Cursor Red Color 0 Register */ |
||||
{0x007A,0x1F}, /* LCD Ink/Cursor Blue Color 1 Register */ |
||||
{0x007B,0x3F}, /* LCD Ink/Cursor Green Color 1 Register */ |
||||
{0x007C,0x1F}, /* LCD Ink/Cursor Red Color 1 Register */ |
||||
{0x007E,0x00}, /* LCD Ink/Cursor FIFO Threshold Register */ |
||||
{0x0080,0x00}, /* CRT/TV Ink/Cursor Control Register */ |
||||
{0x0081,0x01}, /* CRT/TV Ink/Cursor Start Address Register */ |
||||
{0x0082,0x00}, /* CRT/TV Cursor X Position Register 0 */ |
||||
{0x0083,0x00}, /* CRT/TV Cursor X Position Register 1 */ |
||||
{0x0084,0x00}, /* CRT/TV Cursor Y Position Register 0 */ |
||||
{0x0085,0x00}, /* CRT/TV Cursor Y Position Register 1 */ |
||||
{0x0086,0x00}, /* CRT/TV Ink/Cursor Blue Color 0 Register */ |
||||
{0x0087,0x00}, /* CRT/TV Ink/Cursor Green Color 0 Register */ |
||||
{0x0088,0x00}, /* CRT/TV Ink/Cursor Red Color 0 Register */ |
||||
{0x008A,0x1F}, /* CRT/TV Ink/Cursor Blue Color 1 Register */ |
||||
{0x008B,0x3F}, /* CRT/TV Ink/Cursor Green Color 1 Register */ |
||||
{0x008C,0x1F}, /* CRT/TV Ink/Cursor Red Color 1 Register */ |
||||
{0x008E,0x00}, /* CRT/TV Ink/Cursor FIFO Threshold Register */ |
||||
{0x0100,0x00}, /* BitBlt Control Register 0 */ |
||||
{0x0101,0x00}, /* BitBlt Control Register 1 */ |
||||
{0x0102,0x00}, /* BitBlt ROP Code/Color Expansion Register */ |
||||
{0x0103,0x00}, /* BitBlt Operation Register */ |
||||
{0x0104,0x00}, /* BitBlt Source Start Address Register 0 */ |
||||
{0x0105,0x00}, /* BitBlt Source Start Address Register 1 */ |
||||
{0x0106,0x00}, /* BitBlt Source Start Address Register 2 */ |
||||
{0x0108,0x00}, /* BitBlt Destination Start Address Register 0 */ |
||||
{0x0109,0x00}, /* BitBlt Destination Start Address Register 1 */ |
||||
{0x010A,0x00}, /* BitBlt Destination Start Address Register 2 */ |
||||
{0x010C,0x00}, /* BitBlt Memory Address Offset Register 0 */ |
||||
{0x010D,0x00}, /* BitBlt Memory Address Offset Register 1 */ |
||||
{0x0110,0x00}, /* BitBlt Width Register 0 */ |
||||
{0x0111,0x00}, /* BitBlt Width Register 1 */ |
||||
{0x0112,0x00}, /* BitBlt Height Register 0 */ |
||||
{0x0113,0x00}, /* BitBlt Height Register 1 */ |
||||
{0x0114,0x00}, /* BitBlt Background Color Register 0 */ |
||||
{0x0115,0x00}, /* BitBlt Background Color Register 1 */ |
||||
{0x0118,0x00}, /* BitBlt Foreground Color Register 0 */ |
||||
{0x0119,0x00}, /* BitBlt Foreground Color Register 1 */ |
||||
{0x01E0,0x00}, /* Look-Up Table Mode Register */ |
||||
{0x01E2,0x00}, /* Look-Up Table Address Register */ |
||||
{0x01F0,0x10}, /* Power Save Configuration Register */ |
||||
{0x01F1,0x00}, /* Power Save Status Register */ |
||||
{0x01F4,0x00}, /* CPU-to-Memory Access Watchdog Timer Register */ |
||||
{0x01FC,0x01}, /* Display Mode Register */ |
||||
}; |
||||
|
@ -0,0 +1,126 @@ |
||||
/*
|
||||
* |
||||
* File generated by S1D13806CFG.EXE |
||||
* |
||||
* Copyright (c) 2000,2001 Epson Research and Development, Inc. |
||||
* All rights reserved. |
||||
* |
||||
* PLEASE NOTE: If you FTP this file to a non-Windows platform, make |
||||
* sure you transfer this file using ASCII, not BINARY mode. |
||||
* |
||||
* Panel: (active) 640x480 59Hz TFT Single 18-bit (PCLK=CLKI2=25.000MHz) |
||||
* Memory: Embedded SDRAM (MCLK=CLKI=49.152MHz) (BUSCLK=33.333MHz) |
||||
* |
||||
*/ |
||||
|
||||
static S1D_REGS regs_13806_640_480_16bpp[] = |
||||
{ |
||||
{0x0001,0x00}, /* Miscellaneous Register */ |
||||
{0x01FC,0x00}, /* Display Mode Register */ |
||||
{0x0004,0x18}, /* General IO Pins Configuration Register 0 */ |
||||
{0x0005,0x00}, /* General IO Pins Configuration Register 1 */ |
||||
{0x0008,0x18}, /* General IO Pins Control Register 0 */ |
||||
{0x0009,0x00}, /* General IO Pins Control Register 1 */ |
||||
{0x0010,0x00}, /* Memory Clock Configuration Register */ |
||||
{0x0014,0x02}, /* LCD Pixel Clock Configuration Register */ |
||||
{0x0018,0x02}, /* CRT/TV Pixel Clock Configuration Register */ |
||||
{0x001C,0x02}, /* MediaPlug Clock Configuration Register */ |
||||
{0x001E,0x01}, /* CPU To Memory Wait State Select Register */ |
||||
{0x0021,0x03}, /* DRAM Refresh Rate Register */ |
||||
{0x002A,0x00}, /* DRAM Timings Control Register 0 */ |
||||
{0x002B,0x01}, /* DRAM Timings Control Register 1 */ |
||||
{0x0020,0x80}, /* Memory Configuration Register */ |
||||
{0x0030,0x25}, /* Panel Type Register */ |
||||
{0x0031,0x00}, /* MOD Rate Register */ |
||||
{0x0032,0x4F}, /* LCD Horizontal Display Width Register */ |
||||
{0x0034,0x13}, /* LCD Horizontal Non-Display Period Register */ |
||||
{0x0035,0x00}, /* TFT FPLINE Start Position Register */ |
||||
{0x0036,0x0B}, /* TFT FPLINE Pulse Width Register */ |
||||
{0x0038,0xDF}, /* LCD Vertical Display Height Register 0 */ |
||||
{0x0039,0x01}, /* LCD Vertical Display Height Register 1 */ |
||||
{0x003A,0x24}, /* LCD Vertical Non-Display Period Register */ |
||||
{0x003B,0x00}, /* TFT FPFRAME Start Position Register */ |
||||
{0x003C,0x01}, /* TFT FPFRAME Pulse Width Register */ |
||||
{0x0040,0x05}, /* LCD Display Mode Register */ |
||||
{0x0041,0x00}, /* LCD Miscellaneous Register */ |
||||
{0x0042,0x00}, /* LCD Display Start Address Register 0 */ |
||||
{0x0043,0x00}, /* LCD Display Start Address Register 1 */ |
||||
{0x0044,0x00}, /* LCD Display Start Address Register 2 */ |
||||
{0x0046,0x80}, /* LCD Memory Address Offset Register 0 */ |
||||
{0x0047,0x02}, /* LCD Memory Address Offset Register 1 */ |
||||
{0x0048,0x00}, /* LCD Pixel Panning Register */ |
||||
{0x004A,0x00}, /* LCD Display FIFO High Threshold Control Register */ |
||||
{0x004B,0x00}, /* LCD Display FIFO Low Threshold Control Register */ |
||||
{0x0050,0x4F}, /* CRT/TV Horizontal Display Width Register */ |
||||
{0x0052,0x13}, /* CRT/TV Horizontal Non-Display Period Register */ |
||||
{0x0053,0x01}, /* CRT/TV HRTC Start Position Register */ |
||||
{0x0054,0x0B}, /* CRT/TV HRTC Pulse Width Register */ |
||||
{0x0056,0xDF}, /* CRT/TV Vertical Display Height Register 0 */ |
||||
{0x0057,0x01}, /* CRT/TV Vertical Display Height Register 1 */ |
||||
{0x0058,0x2B}, /* CRT/TV Vertical Non-Display Period Register */ |
||||
{0x0059,0x09}, /* CRT/TV VRTC Start Position Register */ |
||||
{0x005A,0x01}, /* CRT/TV VRTC Pulse Width Register */ |
||||
{0x005B,0x10}, /* TV Output Control Register */ |
||||
{0x0060,0x05}, /* CRT/TV Display Mode Register */ |
||||
{0x0062,0x00}, /* CRT/TV Display Start Address Register 0 */ |
||||
{0x0063,0x00}, /* CRT/TV Display Start Address Register 1 */ |
||||
{0x0064,0x00}, /* CRT/TV Display Start Address Register 2 */ |
||||
{0x0066,0x80}, /* CRT/TV Memory Address Offset Register 0 */ |
||||
{0x0067,0x02}, /* CRT/TV Memory Address Offset Register 1 */ |
||||
{0x0068,0x00}, /* CRT/TV Pixel Panning Register */ |
||||
{0x006A,0x00}, /* CRT/TV Display FIFO High Threshold Control Register */ |
||||
{0x006B,0x00}, /* CRT/TV Display FIFO Low Threshold Control Register */ |
||||
{0x0070,0x00}, /* LCD Ink/Cursor Control Register */ |
||||
{0x0071,0x01}, /* LCD Ink/Cursor Start Address Register */ |
||||
{0x0072,0x00}, /* LCD Cursor X Position Register 0 */ |
||||
{0x0073,0x00}, /* LCD Cursor X Position Register 1 */ |
||||
{0x0074,0x00}, /* LCD Cursor Y Position Register 0 */ |
||||
{0x0075,0x00}, /* LCD Cursor Y Position Register 1 */ |
||||
{0x0076,0x00}, /* LCD Ink/Cursor Blue Color 0 Register */ |
||||
{0x0077,0x00}, /* LCD Ink/Cursor Green Color 0 Register */ |
||||
{0x0078,0x00}, /* LCD Ink/Cursor Red Color 0 Register */ |
||||
{0x007A,0x1F}, /* LCD Ink/Cursor Blue Color 1 Register */ |
||||
{0x007B,0x3F}, /* LCD Ink/Cursor Green Color 1 Register */ |
||||
{0x007C,0x1F}, /* LCD Ink/Cursor Red Color 1 Register */ |
||||
{0x007E,0x00}, /* LCD Ink/Cursor FIFO Threshold Register */ |
||||
{0x0080,0x00}, /* CRT/TV Ink/Cursor Control Register */ |
||||
{0x0081,0x01}, /* CRT/TV Ink/Cursor Start Address Register */ |
||||
{0x0082,0x00}, /* CRT/TV Cursor X Position Register 0 */ |
||||
{0x0083,0x00}, /* CRT/TV Cursor X Position Register 1 */ |
||||
{0x0084,0x00}, /* CRT/TV Cursor Y Position Register 0 */ |
||||
{0x0085,0x00}, /* CRT/TV Cursor Y Position Register 1 */ |
||||
{0x0086,0x00}, /* CRT/TV Ink/Cursor Blue Color 0 Register */ |
||||
{0x0087,0x00}, /* CRT/TV Ink/Cursor Green Color 0 Register */ |
||||
{0x0088,0x00}, /* CRT/TV Ink/Cursor Red Color 0 Register */ |
||||
{0x008A,0x1F}, /* CRT/TV Ink/Cursor Blue Color 1 Register */ |
||||
{0x008B,0x3F}, /* CRT/TV Ink/Cursor Green Color 1 Register */ |
||||
{0x008C,0x1F}, /* CRT/TV Ink/Cursor Red Color 1 Register */ |
||||
{0x008E,0x00}, /* CRT/TV Ink/Cursor FIFO Threshold Register */ |
||||
{0x0100,0x00}, /* BitBlt Control Register 0 */ |
||||
{0x0101,0x00}, /* BitBlt Control Register 1 */ |
||||
{0x0102,0x00}, /* BitBlt ROP Code/Color Expansion Register */ |
||||
{0x0103,0x00}, /* BitBlt Operation Register */ |
||||
{0x0104,0x00}, /* BitBlt Source Start Address Register 0 */ |
||||
{0x0105,0x00}, /* BitBlt Source Start Address Register 1 */ |
||||
{0x0106,0x00}, /* BitBlt Source Start Address Register 2 */ |
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{0x0108,0x00}, /* BitBlt Destination Start Address Register 0 */ |
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{0x0109,0x00}, /* BitBlt Destination Start Address Register 1 */ |
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{0x010A,0x00}, /* BitBlt Destination Start Address Register 2 */ |
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{0x010C,0x00}, /* BitBlt Memory Address Offset Register 0 */ |
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{0x010D,0x00}, /* BitBlt Memory Address Offset Register 1 */ |
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{0x0110,0x00}, /* BitBlt Width Register 0 */ |
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{0x0111,0x00}, /* BitBlt Width Register 1 */ |
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{0x0112,0x00}, /* BitBlt Height Register 0 */ |
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{0x0113,0x00}, /* BitBlt Height Register 1 */ |
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{0x0114,0x00}, /* BitBlt Background Color Register 0 */ |
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{0x0115,0x00}, /* BitBlt Background Color Register 1 */ |
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{0x0118,0x00}, /* BitBlt Foreground Color Register 0 */ |
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{0x0119,0x00}, /* BitBlt Foreground Color Register 1 */ |
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{0x01E0,0x00}, /* Look-Up Table Mode Register */ |
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{0x01E2,0x00}, /* Look-Up Table Address Register */ |
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{0x01F0,0x10}, /* Power Save Configuration Register */ |
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{0x01F1,0x00}, /* Power Save Status Register */ |
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{0x01F4,0x00}, /* CPU-to-Memory Access Watchdog Timer Register */ |
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{0x01FC,0x01}, /* Display Mode Register */ |
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}; |
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|
@ -0,0 +1,126 @@ |
||||
/*
|
||||
* |
||||
* File generated by S1D13806CFG.EXE |
||||
* |
||||
* Copyright (c) 2000,2001 Epson Research and Development, Inc. |
||||
* All rights reserved. |
||||
* |
||||
* PLEASE NOTE: If you FTP this file to a non-Windows platform, make |
||||
* sure you transfer this file using ASCII, not BINARY mode. |
||||
* |
||||
* Panel: (active) 640x480 59Hz TFT Single 18-bit (PCLK=CLKI2=25.000MHz) |
||||
* Memory: Embedded SDRAM (MCLK=CLKI=49.152MHz) (BUSCLK=33.333MHz) |
||||
* |
||||
*/ |
||||
|
||||
static S1D_REGS regs_13806_640_320_16bpp[] = |
||||
{ |
||||
{0x0001,0x00}, /* Miscellaneous Register */ |
||||
{0x01FC,0x00}, /* Display Mode Register */ |
||||
{0x0004,0x18}, /* General IO Pins Configuration Register 0 */ |
||||
{0x0005,0x00}, /* General IO Pins Configuration Register 1 */ |
||||
{0x0008,0x18}, /* General IO Pins Control Register 0 */ |
||||
{0x0009,0x00}, /* General IO Pins Control Register 1 */ |
||||
{0x0010,0x00}, /* Memory Clock Configuration Register */ |
||||
{0x0014,0x02}, /* LCD Pixel Clock Configuration Register */ |
||||
{0x0018,0x02}, /* CRT/TV Pixel Clock Configuration Register */ |
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{0x001C,0x02}, /* MediaPlug Clock Configuration Register */ |
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{0x001E,0x01}, /* CPU To Memory Wait State Select Register */ |
||||
{0x0021,0x03}, /* DRAM Refresh Rate Register */ |
||||
{0x002A,0x00}, /* DRAM Timings Control Register 0 */ |
||||
{0x002B,0x01}, /* DRAM Timings Control Register 1 */ |
||||
{0x0020,0x80}, /* Memory Configuration Register */ |
||||
{0x0030,0x25}, /* Panel Type Register */ |
||||
{0x0031,0x00}, /* MOD Rate Register */ |
||||
{0x0032,0x4F}, /* LCD Horizontal Display Width Register */ |
||||
{0x0034,0x13}, /* LCD Horizontal Non-Display Period Register */ |
||||
{0x0035,0x00}, /* TFT FPLINE Start Position Register */ |
||||
{0x0036,0x0B}, /* TFT FPLINE Pulse Width Register */ |
||||
{0x0038,0xDF}, /* LCD Vertical Display Height Register 0 */ |
||||
{0x0039,0x01}, /* LCD Vertical Display Height Register 1 */ |
||||
{0x003A,0x24}, /* LCD Vertical Non-Display Period Register */ |
||||
{0x003B,0x00}, /* TFT FPFRAME Start Position Register */ |
||||
{0x003C,0x01}, /* TFT FPFRAME Pulse Width Register */ |
||||
{0x0040,0x03}, /* LCD Display Mode Register (8bpp) */ |
||||
{0x0041,0x00}, /* LCD Miscellaneous Register */ |
||||
{0x0042,0x00}, /* LCD Display Start Address Register 0 */ |
||||
{0x0043,0x00}, /* LCD Display Start Address Register 1 */ |
||||
{0x0044,0x00}, /* LCD Display Start Address Register 2 */ |
||||
{0x0046,0x80}, /* LCD Memory Address Offset Register 0 */ |
||||
{0x0047,0x02}, /* LCD Memory Address Offset Register 1 */ |
||||
{0x0048,0x00}, /* LCD Pixel Panning Register */ |
||||
{0x004A,0x00}, /* LCD Display FIFO High Threshold Control Register */ |
||||
{0x004B,0x00}, /* LCD Display FIFO Low Threshold Control Register */ |
||||
{0x0050,0x4F}, /* CRT/TV Horizontal Display Width Register */ |
||||
{0x0052,0x13}, /* CRT/TV Horizontal Non-Display Period Register */ |
||||
{0x0053,0x01}, /* CRT/TV HRTC Start Position Register */ |
||||
{0x0054,0x0B}, /* CRT/TV HRTC Pulse Width Register */ |
||||
{0x0056,0xDF}, /* CRT/TV Vertical Display Height Register 0 */ |
||||
{0x0057,0x01}, /* CRT/TV Vertical Display Height Register 1 */ |
||||
{0x0058,0x2B}, /* CRT/TV Vertical Non-Display Period Register */ |
||||
{0x0059,0x09}, /* CRT/TV VRTC Start Position Register */ |
||||
{0x005A,0x01}, /* CRT/TV VRTC Pulse Width Register */ |
||||
{0x005B,0x10}, /* TV Output Control Register */ |
||||
{0x0060,0x05}, /* CRT/TV Display Mode Register */ |
||||
{0x0062,0x00}, /* CRT/TV Display Start Address Register 0 */ |
||||
{0x0063,0x00}, /* CRT/TV Display Start Address Register 1 */ |
||||
{0x0064,0x00}, /* CRT/TV Display Start Address Register 2 */ |
||||
{0x0066,0x80}, /* CRT/TV Memory Address Offset Register 0 */ |
||||
{0x0067,0x02}, /* CRT/TV Memory Address Offset Register 1 */ |
||||
{0x0068,0x00}, /* CRT/TV Pixel Panning Register */ |
||||
{0x006A,0x00}, /* CRT/TV Display FIFO High Threshold Control Register */ |
||||
{0x006B,0x00}, /* CRT/TV Display FIFO Low Threshold Control Register */ |
||||
{0x0070,0x00}, /* LCD Ink/Cursor Control Register */ |
||||
{0x0071,0x01}, /* LCD Ink/Cursor Start Address Register */ |
||||
{0x0072,0x00}, /* LCD Cursor X Position Register 0 */ |
||||
{0x0073,0x00}, /* LCD Cursor X Position Register 1 */ |
||||
{0x0074,0x00}, /* LCD Cursor Y Position Register 0 */ |
||||
{0x0075,0x00}, /* LCD Cursor Y Position Register 1 */ |
||||
{0x0076,0x00}, /* LCD Ink/Cursor Blue Color 0 Register */ |
||||
{0x0077,0x00}, /* LCD Ink/Cursor Green Color 0 Register */ |
||||
{0x0078,0x00}, /* LCD Ink/Cursor Red Color 0 Register */ |
||||
{0x007A,0x1F}, /* LCD Ink/Cursor Blue Color 1 Register */ |
||||
{0x007B,0x3F}, /* LCD Ink/Cursor Green Color 1 Register */ |
||||
{0x007C,0x1F}, /* LCD Ink/Cursor Red Color 1 Register */ |
||||
{0x007E,0x00}, /* LCD Ink/Cursor FIFO Threshold Register */ |
||||
{0x0080,0x00}, /* CRT/TV Ink/Cursor Control Register */ |
||||
{0x0081,0x01}, /* CRT/TV Ink/Cursor Start Address Register */ |
||||
{0x0082,0x00}, /* CRT/TV Cursor X Position Register 0 */ |
||||
{0x0083,0x00}, /* CRT/TV Cursor X Position Register 1 */ |
||||
{0x0084,0x00}, /* CRT/TV Cursor Y Position Register 0 */ |
||||
{0x0085,0x00}, /* CRT/TV Cursor Y Position Register 1 */ |
||||
{0x0086,0x00}, /* CRT/TV Ink/Cursor Blue Color 0 Register */ |
||||
{0x0087,0x00}, /* CRT/TV Ink/Cursor Green Color 0 Register */ |
||||
{0x0088,0x00}, /* CRT/TV Ink/Cursor Red Color 0 Register */ |
||||
{0x008A,0x1F}, /* CRT/TV Ink/Cursor Blue Color 1 Register */ |
||||
{0x008B,0x3F}, /* CRT/TV Ink/Cursor Green Color 1 Register */ |
||||
{0x008C,0x1F}, /* CRT/TV Ink/Cursor Red Color 1 Register */ |
||||
{0x008E,0x00}, /* CRT/TV Ink/Cursor FIFO Threshold Register */ |
||||
{0x0100,0x00}, /* BitBlt Control Register 0 */ |
||||
{0x0101,0x00}, /* BitBlt Control Register 1 */ |
||||
{0x0102,0x00}, /* BitBlt ROP Code/Color Expansion Register */ |
||||
{0x0103,0x00}, /* BitBlt Operation Register */ |
||||
{0x0104,0x00}, /* BitBlt Source Start Address Register 0 */ |
||||
{0x0105,0x00}, /* BitBlt Source Start Address Register 1 */ |
||||
{0x0106,0x00}, /* BitBlt Source Start Address Register 2 */ |
||||
{0x0108,0x00}, /* BitBlt Destination Start Address Register 0 */ |
||||
{0x0109,0x00}, /* BitBlt Destination Start Address Register 1 */ |
||||
{0x010A,0x00}, /* BitBlt Destination Start Address Register 2 */ |
||||
{0x010C,0x00}, /* BitBlt Memory Address Offset Register 0 */ |
||||
{0x010D,0x00}, /* BitBlt Memory Address Offset Register 1 */ |
||||
{0x0110,0x00}, /* BitBlt Width Register 0 */ |
||||
{0x0111,0x00}, /* BitBlt Width Register 1 */ |
||||
{0x0112,0x00}, /* BitBlt Height Register 0 */ |
||||
{0x0113,0x00}, /* BitBlt Height Register 1 */ |
||||
{0x0114,0x00}, /* BitBlt Background Color Register 0 */ |
||||
{0x0115,0x00}, /* BitBlt Background Color Register 1 */ |
||||
{0x0118,0x00}, /* BitBlt Foreground Color Register 0 */ |
||||
{0x0119,0x00}, /* BitBlt Foreground Color Register 1 */ |
||||
{0x01E0,0x00}, /* Look-Up Table Mode Register */ |
||||
{0x01E2,0x00}, /* Look-Up Table Address Register */ |
||||
{0x01F0,0x10}, /* Power Save Configuration Register */ |
||||
{0x01F1,0x00}, /* Power Save Status Register */ |
||||
{0x01F4,0x00}, /* CPU-to-Memory Access Watchdog Timer Register */ |
||||
{0x01FC,0x01}, /* Display Mode Register */ |
||||
}; |
||||
|
Loading…
Reference in new issue