These boards are old enough and have no maintainers. Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>master
Masahiro Yamada
11 years ago
committed by
Tom Rini
parent
dab0f7626e
commit
0657e46e28
@ -1,8 +0,0 @@ |
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#
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# (C) Copyright 2000-2006
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# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
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#
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# SPDX-License-Identifier: GPL-2.0+
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#
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obj-y = RPXlite_dw.o flash.o
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@ -1,161 +0,0 @@ |
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After following the step of Yoo. Jonghoon and Wolfgang Denk, |
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I ported u-boot on RPXlite DW version board: RPXlite_DW or LITE_DW. |
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There are at least three differences between the Yoo-ported RPXlite and the RPXlite_DW. |
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Board(in U-Boot) version(in EmbeddedPlanet) CPU SDRAM FLASH |
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RPXlite RPXlite CW 850 16MB 4MB |
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RPXlite_DW RPXlite DW(EP 823 H1 DW) 823e 64MB 16MB |
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This fireware is specially coded for EmbeddedPlanet Co. Software Development |
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Platform(RPXlite DW),which has a NEC NL6448BC20-08 LCD panel. |
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It has the following three features: |
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1. 64MHz/48MHz system frequence setting options. |
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The default setting is 48MHz.To get a 64MHz u-boot,just add |
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'64' in make command,like |
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make distclean |
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make RPXlite_DW_64_config |
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make all |
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2. CONFIG_ENV_IS_IN_FLASH/CONFIG_ENV_IS_IN_NVRAM |
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The default environment parameter is stored in FLASH because it is a common choice for |
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environment parameter.So I make NVRAM as backup parameter storeage.The reason why I |
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didn't use EEPROM for ENV is that PlanetCore V2.0 use EEPROM as environment parameter |
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home.Because of the possibility of using two firewares on this board,I didn't |
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'disturb' EEPROM.To get NVRAM support,you may use the following build command: |
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make distclean |
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make RPXlite_DW_NVRAM_config |
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make all |
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3. LCD panel support |
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To support the Platform better,I added LCD panel(NL6448BC20-08) function. |
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For the convenience of debug, CONFIG_PERBOOT was supported. So you just |
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perss ENTER if you want to get a serial console in boot downcounting. |
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Then you can switch to LCD and serial console freely just typing |
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'run lcd' or 'run ser'. They are only vaild when CONFIG_LCD was enabled. |
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To get a LCD support u-boot,you can do the following: |
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make distclean |
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make RPXlite_DW_LCD_config |
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make all |
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~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ |
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The basic make commands could be: |
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make RPXlite_DW_config |
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make RPXlite_DW_64_config |
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make RPXlite_DW_LCD_config |
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make RPXlite_DW_NVRAM_config |
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BTW,you can combine the above features together and get a workable u-boot to meet your need. |
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For example,to get a 64MHZ && ENV_IS_IN_FLASH && LCD panel support u-boot,you can type: |
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make RPXlite_DW_NVRAM_64_LCD_config |
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make all |
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So other combining make commands could be: |
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make RPXlite_DW_NVRAM_64_config |
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make RPXlite_DW_NVRAM_LCD_config |
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make RPXlite_DW_64_LCD_config |
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~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ |
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The boot process by "make RPXlite_DW_config" could be: |
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U-Boot 1.1.2 (Aug 29 2004 - 15:11:27) |
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CPU: PPC823EZTnnB2 at 48 MHz: 16 kB I-Cache 8 kB D-Cache |
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Board: RPXlite_DW |
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DRAM: 64 MB |
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FLASH: 16 MB |
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*** Warning - bad CRC, using default environment |
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In: serial |
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Out: serial |
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Err: serial |
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Net: SCC ETHERNET |
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u-boot> |
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~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ |
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A word on the U-Boot environment variable setting and usage : |
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In the beginning, you could just need very simple default environment variable setting, |
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like[include/configs/RPXlite.h] : |
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#define CONFIG_BOOTCOMMAND \ |
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"bootp; " \ |
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"setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} " \ |
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"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off; " \ |
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"bootm" |
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This is enough for kernel NFS test. But as debug process goes on, you would expect |
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to save some time on environment variable setting and u-boot/kernel updating. |
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So the default environment variable setting would become more complicated. Just like |
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the one I did in include/configs/RPXlite_DW.h. |
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Two u-boot commands, ku and uu, should be careful to use. They were designed to update |
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kernel and u-boot image file respectively. You must tftp your image to default address |
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'100000' and then use them correctly. Yeah, you can create your own command to do this |
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job. :-) The example u-boot image updating process could be : |
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u-boot>t 100000 RPXlite_DW_LCD.bin |
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Using SCC ETHERNET device |
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TFTP from server 172.16.115.6; our IP address is 172.16.115.7 |
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Filename 'RPXlite_DW_LCD.bin'. |
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Load address: 0x100000 |
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Loading: ############################# |
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done |
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Bytes transferred = 144700 (2353c hex) |
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u-boot>run uu |
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Un-Protect Flash Sectors 0-4 in Bank # 1 |
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Erase Flash Sectors 0-4 in Bank # 1 |
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.... done |
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Copy to Flash... done |
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ff000000: 27051956 552d426f 6f742031 2e312e32 '..VU-Boot 1.1.2 |
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ff000010: 20284175 67203239 20323030 34202d20 (Aug 29 2004 - |
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ff000020: 31353a32 303a3238 29000000 00000000 15:20:28)....... |
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ff000030: 00000000 00000000 00000000 00000000 ................ |
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ff000040: 00000000 00000000 00000000 00000000 ................ |
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ff000050: 00000000 00000000 00000000 00000000 ................ |
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ff000060: 00000000 00000000 00000000 00000000 ................ |
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ff000070: 00000000 00000000 00000000 00000000 ................ |
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ff000080: 00000000 00000000 00000000 00000000 ................ |
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ff000090: 00000000 00000000 00000000 00000000 ................ |
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ff0000a0: 00000000 00000000 00000000 00000000 ................ |
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ff0000b0: 00000000 00000000 00000000 00000000 ................ |
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ff0000c0: 00000000 00000000 00000000 00000000 ................ |
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ff0000d0: 00000000 00000000 00000000 00000000 ................ |
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ff0000e0: 00000000 00000000 00000000 00000000 ................ |
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ff0000f0: 00000000 00000000 00000000 00000000 ................ |
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u-boot updating finished |
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u-boot> |
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Also for environment updating, 'run eu' could let you erase OLD default environment variable |
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and then use the working u-boot environment setting. |
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~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ |
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Finally, if you want to keep the serial port to possible debug on spot for deployment, you |
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just need to enable 'DEPLOYMENT' in RPXlite_DW.h as 'DEBUG' does. Only the special string |
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defined by CONFIG_AUTOBOOT_STOP_STR like 'st' can stop the autoboot. |
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I'd like to extend my heartfelt gratitute to kind people for helping me work it out. |
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I would particually thank Wolfgang Denk for his nice help. |
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Enjoy, |
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Sam Song, samsongshu@yahoo.com.cn |
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Institute of Electrical Machinery and Controls |
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Shanghai University |
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Oct. 11, 2004 |
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@ -1,164 +0,0 @@ |
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/*
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* (C) Copyright 2004 |
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* Sam Song, IEMC. SHU, samsongshu@yahoo.com.cn |
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* |
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* SPDX-License-Identifier: GPL-2.0+ |
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*/ |
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/*
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* Sam Song |
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* U-Boot port on RPXlite DW board : RPXlite_DW or LITE_DW |
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* Tested on working at 64MHz(CPU)/32MHz(BUS),48MHz/24MHz |
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* with 64MB, 2 SDRAM Micron chips,MT48LC16M16A2-75. |
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*/ |
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#include <common.h> |
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#include <mpc8xx.h> |
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/* ------------------------------------------------------------------------- */ |
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static long int dram_size (long int, long int *, long int); |
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/* ------------------------------------------------------------------------- */ |
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#define _NOT_USED_ 0xFFFFCC25 |
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const uint sdram_table[] = |
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{ |
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/*
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* Single Read. (Offset 00h in UPMA RAM) |
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*/ |
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0x0F03CC04, 0x00ACCC24, 0x1FF74C20, /* last */ |
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_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, |
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_NOT_USED_, |
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/*
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* Burst Read. (Offset 08h in UPMA RAM) |
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*/ |
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0x0F03CC04, 0x00ACCC24, 0x00FFCC20, 0x00FFCC20, |
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0x01FFCC20, 0x1FF74C20, /* last */ |
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_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, |
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_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, |
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_NOT_USED_, _NOT_USED_, |
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/*
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* Single Write. (Offset 18h in UPMA RAM) |
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*/ |
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0x0F03CC02, 0x00AC0C24, 0x1FF74C25, /* last */ |
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_NOT_USED_, _NOT_USED_, 0x0FA00C34,0x0FFFCC35, |
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_NOT_USED_, |
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/*
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* Burst Write. (Offset 20h in UPMA RAM) |
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*/ |
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0x0F03CC00, 0x00AC0C20, 0x00FFFC20, 0x00FFFC22, |
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0x01FFFC24, 0x1FF74C25, /* last */ |
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_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, |
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_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, |
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_NOT_USED_, _NOT_USED_, |
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/*
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* Refresh. (Offset 30h in UPMA RAM) |
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*/ |
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0x0FF0CC24, 0xFFFFCC24, _NOT_USED_, _NOT_USED_, |
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_NOT_USED_, _NOT_USED_, 0xEFFB8C34, 0x0FF74C34, |
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0x0FFACCB4, 0x0FF5CC34, 0x0FFFCC34, 0x0FFFCCB4, |
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/* INIT sequence RAM WORDS
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* SDRAM Initialization (offset 0x36 in UPMA RAM) |
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* The above definition uses the remaining space |
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* to establish an initialization sequence, |
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* which is executed by a RUN command. |
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* The sequence is COMMAND INHIBIT(NOP),Precharge, |
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* Load Mode Register,NOP,Auto Refresh. |
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*/ |
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/*
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* Exception. (Offset 3Ch in UPMA RAM) |
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*/ |
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0x0FEA8C34, 0x1FB54C34, 0xFFFFCC34, _NOT_USED_ |
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}; |
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/*
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* Check Board Identity: |
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*/ |
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int checkboard (void) |
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{ |
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puts ("Board: RPXlite_DW\n") ; |
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return (0) ; |
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} |
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/* ------------------------------------------------------------------------- */ |
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phys_size_t initdram (int board_type) |
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{ |
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volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR; |
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volatile memctl8xx_t *memctl = &immap->im_memctl; |
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long int size9; |
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upmconfig(UPMA, (uint *)sdram_table, sizeof(sdram_table)/sizeof(uint)); |
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/* Refresh clock prescalar */ |
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memctl->memc_mptpr = CONFIG_SYS_MPTPR ; |
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memctl->memc_mar = 0x00000088; |
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/* Map controller banks 1 to the SDRAM bank */ |
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memctl->memc_or1 = CONFIG_SYS_OR1_PRELIM; |
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memctl->memc_br1 = CONFIG_SYS_BR1_PRELIM; |
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memctl->memc_mamr = CONFIG_SYS_MAMR_9COL & (~(MAMR_PTAE)); /* no refresh yet */ |
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/*Disable Periodic timer A. */ |
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udelay(200); |
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/* perform SDRAM initializsation sequence */ |
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memctl->memc_mcr = 0x80002236; /* SDRAM bank 0 - refresh twice */ |
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udelay(1); |
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memctl->memc_mamr |= MAMR_PTAE; /* enable refresh */ |
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/*Enable Periodic timer A */ |
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udelay (1000); |
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/* Check Bank 0 Memory Size
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* try 9 column mode |
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*/ |
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size9 = dram_size (CONFIG_SYS_MAMR_9COL, SDRAM_BASE_PRELIM, SDRAM_MAX_SIZE); |
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/*
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* Final mapping: |
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*/ |
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memctl->memc_or1 = ((-size9) & 0xFFFF0000) | CONFIG_SYS_OR_TIMING_SDRAM; |
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udelay (1000); |
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return (size9); |
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} |
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void rpxlite_init (void) |
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{ |
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/* Enable NVRAM */ |
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*((uchar *) BCSR0) |= BCSR0_ENNVRAM; |
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} |
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/*
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* Check memory range for valid RAM. A simple memory test determines |
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* the actually available RAM size between addresses `base' and |
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* `base + maxsize'. Some (not all) hardware errors are detected: |
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* - short between address lines |
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* - short between data lines |
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*/ |
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static long int dram_size (long int mamr_value, long int *base, |
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long int maxsize) |
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{ |
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volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR; |
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volatile memctl8xx_t *memctl = &immap->im_memctl; |
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memctl->memc_mamr = mamr_value; |
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return (get_ram_size (base, maxsize)); |
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} |
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@ -1,474 +0,0 @@ |
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/*
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* (C) Copyright 2004 |
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* Wolfgang Denk, DENX Software Engineering, wd@denx.de. |
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* |
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* SPDX-License-Identifier: GPL-2.0+ |
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*/ |
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/*
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* Yoo. Jonghoon, IPone, yooth@ipone.co.kr |
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* U-Boot port on RPXlite board |
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* |
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* Some of flash control words are modified. (from 2x16bit device |
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* to 4x8bit device) |
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* RPXLite board I tested has only 4 AM29LV800BB devices. Other devices |
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* are not tested. |
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* |
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* (?) Does an RPXLite board which |
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* does not use AM29LV800 flash memory exist ? |
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* I don't know... |
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*/ |
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/* Yes,Yoo.They do use other FLASH for the board.
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* |
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* Sam Song, IEMC. SHU, samsongshu@yahoo.com.cn |
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* U-Boot port on RPXlite DW version board |
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* |
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* By now,it uses 4 AM29DL323DB90VI devices(4x8bit). |
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* The total FLASH has 16MB(4x4MB). |
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* I just made some necessary changes on the basis of Wolfgang and Yoo's job. |
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* |
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* June 8, 2004 */ |
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#include <common.h> |
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#include <mpc8xx.h> |
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flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips */ |
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/*-----------------------------------------------------------------------
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* Functions vu_long : volatile unsigned long IN include/common.h |
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*/ |
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static ulong flash_get_size (vu_long *addr, flash_info_t *info); |
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static int write_word (flash_info_t *info, ulong dest, ulong data); |
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static void flash_get_offsets (ulong base, flash_info_t *info); |
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unsigned long flash_init (void) |
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{ |
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unsigned long size_b0 ; |
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int i; |
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/* Init: no FLASHes known */ |
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for (i=0; i<CONFIG_SYS_MAX_FLASH_BANKS; ++i) { |
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flash_info[i].flash_id = FLASH_UNKNOWN; |
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} |
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size_b0 = flash_get_size((vu_long *)CONFIG_SYS_FLASH_BASE, &flash_info[0]); |
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flash_get_offsets (CONFIG_SYS_FLASH_BASE, &flash_info[0]); |
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#if CONFIG_SYS_MONITOR_BASE >= CONFIG_SYS_FLASH_BASE |
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/* If Monitor is in the cope of FLASH,then
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* protect this area by default in case for |
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* other occupation. [SAM] */ |
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/* monitor protection ON by default */ |
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flash_protect(FLAG_PROTECT_SET, |
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CONFIG_SYS_MONITOR_BASE, |
|
||||||
CONFIG_SYS_MONITOR_BASE+CONFIG_SYS_MONITOR_LEN-1, |
|
||||||
&flash_info[0]); |
|
||||||
#endif |
|
||||||
flash_info[0].size = size_b0; |
|
||||||
return (size_b0); |
|
||||||
} |
|
||||||
|
|
||||||
static void flash_get_offsets (ulong base, flash_info_t *info) |
|
||||||
{ |
|
||||||
int i; |
|
||||||
|
|
||||||
/* set up sector start address table */ |
|
||||||
if (info->flash_id & FLASH_BTYPE) { |
|
||||||
info->start[0] = base + 0x00000000; |
|
||||||
info->start[1] = base + 0x00008000; |
|
||||||
info->start[2] = base + 0x00010000; |
|
||||||
info->start[3] = base + 0x00018000; |
|
||||||
info->start[4] = base + 0x00020000; |
|
||||||
info->start[5] = base + 0x00028000; |
|
||||||
info->start[6] = base + 0x00030000; |
|
||||||
info->start[7] = base + 0x00038000; |
|
||||||
|
|
||||||
for (i = 8; i < info->sector_count; i++) { |
|
||||||
info->start[i] = base + ((i-7) * 0x00040000); |
|
||||||
} |
|
||||||
} else { |
|
||||||
i = info->sector_count - 1; |
|
||||||
info->start[i--] = base + info->size - 0x00010000; |
|
||||||
info->start[i--] = base + info->size - 0x00018000; |
|
||||||
info->start[i--] = base + info->size - 0x00020000; |
|
||||||
for (; i >= 0; i--) { |
|
||||||
info->start[i] = base + i * 0x00040000; |
|
||||||
} |
|
||||||
} |
|
||||||
|
|
||||||
} |
|
||||||
|
|
||||||
void flash_print_info (flash_info_t *info) |
|
||||||
{ |
|
||||||
int i; |
|
||||||
|
|
||||||
if (info->flash_id == FLASH_UNKNOWN) { |
|
||||||
printf ("missing or unknown FLASH type\n"); |
|
||||||
return; |
|
||||||
} |
|
||||||
|
|
||||||
switch (info->flash_id & FLASH_VENDMASK) { |
|
||||||
case FLASH_MAN_AMD: printf ("AMD "); break; |
|
||||||
case FLASH_MAN_FUJ: printf ("FUJITSU "); break; |
|
||||||
default: printf ("Unknown Vendor "); break; |
|
||||||
} |
|
||||||
|
|
||||||
switch (info->flash_id & FLASH_TYPEMASK) { |
|
||||||
case FLASH_AM400B: printf ("AM29LV400B (4 Mbit, bottom boot sect)\n"); |
|
||||||
break; |
|
||||||
case FLASH_AM400T: printf ("AM29LV400T (4 Mbit, top boot sector)\n"); |
|
||||||
break; |
|
||||||
case FLASH_AM800B: printf ("AM29LV800B (8 Mbit, bottom boot sect)\n"); |
|
||||||
break; |
|
||||||
case FLASH_AM800T: printf ("AM29LV800T (8 Mbit, top boot sector)\n"); |
|
||||||
break; |
|
||||||
case FLASH_AM160B: printf ("AM29LV160B (16 Mbit, bottom boot sect)\n"); |
|
||||||
break; |
|
||||||
case FLASH_AM160T: printf ("AM29LV160T (16 Mbit, top boot sector)\n"); |
|
||||||
break; |
|
||||||
case FLASH_AM320B: printf ("AM29LV320B (32 Mbit, bottom boot sect)\n"); |
|
||||||
break; |
|
||||||
case FLASH_AM320T: printf ("AM29LV320T (32 Mbit, top boot sector)\n"); |
|
||||||
break; |
|
||||||
case FLASH_AMDL323B: printf ("AM29DL323B (32 Mbit, bottom boot sector)\n"); |
|
||||||
break; |
|
||||||
/* I just add the FLASH_AMDL323B for RPXlite_DW BOARD. [SAM] */ |
|
||||||
default: printf ("Unknown Chip Type\n"); |
|
||||||
break; |
|
||||||
} |
|
||||||
printf (" Size: %ld MB in %d Sectors\n",info->size >> 20, info->sector_count); |
|
||||||
printf (" Sector Start Addresses:"); |
|
||||||
for (i=0; i<info->sector_count; ++i) { |
|
||||||
if ((i % 5) == 0) |
|
||||||
printf ("\n "); |
|
||||||
printf (" %08lX%s",info->start[i],info->protect[i] ? " (RO)" : " "); |
|
||||||
} |
|
||||||
printf ("\n"); |
|
||||||
return; |
|
||||||
} |
|
||||||
|
|
||||||
static ulong flash_get_size (vu_long *addr, flash_info_t *info) |
|
||||||
{ |
|
||||||
short i; |
|
||||||
ulong value; |
|
||||||
ulong base = (ulong)addr; |
|
||||||
|
|
||||||
/* Write auto select command: read Manufacturer ID */ |
|
||||||
addr[0xAAA] = 0x00AA00AA ; |
|
||||||
addr[0x555] = 0x00550055 ; |
|
||||||
addr[0xAAA] = 0x00900090 ; |
|
||||||
|
|
||||||
value = addr[0] ; |
|
||||||
switch (value & 0x00FF00FF) { |
|
||||||
case AMD_MANUFACT: /* AMD_MANUFACT =0x00010001 in flash.h */ |
|
||||||
info->flash_id = FLASH_MAN_AMD; /* FLASH_MAN_AMD=0x00000000 in flash.h */ |
|
||||||
break; |
|
||||||
case FUJ_MANUFACT: |
|
||||||
info->flash_id = FLASH_MAN_FUJ; |
|
||||||
break; |
|
||||||
default: |
|
||||||
info->flash_id = FLASH_UNKNOWN; |
|
||||||
info->sector_count = 0; |
|
||||||
info->size = 0; |
|
||||||
return (0); /* no or unknown flash */ |
|
||||||
} |
|
||||||
|
|
||||||
value = addr[2] ; /* device ID */ |
|
||||||
switch (value & 0x00FF00FF) { |
|
||||||
case (AMD_ID_LV400T & 0x00FF00FF): |
|
||||||
info->flash_id += FLASH_AM400T; |
|
||||||
info->sector_count = 11; |
|
||||||
info->size = 0x00100000; |
|
||||||
break; /* => 1 MB */ |
|
||||||
case (AMD_ID_LV400B & 0x00FF00FF): |
|
||||||
info->flash_id += FLASH_AM400B; |
|
||||||
info->sector_count = 11; |
|
||||||
info->size = 0x00100000; |
|
||||||
break; /* => 1 MB */ |
|
||||||
case (AMD_ID_LV800T & 0x00FF00FF): |
|
||||||
info->flash_id += FLASH_AM800T; |
|
||||||
info->sector_count = 19; |
|
||||||
info->size = 0x00200000; |
|
||||||
break; /* => 2 MB */ |
|
||||||
case (AMD_ID_LV800B & 0x00FF00FF): |
|
||||||
info->flash_id += FLASH_AM800B; |
|
||||||
info->sector_count = 19; |
|
||||||
info->size = 0x00400000; /* Size doubled by yooth */ |
|
||||||
break; /* => 4 MB */ |
|
||||||
case (AMD_ID_LV160T & 0x00FF00FF): |
|
||||||
info->flash_id += FLASH_AM160T; |
|
||||||
info->sector_count = 35; |
|
||||||
info->size = 0x00400000; |
|
||||||
break; /* => 4 MB */ |
|
||||||
case (AMD_ID_LV160B & 0x00FF00FF): |
|
||||||
info->flash_id += FLASH_AM160B; |
|
||||||
info->sector_count = 35; |
|
||||||
info->size = 0x00400000; |
|
||||||
break; /* => 4 MB */ |
|
||||||
case (AMD_ID_DL323B & 0x00FF00FF): |
|
||||||
info->flash_id += FLASH_AMDL323B; |
|
||||||
info->sector_count = 71; |
|
||||||
info->size = 0x01000000; |
|
||||||
break; /* => 16 MB(4x4MB) */ |
|
||||||
/* AMD_ID_DL323B= 0x22532253 FLASH_AMDL323B= 0x0013
|
|
||||||
* AMD_ID_DL323B could be found in <flash.h>.[SAM] |
|
||||||
* So we could get : flash_id = 0x00000013. |
|
||||||
* The first four-bit represents VEDOR ID,leaving others for FLASH ID. */ |
|
||||||
default: |
|
||||||
info->flash_id = FLASH_UNKNOWN; |
|
||||||
return (0); /* => no or unknown flash */ |
|
||||||
|
|
||||||
} |
|
||||||
/* set up sector start address table */ |
|
||||||
if (info->flash_id & FLASH_BTYPE) { |
|
||||||
/* FLASH_BTYPE=0x0001 mask for bottom boot sector type.If the last bit equals 1,
|
|
||||||
* it means bottom boot flash. GOOD IDEA! [SAM] |
|
||||||
*/ |
|
||||||
|
|
||||||
/* set sector offsets for bottom boot block type */ |
|
||||||
info->start[0] = base + 0x00000000; |
|
||||||
info->start[1] = base + 0x00008000; |
|
||||||
info->start[2] = base + 0x00010000; |
|
||||||
info->start[3] = base + 0x00018000; |
|
||||||
info->start[4] = base + 0x00020000; |
|
||||||
info->start[5] = base + 0x00028000; |
|
||||||
info->start[6] = base + 0x00030000; |
|
||||||
info->start[7] = base + 0x00038000; |
|
||||||
|
|
||||||
for (i = 8; i < info->sector_count; i++) { |
|
||||||
info->start[i] = base + ((i-7) * 0x00040000) ; |
|
||||||
} |
|
||||||
} else { |
|
||||||
/* set sector offsets for top boot block type */ |
|
||||||
i = info->sector_count - 1; |
|
||||||
info->start[i--] = base + info->size - 0x00010000; |
|
||||||
info->start[i--] = base + info->size - 0x00018000; |
|
||||||
info->start[i--] = base + info->size - 0x00020000; |
|
||||||
for (; i >= 0; i--) { |
|
||||||
info->start[i] = base + i * 0x00040000; |
|
||||||
} |
|
||||||
} |
|
||||||
|
|
||||||
/* check for protected sectors */ |
|
||||||
for (i = 0; i < info->sector_count; i++) { |
|
||||||
/* read sector protection at sector address, (A7 .. A0) = 0x02 */ |
|
||||||
/* D0 = 1 if protected */ |
|
||||||
addr = (volatile unsigned long *)(info->start[i]); |
|
||||||
/* info->protect[i] = addr[4] & 1 ; */ |
|
||||||
/* Mask it for disorder FLASH protection **[Sam]** */ |
|
||||||
} |
|
||||||
|
|
||||||
/*
|
|
||||||
* Prevent writes to uninitialized FLASH. |
|
||||||
*/ |
|
||||||
if (info->flash_id != FLASH_UNKNOWN) { |
|
||||||
addr = (volatile unsigned long *)info->start[0]; |
|
||||||
|
|
||||||
*addr = 0xF0F0F0F0; /* reset bank */ |
|
||||||
} |
|
||||||
return (info->size); |
|
||||||
} |
|
||||||
|
|
||||||
int flash_erase (flash_info_t *info, int s_first, int s_last) |
|
||||||
{ |
|
||||||
vu_long *addr = (vu_long*)(info->start[0]); |
|
||||||
int flag, prot, sect, l_sect; |
|
||||||
ulong start, now, last; |
|
||||||
|
|
||||||
if ((s_first < 0) || (s_first > s_last)) { |
|
||||||
if (info->flash_id == FLASH_UNKNOWN) { |
|
||||||
printf ("- missing\n"); |
|
||||||
} else { |
|
||||||
printf ("- no sectors to erase\n"); |
|
||||||
} |
|
||||||
return 1; |
|
||||||
} |
|
||||||
|
|
||||||
if ((info->flash_id == FLASH_UNKNOWN) || |
|
||||||
(info->flash_id > FLASH_AMD_COMP)) { |
|
||||||
printf ("Can't erase unknown flash type %08lx - aborted\n", |
|
||||||
info->flash_id); |
|
||||||
return 1; |
|
||||||
} |
|
||||||
|
|
||||||
prot = 0; |
|
||||||
for (sect=s_first; sect<=s_last; ++sect) { |
|
||||||
if (info->protect[sect]) { |
|
||||||
prot++; |
|
||||||
} |
|
||||||
} |
|
||||||
|
|
||||||
if (prot) { |
|
||||||
printf ("- Warning: %d protected sectors will not be erased!\n", |
|
||||||
prot); |
|
||||||
} else { |
|
||||||
printf ("\n"); |
|
||||||
} |
|
||||||
|
|
||||||
l_sect = -1; |
|
||||||
|
|
||||||
/* Disable interrupts which might cause a timeout here */ |
|
||||||
flag = disable_interrupts(); |
|
||||||
|
|
||||||
addr[0xAAA] = 0xAAAAAAAA; |
|
||||||
addr[0x555] = 0x55555555; |
|
||||||
addr[0xAAA] = 0x80808080; |
|
||||||
addr[0xAAA] = 0xAAAAAAAA; |
|
||||||
addr[0x555] = 0x55555555; |
|
||||||
|
|
||||||
/* Start erase on unprotected sectors */ |
|
||||||
for (sect = s_first; sect<=s_last; sect++) { |
|
||||||
if (info->protect[sect] == 0) { /* not protected */ |
|
||||||
addr = (vu_long *)(info->start[sect]) ; |
|
||||||
addr[0] = 0x30303030 ; |
|
||||||
l_sect = sect; |
|
||||||
} |
|
||||||
} |
|
||||||
|
|
||||||
/* re-enable interrupts if necessary */ |
|
||||||
if (flag) |
|
||||||
enable_interrupts(); |
|
||||||
|
|
||||||
/* wait at least 80us - let's wait 1 ms */ |
|
||||||
udelay (1000); |
|
||||||
|
|
||||||
/*
|
|
||||||
* We wait for the last triggered sector |
|
||||||
*/ |
|
||||||
if (l_sect < 0) |
|
||||||
goto DONE; |
|
||||||
|
|
||||||
start = get_timer (0); |
|
||||||
last = start; |
|
||||||
addr = (vu_long *)(info->start[l_sect]); |
|
||||||
while ((addr[0] & 0x80808080) != 0x80808080) { |
|
||||||
if ((now = get_timer(start)) > CONFIG_SYS_FLASH_ERASE_TOUT) { |
|
||||||
printf ("Timeout\n"); |
|
||||||
return 1; |
|
||||||
} |
|
||||||
/* show that we're waiting */ |
|
||||||
if ((now - last) > 1000) { /* every second */ |
|
||||||
putc ('.'); |
|
||||||
last = now; |
|
||||||
} |
|
||||||
} |
|
||||||
|
|
||||||
DONE: |
|
||||||
/* reset to read mode */ |
|
||||||
addr = (vu_long *)info->start[0]; |
|
||||||
addr[0] = 0xF0F0F0F0; /* reset bank */ |
|
||||||
|
|
||||||
printf (" done\n"); |
|
||||||
return 0; |
|
||||||
} |
|
||||||
|
|
||||||
/*-----------------------------------------------------------------------
|
|
||||||
* Copy memory to flash, returns: |
|
||||||
* 0 - OK |
|
||||||
* 1 - write timeout |
|
||||||
* 2 - Flash not erased |
|
||||||
*/ |
|
||||||
|
|
||||||
int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt) |
|
||||||
{ |
|
||||||
ulong cp, wp, data; |
|
||||||
int i, l, rc; |
|
||||||
|
|
||||||
wp = (addr & ~3); /* get lower word aligned address */ |
|
||||||
|
|
||||||
/*
|
|
||||||
* handle unaligned start bytes |
|
||||||
*/ |
|
||||||
if ((l = addr - wp) != 0) { |
|
||||||
data = 0; |
|
||||||
for (i=0, cp=wp; i<l; ++i, ++cp) { |
|
||||||
data = (data << 8) | (*(uchar *)cp); |
|
||||||
} |
|
||||||
for (; i<4 && cnt>0; ++i) { |
|
||||||
data = (data << 8) | *src++; |
|
||||||
--cnt; |
|
||||||
++cp; |
|
||||||
} |
|
||||||
for (; cnt==0 && i<4; ++i, ++cp) { |
|
||||||
data = (data << 8) | (*(uchar *)cp); |
|
||||||
} |
|
||||||
|
|
||||||
if ((rc = write_word(info, wp, data)) != 0) { |
|
||||||
return (rc); |
|
||||||
} |
|
||||||
wp += 4; |
|
||||||
} |
|
||||||
|
|
||||||
/*
|
|
||||||
* handle word aligned part |
|
||||||
*/ |
|
||||||
while (cnt >= 4) { |
|
||||||
data = 0; |
|
||||||
for (i=0; i<4; ++i) { |
|
||||||
data = (data << 8) | *src++; |
|
||||||
} |
|
||||||
if ((rc = write_word(info, wp, data)) != 0) { |
|
||||||
return (rc); |
|
||||||
} |
|
||||||
wp += 4; |
|
||||||
cnt -= 4; |
|
||||||
} |
|
||||||
|
|
||||||
if (cnt == 0) { |
|
||||||
return (0); |
|
||||||
} |
|
||||||
|
|
||||||
/*
|
|
||||||
* handle unaligned tail bytes |
|
||||||
*/ |
|
||||||
data = 0; |
|
||||||
for (i=0, cp=wp; i<4 && cnt>0; ++i, ++cp) { |
|
||||||
data = (data << 8) | *src++; |
|
||||||
--cnt; |
|
||||||
} |
|
||||||
for (; i<4; ++i, ++cp) { |
|
||||||
data = (data << 8) | (*(uchar *)cp); |
|
||||||
} |
|
||||||
return (write_word(info, wp, data)); |
|
||||||
} |
|
||||||
|
|
||||||
/*-----------------------------------------------------------------------
|
|
||||||
* Write a word to Flash, returns: |
|
||||||
* 0 - OK |
|
||||||
* 1 - write timeout |
|
||||||
* 2 - Flash not erased |
|
||||||
*/ |
|
||||||
static int write_word (flash_info_t *info, ulong dest, ulong data) |
|
||||||
{ |
|
||||||
vu_long *addr = (vu_long *)(info->start[0]); |
|
||||||
ulong start; |
|
||||||
int flag; |
|
||||||
|
|
||||||
/* Check if Flash is (sufficiently) erased */ |
|
||||||
if ((*((vu_long *)dest) & data) != data) { |
|
||||||
return (2); |
|
||||||
} |
|
||||||
/* Disable interrupts which might cause a timeout here */ |
|
||||||
flag = disable_interrupts(); |
|
||||||
|
|
||||||
addr[0xAAA] = 0xAAAAAAAA; |
|
||||||
addr[0x555] = 0x55555555; |
|
||||||
addr[0xAAA] = 0xA0A0A0A0; |
|
||||||
|
|
||||||
*((vu_long *)dest) = data; |
|
||||||
|
|
||||||
/* re-enable interrupts if necessary */ |
|
||||||
if (flag) |
|
||||||
enable_interrupts(); |
|
||||||
|
|
||||||
/* data polling for D7 */ |
|
||||||
start = get_timer (0); |
|
||||||
while ((*((vu_long *)dest) & 0x80808080) != (data & 0x80808080)) { |
|
||||||
if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) { |
|
||||||
return (1); |
|
||||||
} |
|
||||||
} |
|
||||||
return (0); |
|
||||||
} |
|
||||||
@ -1,82 +0,0 @@ |
|||||||
/* |
|
||||||
* (C) Copyright 2000-2010 |
|
||||||
* Wolfgang Denk, DENX Software Engineering, wd@denx.de. |
|
||||||
* |
|
||||||
* SPDX-License-Identifier: GPL-2.0+ |
|
||||||
*/ |
|
||||||
|
|
||||||
OUTPUT_ARCH(powerpc) |
|
||||||
|
|
||||||
SECTIONS |
|
||||||
{ |
|
||||||
/* Read-only sections, merged into text segment: */ |
|
||||||
. = + SIZEOF_HEADERS; |
|
||||||
.text : |
|
||||||
{ |
|
||||||
arch/powerpc/cpu/mpc8xx/start.o (.text*) |
|
||||||
arch/powerpc/cpu/mpc8xx/traps.o (.text*) |
|
||||||
|
|
||||||
*(.text*) |
|
||||||
} |
|
||||||
_etext = .; |
|
||||||
PROVIDE (etext = .); |
|
||||||
.rodata : |
|
||||||
{ |
|
||||||
*(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) |
|
||||||
} |
|
||||||
|
|
||||||
/* Read-write section, merged into data segment: */ |
|
||||||
. = (. + 0x00FF) & 0xFFFFFF00; |
|
||||||
_erotext = .; |
|
||||||
PROVIDE (erotext = .); |
|
||||||
.reloc : |
|
||||||
{ |
|
||||||
_GOT2_TABLE_ = .; |
|
||||||
KEEP(*(.got2)) |
|
||||||
KEEP(*(.got)) |
|
||||||
PROVIDE(_GLOBAL_OFFSET_TABLE_ = . + 4); |
|
||||||
_FIXUP_TABLE_ = .; |
|
||||||
KEEP(*(.fixup)) |
|
||||||
} |
|
||||||
__got2_entries = ((_GLOBAL_OFFSET_TABLE_ - _GOT2_TABLE_) >> 2) - 1; |
|
||||||
__fixup_entries = (. - _FIXUP_TABLE_)>>2; |
|
||||||
|
|
||||||
.data : |
|
||||||
{ |
|
||||||
*(.data*) |
|
||||||
*(.sdata*) |
|
||||||
} |
|
||||||
_edata = .; |
|
||||||
PROVIDE (edata = .); |
|
||||||
|
|
||||||
. = .; |
|
||||||
|
|
||||||
. = ALIGN(4); |
|
||||||
.u_boot_list : { |
|
||||||
KEEP(*(SORT(.u_boot_list*))); |
|
||||||
} |
|
||||||
|
|
||||||
|
|
||||||
. = .; |
|
||||||
__start___ex_table = .; |
|
||||||
__ex_table : { *(__ex_table) } |
|
||||||
__stop___ex_table = .; |
|
||||||
|
|
||||||
. = ALIGN(256); |
|
||||||
__init_begin = .; |
|
||||||
.text.init : { *(.text.init) } |
|
||||||
.data.init : { *(.data.init) } |
|
||||||
. = ALIGN(256); |
|
||||||
__init_end = .; |
|
||||||
|
|
||||||
__bss_start = .; |
|
||||||
.bss (NOLOAD) : |
|
||||||
{ |
|
||||||
*(.bss*) |
|
||||||
*(.sbss*) |
|
||||||
*(COMMON) |
|
||||||
. = ALIGN(4); |
|
||||||
} |
|
||||||
__bss_end = . ; |
|
||||||
PROVIDE (end = .); |
|
||||||
} |
|
||||||
@ -1,121 +0,0 @@ |
|||||||
/* |
|
||||||
* (C) Copyright 2000-2004 |
|
||||||
* Wolfgang Denk, DENX Software Engineering, wd@denx.de. |
|
||||||
* |
|
||||||
* SPDX-License-Identifier: GPL-2.0+ |
|
||||||
*/ |
|
||||||
|
|
||||||
OUTPUT_ARCH(powerpc) |
|
||||||
/* Do we need any of these for elf? |
|
||||||
__DYNAMIC = 0; */ |
|
||||||
SECTIONS |
|
||||||
{ |
|
||||||
/* Read-only sections, merged into text segment: */ |
|
||||||
. = + SIZEOF_HEADERS; |
|
||||||
.interp : { *(.interp) } |
|
||||||
.hash : { *(.hash) } |
|
||||||
.dynsym : { *(.dynsym) } |
|
||||||
.dynstr : { *(.dynstr) } |
|
||||||
.rel.text : { *(.rel.text) } |
|
||||||
.rela.text : { *(.rela.text) } |
|
||||||
.rel.data : { *(.rel.data) } |
|
||||||
.rela.data : { *(.rela.data) } |
|
||||||
.rel.rodata : { *(.rel.rodata) } |
|
||||||
.rela.rodata : { *(.rela.rodata) } |
|
||||||
.rel.got : { *(.rel.got) } |
|
||||||
.rela.got : { *(.rela.got) } |
|
||||||
.rel.ctors : { *(.rel.ctors) } |
|
||||||
.rela.ctors : { *(.rela.ctors) } |
|
||||||
.rel.dtors : { *(.rel.dtors) } |
|
||||||
.rela.dtors : { *(.rela.dtors) } |
|
||||||
.rel.bss : { *(.rel.bss) } |
|
||||||
.rela.bss : { *(.rela.bss) } |
|
||||||
.rel.plt : { *(.rel.plt) } |
|
||||||
.rela.plt : { *(.rela.plt) } |
|
||||||
.init : { *(.init) } |
|
||||||
.plt : { *(.plt) } |
|
||||||
.text : |
|
||||||
{ |
|
||||||
/* WARNING - the following is hand-optimized to fit within */ |
|
||||||
/* the sector layout of our flash chips! XXX FIXME XXX */ |
|
||||||
|
|
||||||
arch/powerpc/cpu/mpc8xx/start.o (.text) |
|
||||||
common/dlmalloc.o (.text) |
|
||||||
lib/vsprintf.o (.text) |
|
||||||
lib/crc32.o (.text) |
|
||||||
|
|
||||||
. = env_offset; |
|
||||||
common/env_embedded.o(.text) |
|
||||||
|
|
||||||
*(.text) |
|
||||||
*(.got1) |
|
||||||
} |
|
||||||
_etext = .; |
|
||||||
PROVIDE (etext = .); |
|
||||||
.rodata : |
|
||||||
{ |
|
||||||
*(.rodata) |
|
||||||
*(.rodata1) |
|
||||||
*(.rodata.str1.4) |
|
||||||
*(.eh_frame) |
|
||||||
} |
|
||||||
.fini : { *(.fini) } =0 |
|
||||||
.ctors : { *(.ctors) } |
|
||||||
.dtors : { *(.dtors) } |
|
||||||
|
|
||||||
/* Read-write section, merged into data segment: */ |
|
||||||
. = (. + 0x0FFF) & 0xFFFFF000; |
|
||||||
_erotext = .; |
|
||||||
PROVIDE (erotext = .); |
|
||||||
.reloc : |
|
||||||
{ |
|
||||||
*(.got) |
|
||||||
_GOT2_TABLE_ = .; |
|
||||||
*(.got2) |
|
||||||
_FIXUP_TABLE_ = .; |
|
||||||
*(.fixup) |
|
||||||
} |
|
||||||
__got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2; |
|
||||||
__fixup_entries = (. - _FIXUP_TABLE_)>>2; |
|
||||||
|
|
||||||
.data : |
|
||||||
{ |
|
||||||
*(.data) |
|
||||||
*(.data1) |
|
||||||
*(.sdata) |
|
||||||
*(.sdata2) |
|
||||||
*(.dynamic) |
|
||||||
CONSTRUCTORS |
|
||||||
} |
|
||||||
_edata = .; |
|
||||||
PROVIDE (edata = .); |
|
||||||
|
|
||||||
|
|
||||||
. = ALIGN(4); |
|
||||||
.u_boot_list : { |
|
||||||
KEEP(*(SORT(.u_boot_list*))); |
|
||||||
} |
|
||||||
|
|
||||||
|
|
||||||
__start___ex_table = .; |
|
||||||
__ex_table : { *(__ex_table) } |
|
||||||
__stop___ex_table = .; |
|
||||||
|
|
||||||
. = ALIGN(4096); |
|
||||||
__init_begin = .; |
|
||||||
.text.init : { *(.text.init) } |
|
||||||
.data.init : { *(.data.init) } |
|
||||||
. = ALIGN(4096); |
|
||||||
__init_end = .; |
|
||||||
|
|
||||||
__bss_start = .; |
|
||||||
.bss : |
|
||||||
{ |
|
||||||
*(.sbss) *(.scommon) |
|
||||||
*(.dynbss) |
|
||||||
*(.bss) |
|
||||||
*(COMMON) |
|
||||||
} |
|
||||||
__bss_end = . ; |
|
||||||
PROVIDE (end = .); |
|
||||||
} |
|
||||||
@ -1,8 +0,0 @@ |
|||||||
#
|
|
||||||
# (C) Copyright 2000-2006
|
|
||||||
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
|
|
||||||
#
|
|
||||||
# SPDX-License-Identifier: GPL-2.0+
|
|
||||||
#
|
|
||||||
|
|
||||||
obj-y = quantum.o fpga.o
|
|
||||||
@ -1,247 +0,0 @@ |
|||||||
/*
|
|
||||||
* (C) Copyright 2001-2003 |
|
||||||
* Matthias Fuchs, esd gmbh germany, matthias.fuchs@esd-electronics.com |
|
||||||
* Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com |
|
||||||
* |
|
||||||
* SPDX-License-Identifier: GPL-2.0+ |
|
||||||
*/ |
|
||||||
/* The DEBUG define must be before common to enable debugging */ |
|
||||||
#undef DEBUG |
|
||||||
#include <common.h> |
|
||||||
#include <asm/processor.h> |
|
||||||
#include <command.h> |
|
||||||
#include "fpga.h" |
|
||||||
/* ------------------------------------------------------------------------- */ |
|
||||||
|
|
||||||
#define MAX_ONES 226 |
|
||||||
|
|
||||||
/* MPC850 port D */ |
|
||||||
#define PD(bit) (1 << (15 - (bit))) |
|
||||||
# define FPGA_INIT PD(11) /* FPGA init pin (ppc input) */ |
|
||||||
# define FPGA_PRG PD(12) /* FPGA program pin (ppc output) */ |
|
||||||
# define FPGA_CLK PD(13) /* FPGA clk pin (ppc output) */ |
|
||||||
# define FPGA_DATA PD(14) /* FPGA data pin (ppc output) */ |
|
||||||
# define FPGA_DONE PD(15) /* FPGA done pin (ppc input) */ |
|
||||||
|
|
||||||
|
|
||||||
/* DDR 0 - input, 1 - output */ |
|
||||||
#define FPGA_INIT_PDDIR FPGA_PRG | FPGA_CLK | FPGA_DATA /* just set outputs */ |
|
||||||
|
|
||||||
|
|
||||||
#define SET_FPGA(data) immr->im_ioport.iop_pddat = (data) |
|
||||||
#define GET_FPGA immr->im_ioport.iop_pddat |
|
||||||
|
|
||||||
#define FPGA_WRITE_1 { \ |
|
||||||
SET_FPGA(FPGA_PRG | FPGA_DATA); /* set clock to 0 */ \
|
|
||||||
SET_FPGA(FPGA_PRG | FPGA_DATA); /* set data to 1 */ \
|
|
||||||
SET_FPGA(FPGA_PRG | FPGA_CLK | FPGA_DATA); /* set clock to 1 */ \
|
|
||||||
SET_FPGA(FPGA_PRG | FPGA_CLK | FPGA_DATA);} /* set data to 1 */ |
|
||||||
|
|
||||||
#define FPGA_WRITE_0 { \ |
|
||||||
SET_FPGA(FPGA_PRG | FPGA_DATA); /* set clock to 0 */ \
|
|
||||||
SET_FPGA(FPGA_PRG); /* set data to 0 */ \
|
|
||||||
SET_FPGA(FPGA_PRG | FPGA_CLK); /* set clock to 1 */ \
|
|
||||||
SET_FPGA(FPGA_PRG | FPGA_CLK | FPGA_DATA);} /* set data to 1 */ |
|
||||||
|
|
||||||
|
|
||||||
int fpga_boot (unsigned char *fpgadata, int size) |
|
||||||
{ |
|
||||||
volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR; |
|
||||||
int i, index, len; |
|
||||||
int count; |
|
||||||
|
|
||||||
#ifdef CONFIG_SYS_FPGA_SPARTAN2 |
|
||||||
int j; |
|
||||||
unsigned char data; |
|
||||||
#else |
|
||||||
unsigned char b; |
|
||||||
int bit; |
|
||||||
#endif |
|
||||||
|
|
||||||
debug ("fpga_boot: fpgadata = %p, size = %d\n", fpgadata, size); |
|
||||||
|
|
||||||
/* display infos on fpgaimage */ |
|
||||||
printf ("FPGA:"); |
|
||||||
index = 15; |
|
||||||
for (i = 0; i < 4; i++) { |
|
||||||
len = fpgadata[index]; |
|
||||||
printf (" %s", &(fpgadata[index + 1])); |
|
||||||
index += len + 3; |
|
||||||
} |
|
||||||
printf ("\n"); |
|
||||||
|
|
||||||
|
|
||||||
index = 0; |
|
||||||
|
|
||||||
#ifdef CONFIG_SYS_FPGA_SPARTAN2 |
|
||||||
/* search for preamble 0xFFFFFFFF */ |
|
||||||
while (1) { |
|
||||||
if ((fpgadata[index] == 0xff) && (fpgadata[index + 1] == 0xff) |
|
||||||
&& (fpgadata[index + 2] == 0xff) |
|
||||||
&& (fpgadata[index + 3] == 0xff)) |
|
||||||
break; /* preamble found */ |
|
||||||
else |
|
||||||
index++; |
|
||||||
} |
|
||||||
#else |
|
||||||
/* search for preamble 0xFF2X */ |
|
||||||
for (index = 0; index < size - 1; index++) { |
|
||||||
if ((fpgadata[index] == 0xff) |
|
||||||
&& ((fpgadata[index + 1] & 0xf0) == 0x30)) |
|
||||||
break; |
|
||||||
} |
|
||||||
index += 2; |
|
||||||
#endif |
|
||||||
|
|
||||||
debug ("FPGA: configdata starts at position 0x%x\n", index); |
|
||||||
debug ("FPGA: length of fpga-data %d\n", size - index); |
|
||||||
|
|
||||||
/*
|
|
||||||
* Setup port pins for fpga programming |
|
||||||
*/ |
|
||||||
immr->im_ioport.iop_pddir = FPGA_INIT_PDDIR; |
|
||||||
|
|
||||||
debug ("%s, ", ((GET_FPGA & FPGA_DONE) == 0) ? "NOT DONE" : "DONE"); |
|
||||||
debug ("%s\n", ((GET_FPGA & FPGA_INIT) == 0) ? "NOT INIT" : "INIT"); |
|
||||||
|
|
||||||
/*
|
|
||||||
* Init fpga by asserting and deasserting PROGRAM* |
|
||||||
*/ |
|
||||||
SET_FPGA (FPGA_CLK | FPGA_DATA); |
|
||||||
|
|
||||||
/* Wait for FPGA init line low */ |
|
||||||
count = 0; |
|
||||||
while (GET_FPGA & FPGA_INIT) { |
|
||||||
udelay (1000); /* wait 1ms */ |
|
||||||
/* Check for timeout - 100us max, so use 3ms */ |
|
||||||
if (count++ > 3) { |
|
||||||
debug ("FPGA: Booting failed!\n"); |
|
||||||
return ERROR_FPGA_PRG_INIT_LOW; |
|
||||||
} |
|
||||||
} |
|
||||||
|
|
||||||
debug ("%s, ", ((GET_FPGA & FPGA_DONE) == 0) ? "NOT DONE" : "DONE"); |
|
||||||
debug ("%s\n", ((GET_FPGA & FPGA_INIT) == 0) ? "NOT INIT" : "INIT"); |
|
||||||
|
|
||||||
/* deassert PROGRAM* */ |
|
||||||
SET_FPGA (FPGA_PRG | FPGA_CLK | FPGA_DATA); |
|
||||||
|
|
||||||
/* Wait for FPGA end of init period . */ |
|
||||||
count = 0; |
|
||||||
while (!(GET_FPGA & FPGA_INIT)) { |
|
||||||
udelay (1000); /* wait 1ms */ |
|
||||||
/* Check for timeout */ |
|
||||||
if (count++ > 3) { |
|
||||||
debug ("FPGA: Booting failed!\n"); |
|
||||||
return ERROR_FPGA_PRG_INIT_HIGH; |
|
||||||
} |
|
||||||
} |
|
||||||
|
|
||||||
debug ("%s, ", ((GET_FPGA & FPGA_DONE) == 0) ? "NOT DONE" : "DONE"); |
|
||||||
debug ("%s\n", ((GET_FPGA & FPGA_INIT) == 0) ? "NOT INIT" : "INIT"); |
|
||||||
|
|
||||||
debug ("write configuration data into fpga\n"); |
|
||||||
/* write configuration-data into fpga... */ |
|
||||||
|
|
||||||
#ifdef CONFIG_SYS_FPGA_SPARTAN2 |
|
||||||
/*
|
|
||||||
* Load uncompressed image into fpga |
|
||||||
*/ |
|
||||||
for (i = index; i < size; i++) { |
|
||||||
#ifdef CONFIG_SYS_FPGA_PROG_FEEDBACK |
|
||||||
if ((i % 1024) == 0) |
|
||||||
printf ("%6d out of %6d\r", i, size); /* let them know we are alive */ |
|
||||||
#endif |
|
||||||
|
|
||||||
data = fpgadata[i]; |
|
||||||
for (j = 0; j < 8; j++) { |
|
||||||
if ((data & 0x80) == 0x80) { |
|
||||||
FPGA_WRITE_1; |
|
||||||
} else { |
|
||||||
FPGA_WRITE_0; |
|
||||||
} |
|
||||||
data <<= 1; |
|
||||||
} |
|
||||||
} |
|
||||||
/* add some 0xff to the end of the file */ |
|
||||||
for (i = 0; i < 8; i++) { |
|
||||||
data = 0xff; |
|
||||||
for (j = 0; j < 8; j++) { |
|
||||||
if ((data & 0x80) == 0x80) { |
|
||||||
FPGA_WRITE_1; |
|
||||||
} else { |
|
||||||
FPGA_WRITE_0; |
|
||||||
} |
|
||||||
data <<= 1; |
|
||||||
} |
|
||||||
} |
|
||||||
#else |
|
||||||
/* send 0xff 0x20 */ |
|
||||||
FPGA_WRITE_1; |
|
||||||
FPGA_WRITE_1; |
|
||||||
FPGA_WRITE_1; |
|
||||||
FPGA_WRITE_1; |
|
||||||
FPGA_WRITE_1; |
|
||||||
FPGA_WRITE_1; |
|
||||||
FPGA_WRITE_1; |
|
||||||
FPGA_WRITE_1; |
|
||||||
FPGA_WRITE_0; |
|
||||||
FPGA_WRITE_0; |
|
||||||
FPGA_WRITE_1; |
|
||||||
FPGA_WRITE_0; |
|
||||||
FPGA_WRITE_0; |
|
||||||
FPGA_WRITE_0; |
|
||||||
FPGA_WRITE_0; |
|
||||||
FPGA_WRITE_0; |
|
||||||
|
|
||||||
/*
|
|
||||||
** Bit_DeCompression |
|
||||||
** Code 1 .. maxOnes : n '1's followed by '0' |
|
||||||
** maxOnes + 1 .. maxOnes + 1 : n - 1 '1's no '0' |
|
||||||
** maxOnes + 2 .. 254 : n - (maxOnes + 2) '0's followed by '1' |
|
||||||
** 255 : '1' |
|
||||||
*/ |
|
||||||
|
|
||||||
for (i = index; i < size; i++) { |
|
||||||
b = fpgadata[i]; |
|
||||||
if ((b >= 1) && (b <= MAX_ONES)) { |
|
||||||
for (bit = 0; bit < b; bit++) { |
|
||||||
FPGA_WRITE_1; |
|
||||||
} |
|
||||||
FPGA_WRITE_0; |
|
||||||
} else if (b == (MAX_ONES + 1)) { |
|
||||||
for (bit = 1; bit < b; bit++) { |
|
||||||
FPGA_WRITE_1; |
|
||||||
} |
|
||||||
} else if ((b >= (MAX_ONES + 2)) && (b <= 254)) { |
|
||||||
for (bit = 0; bit < (b - (MAX_ONES + 2)); bit++) { |
|
||||||
FPGA_WRITE_0; |
|
||||||
} |
|
||||||
FPGA_WRITE_1; |
|
||||||
} else if (b == 255) { |
|
||||||
FPGA_WRITE_1; |
|
||||||
} |
|
||||||
} |
|
||||||
#endif |
|
||||||
debug ("\n\n"); |
|
||||||
debug ("%s, ", ((GET_FPGA & FPGA_DONE) == 0) ? "NOT DONE" : "DONE"); |
|
||||||
debug ("%s\n", ((GET_FPGA & FPGA_INIT) == 0) ? "NOT INIT" : "INIT"); |
|
||||||
|
|
||||||
/*
|
|
||||||
* Check if fpga's DONE signal - correctly booted ? |
|
||||||
*/ |
|
||||||
|
|
||||||
/* Wait for FPGA end of programming period . */ |
|
||||||
count = 0; |
|
||||||
while (!(GET_FPGA & FPGA_DONE)) { |
|
||||||
udelay (1000); /* wait 1ms */ |
|
||||||
/* Check for timeout */ |
|
||||||
if (count++ > 3) { |
|
||||||
debug ("FPGA: Booting failed!\n"); |
|
||||||
return ERROR_FPGA_PRG_DONE; |
|
||||||
} |
|
||||||
} |
|
||||||
|
|
||||||
debug ("FPGA: Booting successful!\n"); |
|
||||||
return 0; |
|
||||||
} |
|
||||||
@ -1,16 +0,0 @@ |
|||||||
/*
|
|
||||||
* (C) Copyright 2002 |
|
||||||
* Rich Ireland, Enterasys Networks, rireland@enterasys.com. |
|
||||||
* Keith Outwater, keith_outwater@mvis.com. |
|
||||||
* |
|
||||||
* SPDX-License-Identifier: GPL-2.0+ |
|
||||||
*/ |
|
||||||
|
|
||||||
/*
|
|
||||||
* Virtex2 FPGA configuration support for the QUANTUM computer |
|
||||||
*/ |
|
||||||
int fpga_boot(unsigned char *fpgadata, int size); |
|
||||||
|
|
||||||
#define ERROR_FPGA_PRG_INIT_LOW -1 /* Timeout after PRG* asserted */ |
|
||||||
#define ERROR_FPGA_PRG_INIT_HIGH -2 /* Timeout after PRG* deasserted */ |
|
||||||
#define ERROR_FPGA_PRG_DONE -3 /* Timeout after programming */ |
|
||||||
@ -1,243 +0,0 @@ |
|||||||
/*
|
|
||||||
* (C) Copyright 2000 |
|
||||||
* Wolfgang Denk, DENX Software Engineering, wd@denx.de. |
|
||||||
* |
|
||||||
* SPDX-License-Identifier: GPL-2.0+ |
|
||||||
*/ |
|
||||||
|
|
||||||
|
|
||||||
#include <common.h> |
|
||||||
#include <mpc8xx.h> |
|
||||||
#include "fpga.h" |
|
||||||
|
|
||||||
/* ------------------------------------------------------------------------- */ |
|
||||||
|
|
||||||
static long int dram_size (long int, long int *, long int); |
|
||||||
unsigned long flash_init (void); |
|
||||||
|
|
||||||
/* ------------------------------------------------------------------------- */ |
|
||||||
|
|
||||||
#define _NOT_USED_ 0xFFFFCC25 |
|
||||||
|
|
||||||
const uint sdram_table[] = { |
|
||||||
/*
|
|
||||||
* Single Read. (Offset 00h in UPMA RAM) |
|
||||||
*/ |
|
||||||
0x0F03CC04, 0x00ACCC24, 0x1FF74C20, _NOT_USED_, |
|
||||||
_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, |
|
||||||
|
|
||||||
/*
|
|
||||||
* Burst Read. (Offset 08h in UPMA RAM) |
|
||||||
*/ |
|
||||||
0x0F03CC04, 0x00ACCC24, 0x00FFCC20, 0x00FFCC20, |
|
||||||
0x01FFCC20, 0x1FF74C20, _NOT_USED_, _NOT_USED_, |
|
||||||
_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, |
|
||||||
_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, |
|
||||||
|
|
||||||
/*
|
|
||||||
* Single Write. (Offset 18h in UPMA RAM) |
|
||||||
*/ |
|
||||||
0x0F03CC02, 0x00AC0C24, 0x1FF74C25, _NOT_USED_, |
|
||||||
_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, |
|
||||||
|
|
||||||
/*
|
|
||||||
* Burst Write. (Offset 20h in UPMA RAM) |
|
||||||
*/ |
|
||||||
0x0F03CC00, 0x00AC0C20, 0x00FFFC20, 0x00FFFC22, |
|
||||||
0x01FFFC24, 0x1FF74C25, _NOT_USED_, _NOT_USED_, |
|
||||||
_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, |
|
||||||
_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, |
|
||||||
|
|
||||||
/*
|
|
||||||
* Refresh. (Offset 30h in UPMA RAM) |
|
||||||
* (Initialization code at 0x36) |
|
||||||
*/ |
|
||||||
0x0FF0CC24, 0xFFFFCC24, _NOT_USED_, _NOT_USED_, |
|
||||||
_NOT_USED_, _NOT_USED_, 0xEFFB8C34, 0x0FF74C34, |
|
||||||
0x0FFACCB4, 0x0FF5CC34, 0x0FFCC34, 0x0FFFCCB4, |
|
||||||
|
|
||||||
/*
|
|
||||||
* Exception. (Offset 3Ch in UPMA RAM) |
|
||||||
*/ |
|
||||||
0x0FEA8C34, 0x1FB54C34, 0xFFFFCC34, _NOT_USED_ |
|
||||||
}; |
|
||||||
|
|
||||||
/* ------------------------------------------------------------------------- */ |
|
||||||
|
|
||||||
|
|
||||||
/*
|
|
||||||
* Check Board Identity: |
|
||||||
*/ |
|
||||||
|
|
||||||
int checkboard (void) |
|
||||||
{ |
|
||||||
char buf[64]; |
|
||||||
int i; |
|
||||||
int l = getenv_f("serial#", buf, sizeof(buf)); |
|
||||||
|
|
||||||
puts ("Board QUANTUM, Serial No: "); |
|
||||||
|
|
||||||
for (i = 0; i < l; ++i) { |
|
||||||
if (buf[i] == ' ') |
|
||||||
break; |
|
||||||
putc (buf[i]); |
|
||||||
} |
|
||||||
putc ('\n'); |
|
||||||
return (0); /* success */ |
|
||||||
} |
|
||||||
|
|
||||||
/* ------------------------------------------------------------------------- */ |
|
||||||
|
|
||||||
phys_size_t initdram (int board_type) |
|
||||||
{ |
|
||||||
volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR; |
|
||||||
volatile memctl8xx_t *memctl = &immap->im_memctl; |
|
||||||
long int size9; |
|
||||||
|
|
||||||
upmconfig (UPMA, (uint *) sdram_table, |
|
||||||
sizeof (sdram_table) / sizeof (uint)); |
|
||||||
|
|
||||||
/* Refresh clock prescalar */ |
|
||||||
memctl->memc_mptpr = CONFIG_SYS_MPTPR; |
|
||||||
|
|
||||||
memctl->memc_mar = 0x00000088; |
|
||||||
|
|
||||||
/* Map controller banks 1 to the SDRAM bank */ |
|
||||||
memctl->memc_or1 = CONFIG_SYS_OR1_PRELIM; |
|
||||||
memctl->memc_br1 = CONFIG_SYS_BR1_PRELIM; |
|
||||||
|
|
||||||
memctl->memc_mamr = CONFIG_SYS_MAMR_9COL & (~(MAMR_PTAE)); /* no refresh yet */ |
|
||||||
|
|
||||||
udelay (200); |
|
||||||
|
|
||||||
/* perform SDRAM initializsation sequence */ |
|
||||||
|
|
||||||
memctl->memc_mcr = 0x80002136; /* SDRAM bank 0 */ |
|
||||||
udelay (1); |
|
||||||
|
|
||||||
memctl->memc_mamr |= MAMR_PTAE; /* enable refresh */ |
|
||||||
|
|
||||||
udelay (1000); |
|
||||||
|
|
||||||
/* Check Bank 0 Memory Size,
|
|
||||||
* 9 column mode |
|
||||||
*/ |
|
||||||
size9 = dram_size (CONFIG_SYS_MAMR_9COL, (long *) SDRAM_BASE_PRELIM, |
|
||||||
SDRAM_MAX_SIZE); |
|
||||||
/*
|
|
||||||
* Final mapping: |
|
||||||
*/ |
|
||||||
memctl->memc_or1 = ((-size9) & 0xFFFF0000) | CONFIG_SYS_OR_TIMING_SDRAM; |
|
||||||
udelay (1000); |
|
||||||
|
|
||||||
return (size9); |
|
||||||
} |
|
||||||
|
|
||||||
/* ------------------------------------------------------------------------- */ |
|
||||||
|
|
||||||
/*
|
|
||||||
* Check memory range for valid RAM. A simple memory test determines |
|
||||||
* the actually available RAM size between addresses `base' and |
|
||||||
* `base + maxsize'. Some (not all) hardware errors are detected: |
|
||||||
* - short between address lines |
|
||||||
* - short between data lines |
|
||||||
*/ |
|
||||||
|
|
||||||
static long int dram_size (long int mamr_value, long int *base, |
|
||||||
long int maxsize) |
|
||||||
{ |
|
||||||
volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR; |
|
||||||
volatile memctl8xx_t *memctl = &immap->im_memctl; |
|
||||||
volatile ulong *addr; |
|
||||||
ulong cnt, val, size; |
|
||||||
ulong save[32]; /* to make test non-destructive */ |
|
||||||
unsigned char i = 0; |
|
||||||
|
|
||||||
memctl->memc_mamr = mamr_value; |
|
||||||
|
|
||||||
for (cnt = maxsize / sizeof (long); cnt > 0; cnt >>= 1) { |
|
||||||
addr = (volatile ulong *)(base + cnt); /* pointer arith! */ |
|
||||||
|
|
||||||
save[i++] = *addr; |
|
||||||
*addr = ~cnt; |
|
||||||
} |
|
||||||
|
|
||||||
/* write 0 to base address */ |
|
||||||
addr = (volatile ulong *)base; |
|
||||||
save[i] = *addr; |
|
||||||
*addr = 0; |
|
||||||
|
|
||||||
/* check at base address */ |
|
||||||
if ((val = *addr) != 0) { |
|
||||||
/* Restore the original data before leaving the function.
|
|
||||||
*/ |
|
||||||
*addr = save[i]; |
|
||||||
for (cnt = 1; cnt <= maxsize / sizeof (long); cnt <<= 1) { |
|
||||||
addr = (volatile ulong *) base + cnt; |
|
||||||
*addr = save[--i]; |
|
||||||
} |
|
||||||
return (0); |
|
||||||
} |
|
||||||
|
|
||||||
for (cnt = 1; cnt <= maxsize / sizeof (long); cnt <<= 1) { |
|
||||||
addr = (volatile ulong *)(base + cnt); /* pointer arith! */ |
|
||||||
|
|
||||||
val = *addr; |
|
||||||
*addr = save[--i]; |
|
||||||
|
|
||||||
if (val != (~cnt)) { |
|
||||||
size = cnt * sizeof (long); |
|
||||||
/* Restore the original data before returning
|
|
||||||
*/ |
|
||||||
for (cnt <<= 1; cnt <= maxsize / sizeof (long); |
|
||||||
cnt <<= 1) { |
|
||||||
addr = (volatile ulong *) base + cnt; |
|
||||||
*addr = save[--i]; |
|
||||||
} |
|
||||||
return (size); |
|
||||||
} |
|
||||||
} |
|
||||||
return (maxsize); |
|
||||||
} |
|
||||||
|
|
||||||
/*
|
|
||||||
* Miscellaneous intialization |
|
||||||
*/ |
|
||||||
int misc_init_r (void) |
|
||||||
{ |
|
||||||
char *fpga_data_str = getenv ("fpgadata"); |
|
||||||
char *fpga_size_str = getenv ("fpgasize"); |
|
||||||
void *fpga_data; |
|
||||||
int fpga_size; |
|
||||||
int status; |
|
||||||
volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR; |
|
||||||
volatile memctl8xx_t *memctl = &immap->im_memctl; |
|
||||||
int flash_size; |
|
||||||
|
|
||||||
/* Remap FLASH according to real size */ |
|
||||||
flash_size = flash_init (); |
|
||||||
memctl->memc_or0 = CONFIG_SYS_OR_TIMING_FLASH | (-flash_size & 0xFFFF8000); |
|
||||||
memctl->memc_br0 = (CONFIG_SYS_FLASH_BASE & BR_BA_MSK) | BR_MS_GPCM | BR_V; |
|
||||||
|
|
||||||
if (fpga_data_str && fpga_size_str) { |
|
||||||
fpga_data = (void *) simple_strtoul (fpga_data_str, NULL, 16); |
|
||||||
fpga_size = simple_strtoul (fpga_size_str, NULL, 10); |
|
||||||
|
|
||||||
status = fpga_boot (fpga_data, fpga_size); |
|
||||||
if (status != 0) { |
|
||||||
printf ("\nFPGA: Booting failed "); |
|
||||||
switch (status) { |
|
||||||
case ERROR_FPGA_PRG_INIT_LOW: |
|
||||||
printf ("(Timeout: INIT not low after asserting PROGRAM*)\n "); |
|
||||||
break; |
|
||||||
case ERROR_FPGA_PRG_INIT_HIGH: |
|
||||||
printf ("(Timeout: INIT not high after deasserting PROGRAM*)\n "); |
|
||||||
break; |
|
||||||
case ERROR_FPGA_PRG_DONE: |
|
||||||
printf ("(Timeout: DONE not high after programming FPGA)\n "); |
|
||||||
break; |
|
||||||
} |
|
||||||
} |
|
||||||
} |
|
||||||
return 0; |
|
||||||
} |
|
||||||
@ -1,82 +0,0 @@ |
|||||||
/* |
|
||||||
* (C) Copyright 2000-2010 |
|
||||||
* Wolfgang Denk, DENX Software Engineering, wd@denx.de. |
|
||||||
* |
|
||||||
* SPDX-License-Identifier: GPL-2.0+ |
|
||||||
*/ |
|
||||||
|
|
||||||
OUTPUT_ARCH(powerpc) |
|
||||||
|
|
||||||
SECTIONS |
|
||||||
{ |
|
||||||
/* Read-only sections, merged into text segment: */ |
|
||||||
. = + SIZEOF_HEADERS; |
|
||||||
.text : |
|
||||||
{ |
|
||||||
arch/powerpc/cpu/mpc8xx/start.o (.text*) |
|
||||||
arch/powerpc/cpu/mpc8xx/traps.o (.text*) |
|
||||||
|
|
||||||
*(.text*) |
|
||||||
} |
|
||||||
_etext = .; |
|
||||||
PROVIDE (etext = .); |
|
||||||
.rodata : |
|
||||||
{ |
|
||||||
*(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) |
|
||||||
} |
|
||||||
|
|
||||||
/* Read-write section, merged into data segment: */ |
|
||||||
. = (. + 0x00FF) & 0xFFFFFF00; |
|
||||||
_erotext = .; |
|
||||||
PROVIDE (erotext = .); |
|
||||||
.reloc : |
|
||||||
{ |
|
||||||
_GOT2_TABLE_ = .; |
|
||||||
KEEP(*(.got2)) |
|
||||||
KEEP(*(.got)) |
|
||||||
PROVIDE(_GLOBAL_OFFSET_TABLE_ = . + 4); |
|
||||||
_FIXUP_TABLE_ = .; |
|
||||||
KEEP(*(.fixup)) |
|
||||||
} |
|
||||||
__got2_entries = ((_GLOBAL_OFFSET_TABLE_ - _GOT2_TABLE_) >> 2) - 1; |
|
||||||
__fixup_entries = (. - _FIXUP_TABLE_)>>2; |
|
||||||
|
|
||||||
.data : |
|
||||||
{ |
|
||||||
*(.data*) |
|
||||||
*(.sdata*) |
|
||||||
} |
|
||||||
_edata = .; |
|
||||||
PROVIDE (edata = .); |
|
||||||
|
|
||||||
. = .; |
|
||||||
|
|
||||||
. = ALIGN(4); |
|
||||||
.u_boot_list : { |
|
||||||
KEEP(*(SORT(.u_boot_list*))); |
|
||||||
} |
|
||||||
|
|
||||||
|
|
||||||
. = .; |
|
||||||
__start___ex_table = .; |
|
||||||
__ex_table : { *(__ex_table) } |
|
||||||
__stop___ex_table = .; |
|
||||||
|
|
||||||
. = ALIGN(256); |
|
||||||
__init_begin = .; |
|
||||||
.text.init : { *(.text.init) } |
|
||||||
.data.init : { *(.data.init) } |
|
||||||
. = ALIGN(256); |
|
||||||
__init_end = .; |
|
||||||
|
|
||||||
__bss_start = .; |
|
||||||
.bss (NOLOAD) : |
|
||||||
{ |
|
||||||
*(.bss*) |
|
||||||
*(.sbss*) |
|
||||||
*(COMMON) |
|
||||||
. = ALIGN(4); |
|
||||||
} |
|
||||||
__bss_end = . ; |
|
||||||
PROVIDE (end = .); |
|
||||||
} |
|
||||||
@ -1,114 +0,0 @@ |
|||||||
/* |
|
||||||
* (C) Copyright 2000 |
|
||||||
* Wolfgang Denk, DENX Software Engineering, wd@denx.de. |
|
||||||
* |
|
||||||
* SPDX-License-Identifier: GPL-2.0+ |
|
||||||
*/ |
|
||||||
|
|
||||||
OUTPUT_ARCH(powerpc) |
|
||||||
/* Do we need any of these for elf? |
|
||||||
__DYNAMIC = 0; */ |
|
||||||
SECTIONS |
|
||||||
{ |
|
||||||
/* Read-only sections, merged into text segment: */ |
|
||||||
. = + SIZEOF_HEADERS; |
|
||||||
.interp : { *(.interp) } |
|
||||||
.hash : { *(.hash) } |
|
||||||
.dynsym : { *(.dynsym) } |
|
||||||
.dynstr : { *(.dynstr) } |
|
||||||
.rel.text : { *(.rel.text) } |
|
||||||
.rela.text : { *(.rela.text) } |
|
||||||
.rel.data : { *(.rel.data) } |
|
||||||
.rela.data : { *(.rela.data) } |
|
||||||
.rel.rodata : { *(.rel.rodata) } |
|
||||||
.rela.rodata : { *(.rela.rodata) } |
|
||||||
.rel.got : { *(.rel.got) } |
|
||||||
.rela.got : { *(.rela.got) } |
|
||||||
.rel.ctors : { *(.rel.ctors) } |
|
||||||
.rela.ctors : { *(.rela.ctors) } |
|
||||||
.rel.dtors : { *(.rel.dtors) } |
|
||||||
.rela.dtors : { *(.rela.dtors) } |
|
||||||
.rel.bss : { *(.rel.bss) } |
|
||||||
.rela.bss : { *(.rela.bss) } |
|
||||||
.rel.plt : { *(.rel.plt) } |
|
||||||
.rela.plt : { *(.rela.plt) } |
|
||||||
.init : { *(.init) } |
|
||||||
.plt : { *(.plt) } |
|
||||||
.text : |
|
||||||
{ |
|
||||||
/* WARNING - the following is hand-optimized to fit within */ |
|
||||||
/* the sector layout of our flash chips! XXX FIXME XXX */ |
|
||||||
|
|
||||||
arch/powerpc/cpu/mpc8xx/start.o (.text) |
|
||||||
common/dlmalloc.o (.text) |
|
||||||
lib/vsprintf.o (.text) |
|
||||||
lib/crc32.o (.text) |
|
||||||
|
|
||||||
. = env_offset; |
|
||||||
common/env_embedded.o(.text) |
|
||||||
|
|
||||||
*(.text) |
|
||||||
*(.got1) |
|
||||||
} |
|
||||||
_etext = .; |
|
||||||
PROVIDE (etext = .); |
|
||||||
.rodata : |
|
||||||
{ |
|
||||||
*(.rodata) |
|
||||||
*(.rodata1) |
|
||||||
*(.rodata.str1.4) |
|
||||||
*(.eh_frame) |
|
||||||
} |
|
||||||
.fini : { *(.fini) } =0 |
|
||||||
.ctors : { *(.ctors) } |
|
||||||
.dtors : { *(.dtors) } |
|
||||||
|
|
||||||
/* Read-write section, merged into data segment: */ |
|
||||||
. = (. + 0x0FFF) & 0xFFFFF000; |
|
||||||
_erotext = .; |
|
||||||
PROVIDE (erotext = .); |
|
||||||
.reloc : |
|
||||||
{ |
|
||||||
*(.got) |
|
||||||
_GOT2_TABLE_ = .; |
|
||||||
*(.got2) |
|
||||||
_FIXUP_TABLE_ = .; |
|
||||||
*(.fixup) |
|
||||||
} |
|
||||||
__got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2; |
|
||||||
__fixup_entries = (. - _FIXUP_TABLE_)>>2; |
|
||||||
|
|
||||||
.data : |
|
||||||
{ |
|
||||||
*(.data) |
|
||||||
*(.data1) |
|
||||||
*(.sdata) |
|
||||||
*(.sdata2) |
|
||||||
*(.dynamic) |
|
||||||
CONSTRUCTORS |
|
||||||
} |
|
||||||
_edata = .; |
|
||||||
PROVIDE (edata = .); |
|
||||||
|
|
||||||
__start___ex_table = .; |
|
||||||
__ex_table : { *(__ex_table) } |
|
||||||
__stop___ex_table = .; |
|
||||||
|
|
||||||
. = ALIGN(4096); |
|
||||||
__init_begin = .; |
|
||||||
.text.init : { *(.text.init) } |
|
||||||
.data.init : { *(.data.init) } |
|
||||||
. = ALIGN(4096); |
|
||||||
__init_end = .; |
|
||||||
|
|
||||||
__bss_start = .; |
|
||||||
.bss : |
|
||||||
{ |
|
||||||
*(.sbss) *(.scommon) |
|
||||||
*(.dynbss) |
|
||||||
*(.bss) |
|
||||||
*(COMMON) |
|
||||||
} |
|
||||||
__bss_end = . ; |
|
||||||
PROVIDE (end = .); |
|
||||||
} |
|
||||||
@ -1,73 +0,0 @@ |
|||||||
/* -------------------------------------------------------------------- */ |
|
||||||
/* RPX Boards from Embedded Planet */ |
|
||||||
/* -------------------------------------------------------------------- */ |
|
||||||
#include <common.h> |
|
||||||
#ifdef CONFIG_8xx |
|
||||||
#include <mpc8xx.h> |
|
||||||
#endif |
|
||||||
#include <pcmcia.h> |
|
||||||
|
|
||||||
#undef CONFIG_PCMCIA |
|
||||||
|
|
||||||
#if defined(CONFIG_CMD_PCMCIA) |
|
||||||
#define CONFIG_PCMCIA |
|
||||||
#endif |
|
||||||
|
|
||||||
#if defined(CONFIG_CMD_IDE) && defined(CONFIG_IDE_8xx_PCCARD) |
|
||||||
#define CONFIG_PCMCIA |
|
||||||
#endif |
|
||||||
|
|
||||||
#if defined(CONFIG_PCMCIA) \ |
|
||||||
&& defined(CONFIG_RPXLITE) |
|
||||||
|
|
||||||
#define PCMCIA_BOARD_MSG "RPX CLASSIC or RPX LITE" |
|
||||||
|
|
||||||
int pcmcia_voltage_set(int slot, int vcc, int vpp) |
|
||||||
{ |
|
||||||
u_long reg = 0; |
|
||||||
|
|
||||||
switch(vcc) { |
|
||||||
case 0: break; |
|
||||||
case 33: reg |= BCSR1_PCVCTL4; break; |
|
||||||
case 50: reg |= BCSR1_PCVCTL5; break; |
|
||||||
default: return 1; |
|
||||||
} |
|
||||||
|
|
||||||
switch(vpp) { |
|
||||||
case 0: break; |
|
||||||
case 33: |
|
||||||
case 50: |
|
||||||
if(vcc == vpp) |
|
||||||
reg |= BCSR1_PCVCTL6; |
|
||||||
else |
|
||||||
return 1; |
|
||||||
break; |
|
||||||
case 120: |
|
||||||
reg |= BCSR1_PCVCTL7; |
|
||||||
default: return 1; |
|
||||||
} |
|
||||||
|
|
||||||
/* first, turn off all power */ |
|
||||||
*((uint *)RPX_CSR_ADDR) &= ~(BCSR1_PCVCTL4 | BCSR1_PCVCTL5 |
|
||||||
| BCSR1_PCVCTL6 | BCSR1_PCVCTL7); |
|
||||||
|
|
||||||
/* enable new powersettings */ |
|
||||||
*((uint *)RPX_CSR_ADDR) |= reg; |
|
||||||
|
|
||||||
return 0; |
|
||||||
} |
|
||||||
|
|
||||||
int pcmcia_hardware_enable (int slot) |
|
||||||
{ |
|
||||||
return 0; /* No hardware to enable */ |
|
||||||
} |
|
||||||
|
|
||||||
#if defined(CONFIG_CMD_PCMCIA) |
|
||||||
static int pcmcia_hardware_disable(int slot) |
|
||||||
{ |
|
||||||
return 0; /* No hardware to disable */ |
|
||||||
} |
|
||||||
#endif |
|
||||||
|
|
||||||
|
|
||||||
#endif /* CONFIG_PCMCIA && CONFIG_RPXLITE */ |
|
||||||
@ -1,462 +0,0 @@ |
|||||||
/*
|
|
||||||
* (C) Copyright 2004 |
|
||||||
* Wolfgang Denk, DENX Software Engineering, wd@denx.de. |
|
||||||
* Sam Song, IEMC. SHU, samsongshu@yahoo.com.cn |
|
||||||
* |
|
||||||
* SPDX-License-Identifier: GPL-2.0+ |
|
||||||
*/ |
|
||||||
|
|
||||||
/*
|
|
||||||
* board/config.h - configuration options, board specific |
|
||||||
*/ |
|
||||||
|
|
||||||
/* Yoo. Jonghoon, IPone, yooth@ipone.co.kr
|
|
||||||
* U-BOOT port on RPXlite board |
|
||||||
*/ |
|
||||||
|
|
||||||
/*
|
|
||||||
* Sam Song, IEMC. SHU, samsongshu@yahoo.com.cn |
|
||||||
* U-BOOT port on RPXlite DW version board--RPXlite_DW |
|
||||||
* June 8 ,2004 |
|
||||||
*/ |
|
||||||
|
|
||||||
#ifndef __CONFIG_H |
|
||||||
#define __CONFIG_H |
|
||||||
|
|
||||||
/*
|
|
||||||
* High Level Configuration Options |
|
||||||
* (easy to change) |
|
||||||
*/ |
|
||||||
|
|
||||||
/* #define DEBUG 1 */ |
|
||||||
/* #define DEPLOYMENT 1 */ |
|
||||||
|
|
||||||
#undef CONFIG_MPC860 |
|
||||||
#define CONFIG_MPC823 1 /* This is a MPC823e CPU. */ |
|
||||||
#define CONFIG_RPXLITE 1 /* RPXlite DW version board */ |
|
||||||
|
|
||||||
#define CONFIG_SYS_TEXT_BASE 0xff000000 |
|
||||||
|
|
||||||
#ifdef CONFIG_LCD /* with LCD controller ? */ |
|
||||||
#define CONFIG_MPC8XX_LCD |
|
||||||
#define CONFIG_SPLASH_SCREEN /* ... with splashscreen support*/ |
|
||||||
#endif |
|
||||||
|
|
||||||
#define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */ |
|
||||||
#undef CONFIG_8xx_CONS_SMC2 |
|
||||||
#undef CONFIG_8xx_CONS_NONE |
|
||||||
#define CONFIG_BAUDRATE 9600 /* console default baudrate = 9600bps */ |
|
||||||
|
|
||||||
#ifdef DEBUG |
|
||||||
#define CONFIG_BOOTDELAY -1 /* autoboot disabled */ |
|
||||||
#else |
|
||||||
#define CONFIG_BOOTDELAY 6 /* autoboot after 6 seconds */ |
|
||||||
|
|
||||||
#ifdef DEPLOYMENT |
|
||||||
#define CONFIG_BOOT_RETRY_TIME -1 |
|
||||||
#define CONFIG_AUTOBOOT_KEYED |
|
||||||
#define CONFIG_AUTOBOOT_PROMPT \ |
|
||||||
"autoboot in %d seconds (stop with 'st')...\n", bootdelay |
|
||||||
#define CONFIG_AUTOBOOT_STOP_STR "st" |
|
||||||
#define CONFIG_ZERO_BOOTDELAY_CHECK |
|
||||||
#define CONFIG_RESET_TO_RETRY 1 |
|
||||||
#define CONFIG_BOOT_RETRY_MIN 1 |
|
||||||
#endif /* DEPLOYMENT */ |
|
||||||
#endif /* DEBUG */ |
|
||||||
|
|
||||||
/* pre-boot commands */ |
|
||||||
#define CONFIG_PREBOOT "setenv stdout serial;setenv stdin serial" |
|
||||||
|
|
||||||
#undef CONFIG_BOOTARGS |
|
||||||
#define CONFIG_EXTRA_ENV_SETTINGS \ |
|
||||||
"netdev=eth0\0" \
|
|
||||||
"nfsargs=setenv bootargs console=tty0 console=ttyS0,9600 " \
|
|
||||||
"root=/dev/nfs rw nfsroot=${serverip}:${rootpath}\0" \
|
|
||||||
"ramargs=setenv bootargs console=tty0 root=/dev/ram rw\0" \
|
|
||||||
"addip=setenv bootargs ${bootargs} " \
|
|
||||||
"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
|
|
||||||
":${hostname}:${netdev}:off panic=1\0" \
|
|
||||||
"flash_nfs=run nfsargs addip;" \
|
|
||||||
"bootm ${kernel_addr}\0" \
|
|
||||||
"flash_self=run ramargs addip;" \
|
|
||||||
"bootm ${kernel_addr} ${ramdisk_addr}\0" \
|
|
||||||
"net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0" \
|
|
||||||
"gatewayip=172.16.115.254\0" \
|
|
||||||
"netmask=255.255.255.0\0" \
|
|
||||||
"kernel_addr=ff040000\0" \
|
|
||||||
"ramdisk_addr=ff200000\0" \
|
|
||||||
"ku=era ${kernel_addr} ff1fffff;cp.b 100000 ${kernel_addr} " \
|
|
||||||
"${filesize};md ${kernel_addr};" \
|
|
||||||
"echo kernel updating finished\0" \
|
|
||||||
"uu=protect off 1:0-4;era 1:0-4;cp.b 100000 ff000000 " \
|
|
||||||
"${filesize};md ff000000;" \
|
|
||||||
"echo u-boot updating finished\0" \
|
|
||||||
"eu=protect off 1:6;era 1:6;reset\0" \
|
|
||||||
"lcd=setenv stdout lcd;setenv stdin lcd\0" \
|
|
||||||
"ser=setenv stdout serial;setenv stdin serial\0" \
|
|
||||||
"verify=no" |
|
||||||
|
|
||||||
#define CONFIG_BOOTCOMMAND "run flash_self" |
|
||||||
|
|
||||||
#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ |
|
||||||
#undef CONFIG_SYS_LOADS_BAUD_CHANGE /* don't allow baudrate change */ |
|
||||||
#undef CONFIG_WATCHDOG /* watchdog disabled */ |
|
||||||
#undef CONFIG_STATUS_LED /* disturbs display. Status LED disabled. */ |
|
||||||
|
|
||||||
/*
|
|
||||||
* BOOTP options |
|
||||||
*/ |
|
||||||
#define CONFIG_BOOTP_SUBNETMASK |
|
||||||
#define CONFIG_BOOTP_GATEWAY |
|
||||||
#define CONFIG_BOOTP_HOSTNAME |
|
||||||
#define CONFIG_BOOTP_BOOTPATH |
|
||||||
#define CONFIG_BOOTP_BOOTFILESIZE |
|
||||||
|
|
||||||
|
|
||||||
#if 1 /* Enable this stuff could make image enlarge about 25KB. Mask it if you |
|
||||||
don't want the advanced function */ |
|
||||||
|
|
||||||
|
|
||||||
/*
|
|
||||||
* Command line configuration. |
|
||||||
*/ |
|
||||||
#include <config_cmd_default.h> |
|
||||||
|
|
||||||
#define CONFIG_CMD_ASKENV |
|
||||||
#define CONFIG_CMD_JFFS2 |
|
||||||
#define CONFIG_CMD_PING |
|
||||||
#define CONFIG_CMD_ELF |
|
||||||
#define CONFIG_CMD_REGINFO |
|
||||||
#define CONFIG_CMD_DHCP |
|
||||||
|
|
||||||
#ifdef CONFIG_SPLASH_SCREEN |
|
||||||
#define CONFIG_CMD_BMP |
|
||||||
#endif |
|
||||||
|
|
||||||
|
|
||||||
/* test-only */ |
|
||||||
#define CONFIG_SYS_JFFS2_FIRST_BANK 0 /* use for JFFS2 */ |
|
||||||
#define CONFIG_SYS_JFFS2_NUM_BANKS 1 /* ! second bank contains U-Boot */ |
|
||||||
|
|
||||||
#define CONFIG_NETCONSOLE |
|
||||||
|
|
||||||
#endif /* 1 */ |
|
||||||
|
|
||||||
/*
|
|
||||||
* Miscellaneous configurable options |
|
||||||
*/ |
|
||||||
#define CONFIG_SYS_LONGHELP /* undef to save memory */ |
|
||||||
#define CONFIG_SYS_PROMPT "u-boot>" /* Monitor Command Prompt */ |
|
||||||
|
|
||||||
#if defined(CONFIG_CMD_KGDB) |
|
||||||
#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ |
|
||||||
#else |
|
||||||
#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ |
|
||||||
#endif |
|
||||||
|
|
||||||
#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ |
|
||||||
#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ |
|
||||||
#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ |
|
||||||
|
|
||||||
#define CONFIG_SYS_MEMTEST_START 0x0040000 /* memtest works on */ |
|
||||||
#define CONFIG_SYS_MEMTEST_END 0x00C0000 /* 4 ... 12 MB in DRAM */ |
|
||||||
#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */ |
|
||||||
|
|
||||||
/*
|
|
||||||
* Low Level Configuration Settings |
|
||||||
* (address mappings, register initial values, etc.) |
|
||||||
* You should know what you are doing if you make changes here. |
|
||||||
*/ |
|
||||||
/*-----------------------------------------------------------------------
|
|
||||||
* Internal Memory Mapped Register |
|
||||||
*/ |
|
||||||
#define CONFIG_SYS_IMMR 0xFA200000 |
|
||||||
|
|
||||||
/*-----------------------------------------------------------------------
|
|
||||||
* Definitions for initial stack pointer and data area (in DPRAM) |
|
||||||
*/ |
|
||||||
#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR |
|
||||||
#define CONFIG_SYS_INIT_RAM_SIZE 0x2F00 /* Size of used area in DPRAM */ |
|
||||||
#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) |
|
||||||
#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET |
|
||||||
|
|
||||||
/*-----------------------------------------------------------------------
|
|
||||||
* Start addresses for the final memory configuration |
|
||||||
* (Set up by the startup code) |
|
||||||
* Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 |
|
||||||
*/ |
|
||||||
#define CONFIG_SYS_SDRAM_BASE 0x00000000 |
|
||||||
#define CONFIG_SYS_FLASH_BASE 0xFF000000 |
|
||||||
|
|
||||||
#if defined(DEBUG) || defined(CONFIG_CMD_IDE) |
|
||||||
#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ |
|
||||||
#else |
|
||||||
#define CONFIG_SYS_MONITOR_LEN (128 << 10) /* Reserve 128 kB for Monitor */ |
|
||||||
#endif |
|
||||||
|
|
||||||
#define CONFIG_SYS_MONITOR_BASE 0xFF000000 |
|
||||||
#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ |
|
||||||
|
|
||||||
/*
|
|
||||||
* For booting Linux, the board info and command line data |
|
||||||
* have to be in the first 8 MB of memory, since this is |
|
||||||
* the maximum mapped by the Linux kernel during initialization. |
|
||||||
*/ |
|
||||||
#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ |
|
||||||
|
|
||||||
/*-----------------------------------------------------------------------
|
|
||||||
* FLASH organization |
|
||||||
*/ |
|
||||||
#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */ |
|
||||||
#define CONFIG_SYS_MAX_FLASH_SECT 71 /* max number of sectors on one chip */ |
|
||||||
#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ |
|
||||||
#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ |
|
||||||
|
|
||||||
#ifdef CONFIG_ENV_IS_IN_NVRAM |
|
||||||
#define CONFIG_ENV_ADDR 0xFA000100 |
|
||||||
#define CONFIG_ENV_SIZE 0x1000 |
|
||||||
#else |
|
||||||
#define CONFIG_ENV_IS_IN_FLASH |
|
||||||
#define CONFIG_ENV_OFFSET 0x30000 /* Offset of Environment Sector */ |
|
||||||
#define CONFIG_ENV_SIZE 0x8000 /* Total Size of Environment Sector */ |
|
||||||
#endif /* CONFIG_ENV_IS_IN_NVRAM */ |
|
||||||
|
|
||||||
#define CONFIG_SYS_RESET_ADDRESS ((ulong)((((immap_t *)CONFIG_SYS_IMMR)->im_clkrst.res))) |
|
||||||
|
|
||||||
/*-----------------------------------------------------------------------
|
|
||||||
* Cache Configuration |
|
||||||
*/ |
|
||||||
#define CONFIG_SYS_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */ |
|
||||||
#if defined(CONFIG_CMD_KGDB) |
|
||||||
#define CONFIG_SYS_CACHELINE_SHIFT 4 /* log base 2 of the above value */ |
|
||||||
#endif |
|
||||||
|
|
||||||
/*-----------------------------------------------------------------------
|
|
||||||
* SYPCR - System Protection Control 32-bit 12-35 |
|
||||||
* SYPCR can only be written once after reset! |
|
||||||
*----------------------------------------------------------------------- |
|
||||||
* Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze |
|
||||||
*/ |
|
||||||
#if defined(CONFIG_WATCHDOG) |
|
||||||
#define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \ |
|
||||||
SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP) |
|
||||||
#else |
|
||||||
#define CONFIG_SYS_SYPCR (SYPCR_SWTC | 0x00000600 | SYPCR_BME | SYPCR_SWF | SYPCR_SWP) |
|
||||||
#endif /* We can get SYPCR: 0xFFFF0689. */ |
|
||||||
|
|
||||||
/*-----------------------------------------------------------------------
|
|
||||||
* SIUMCR - SIU Module Configuration 32-bit 12-30 |
|
||||||
*----------------------------------------------------------------------- |
|
||||||
* PCMCIA config., multi-function pin tri-state |
|
||||||
*/ |
|
||||||
#define CONFIG_SYS_SIUMCR (SIUMCR_MLRC10) /* SIUMCR:0x00000800 */ |
|
||||||
|
|
||||||
/*---------------------------------------------------------------------
|
|
||||||
* TBSCR - Time Base Status and Control 16-bit 12-16 |
|
||||||
*--------------------------------------------------------------------- |
|
||||||
* Clear Reference Interrupt Status, Timebase freezing enabled |
|
||||||
*/ |
|
||||||
#define CONFIG_SYS_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF | TBSCR_TBE) |
|
||||||
/* TBSCR: 0x00C3 [SAM] */ |
|
||||||
|
|
||||||
/*-----------------------------------------------------------------------
|
|
||||||
* RTCSC - Real-Time Clock Status and Control Register 16-bit 12-18 |
|
||||||
*----------------------------------------------------------------------- |
|
||||||
* [RTC enabled but not stopped on FRZ] |
|
||||||
*/ |
|
||||||
#define CONFIG_SYS_RTCSC (RTCSC_SEC | RTCSC_ALR | RTCSC_RTE) /* RTCSC:0x00C1 */ |
|
||||||
|
|
||||||
/*-----------------------------------------------------------------------
|
|
||||||
* PISCR - Periodic Interrupt Status and Control 16-bit 12-23 |
|
||||||
*----------------------------------------------------------------------- |
|
||||||
* Clear Periodic Interrupt Status, Interrupt Timer freezing enabled |
|
||||||
* [Periodic timer enabled,Periodic timer interrupt disable. ] |
|
||||||
*/ |
|
||||||
#define CONFIG_SYS_PISCR (PISCR_PS | PISCR_PITF | PISCR_PTE) /* PISCR:0x0083 */ |
|
||||||
|
|
||||||
/*-----------------------------------------------------------------------
|
|
||||||
* PLPRCR - PLL, Low-Power, and Reset Control Register 32-bit 5-7 |
|
||||||
*----------------------------------------------------------------------- |
|
||||||
* Reset PLL lock status sticky bit, timer expired status bit and timer |
|
||||||
* interrupt status bit |
|
||||||
*/ |
|
||||||
/* up to 64 MHz we use a 1:2 clock */ |
|
||||||
#if defined(RPXlite_64MHz) |
|
||||||
#define CONFIG_SYS_PLPRCR ( (7 << PLPRCR_MF_SHIFT) | PLPRCR_TEXPS ) /*PLPRCR: 0x00700000. */ |
|
||||||
#else |
|
||||||
#define CONFIG_SYS_PLPRCR ( (5 << PLPRCR_MF_SHIFT) | PLPRCR_TEXPS ) |
|
||||||
#endif |
|
||||||
|
|
||||||
/*-----------------------------------------------------------------------
|
|
||||||
* SCCR - System Clock and reset Control Register 5-3 |
|
||||||
*----------------------------------------------------------------------- |
|
||||||
* Set clock output, timebase and RTC source and divider, |
|
||||||
* power management and some other internal clocks |
|
||||||
*/ |
|
||||||
#define SCCR_MASK SCCR_EBDF00 |
|
||||||
/* Up to 48MHz system clock, we use 1:1 SYSTEM/BUS ratio */ |
|
||||||
#if defined(RPXlite_64MHz) |
|
||||||
#define CONFIG_SYS_SCCR ( SCCR_TBS | SCCR_EBDF01 ) /* %%%SCCR:0x02020000 */ |
|
||||||
#else |
|
||||||
#define CONFIG_SYS_SCCR ( SCCR_TBS | SCCR_EBDF00 ) /* %%%SCCR:0x02000000 */ |
|
||||||
#endif |
|
||||||
|
|
||||||
/*-----------------------------------------------------------------------
|
|
||||||
* PCMCIA stuff |
|
||||||
*----------------------------------------------------------------------- |
|
||||||
*/ |
|
||||||
#define CONFIG_SYS_PCMCIA_MEM_ADDR (0xE0000000) |
|
||||||
#define CONFIG_SYS_PCMCIA_MEM_SIZE ( 64 << 20 ) |
|
||||||
#define CONFIG_SYS_PCMCIA_DMA_ADDR (0xE4000000) |
|
||||||
#define CONFIG_SYS_PCMCIA_DMA_SIZE ( 64 << 20 ) |
|
||||||
#define CONFIG_SYS_PCMCIA_ATTRB_ADDR (0xE8000000) |
|
||||||
#define CONFIG_SYS_PCMCIA_ATTRB_SIZE ( 64 << 20 ) |
|
||||||
#define CONFIG_SYS_PCMCIA_IO_ADDR (0xEC000000) |
|
||||||
#define CONFIG_SYS_PCMCIA_IO_SIZE ( 64 << 20 ) |
|
||||||
|
|
||||||
/*-----------------------------------------------------------------------
|
|
||||||
* IDE/ATA stuff (Supports IDE harddisk on PCMCIA Adapter) |
|
||||||
*----------------------------------------------------------------------- |
|
||||||
*/ |
|
||||||
#define CONFIG_IDE_PREINIT 1 /* Use preinit IDE hook */ |
|
||||||
#define CONFIG_IDE_8xx_PCCARD 1 /* Use IDE with PC Card Adapter */ |
|
||||||
|
|
||||||
#undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */ |
|
||||||
#undef CONFIG_IDE_LED /* LED for ide not supported */ |
|
||||||
#undef CONFIG_IDE_RESET /* reset for ide not supported */ |
|
||||||
|
|
||||||
#define CONFIG_SYS_IDE_MAXBUS 1 /* max. 1 IDE bus */ |
|
||||||
#define CONFIG_SYS_IDE_MAXDEVICE 1 /* max. 1 drive per IDE bus */ |
|
||||||
|
|
||||||
#define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000 |
|
||||||
#define CONFIG_SYS_ATA_BASE_ADDR CONFIG_SYS_PCMCIA_MEM_ADDR |
|
||||||
|
|
||||||
/* Offset for data I/O */ |
|
||||||
#define CONFIG_SYS_ATA_DATA_OFFSET (CONFIG_SYS_PCMCIA_MEM_SIZE + 0x320) |
|
||||||
|
|
||||||
/* Offset for normal register accesses */ |
|
||||||
#define CONFIG_SYS_ATA_REG_OFFSET (2 * CONFIG_SYS_PCMCIA_MEM_SIZE + 0x320) |
|
||||||
|
|
||||||
/* Offset for alternate registers */ |
|
||||||
#define CONFIG_SYS_ATA_ALT_OFFSET 0x0100 |
|
||||||
|
|
||||||
#define CONFIG_SYS_DER 0 |
|
||||||
|
|
||||||
/*
|
|
||||||
* Init Memory Controller: |
|
||||||
* |
|
||||||
* BR0 and OR0 (FLASH) |
|
||||||
*/ |
|
||||||
#define FLASH_BASE_PRELIM 0xFC000000 /* FLASH base */ |
|
||||||
#define CONFIG_SYS_PRELIM_OR_AM 0xFC000000 /* OR addr mask */ |
|
||||||
|
|
||||||
/* FLASH timing: ACS = 0, TRLX = 0, CSNT = 0, SCY = 8, ETHR = 0, BIH = 1 */ |
|
||||||
#define CONFIG_SYS_OR_TIMING_FLASH (OR_SCY_8_CLK | OR_BI) |
|
||||||
#define CONFIG_SYS_OR0_PRELIM (CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_FLASH) |
|
||||||
#define CONFIG_SYS_BR0_PRELIM ((FLASH_BASE_PRELIM & BR_BA_MSK) | BR_V) |
|
||||||
|
|
||||||
/*
|
|
||||||
* BR1 and OR1 (SDRAM) |
|
||||||
* |
|
||||||
*/ |
|
||||||
#define SDRAM_BASE_PRELIM 0x00000000 /* SDRAM base */ |
|
||||||
#define SDRAM_MAX_SIZE 0x08000000 /* max 128 MB in system */ |
|
||||||
|
|
||||||
/* SDRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care) */ |
|
||||||
#define CONFIG_SYS_OR_TIMING_SDRAM 0x00000E00 |
|
||||||
#define CONFIG_SYS_OR_AM_SDRAM (-(SDRAM_MAX_SIZE & OR_AM_MSK)) |
|
||||||
#define CONFIG_SYS_OR1_PRELIM ( CONFIG_SYS_OR_AM_SDRAM | CONFIG_SYS_OR_TIMING_SDRAM ) |
|
||||||
#define CONFIG_SYS_BR1_PRELIM ((SDRAM_BASE_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V ) |
|
||||||
|
|
||||||
/* RPXlite mem setting */ |
|
||||||
#define CONFIG_SYS_BR3_PRELIM 0xFA400001 /* BCSR */ |
|
||||||
#define CONFIG_SYS_OR3_PRELIM 0xFF7F8900 |
|
||||||
#define CONFIG_SYS_BR4_PRELIM 0xFA000401 /* NVRAM&SRAM */ |
|
||||||
#define CONFIG_SYS_OR4_PRELIM 0xFFFE0040 |
|
||||||
|
|
||||||
/*
|
|
||||||
* Memory Periodic Timer Prescaler |
|
||||||
*/ |
|
||||||
/* periodic timer for refresh */ |
|
||||||
#if defined(RPXlite_64MHz) |
|
||||||
#define CONFIG_SYS_MAMR_PTA 32 |
|
||||||
#else |
|
||||||
#define CONFIG_SYS_MAMR_PTA 20 |
|
||||||
#endif |
|
||||||
|
|
||||||
/*
|
|
||||||
* Refresh clock Prescalar |
|
||||||
*/ |
|
||||||
#define CONFIG_SYS_MPTPR MPTPR_PTP_DIV2 |
|
||||||
|
|
||||||
/*
|
|
||||||
* MAMR settings for SDRAM |
|
||||||
*/ |
|
||||||
|
|
||||||
/* 9 column SDRAM */ |
|
||||||
#define CONFIG_SYS_MAMR_9COL ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \ |
|
||||||
MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10) |
|
||||||
/* CONFIG_SYS_MAMR_9COL:0x20904000 @ 64MHz */ |
|
||||||
|
|
||||||
/*%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% */ |
|
||||||
/* Configuration variable added by yooth. */ |
|
||||||
/*%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% */ |
|
||||||
/*
|
|
||||||
* BCSRx |
|
||||||
* |
|
||||||
* Board Status and Control Registers |
|
||||||
* |
|
||||||
*/ |
|
||||||
#define BCSR0 0xFA400000 |
|
||||||
#define BCSR1 0xFA400001 |
|
||||||
#define BCSR2 0xFA400002 |
|
||||||
#define BCSR3 0xFA400003 |
|
||||||
|
|
||||||
#define BCSR0_ENMONXCVR 0x01 /* Monitor XVCR Control */ |
|
||||||
#define BCSR0_ENNVRAM 0x02 /* CS4# Control */ |
|
||||||
#define BCSR0_LED5 0x04 /* LED5 control 0='on' 1='off' */ |
|
||||||
#define BCSR0_LED4 0x08 /* LED4 control 0='on' 1='off' */ |
|
||||||
#define BCSR0_FULLDPLX 0x10 /* Ethernet XCVR Control */ |
|
||||||
#define BCSR0_COLTEST 0x20 |
|
||||||
#define BCSR0_ETHLPBK 0x40 |
|
||||||
#define BCSR0_ETHEN 0x80 |
|
||||||
|
|
||||||
#define BCSR1_PCVCTL7 0x01 /* PC Slot B Control */ |
|
||||||
#define BCSR1_PCVCTL6 0x02 |
|
||||||
#define BCSR1_PCVCTL5 0x04 |
|
||||||
#define BCSR1_PCVCTL4 0x08 |
|
||||||
#define BCSR1_IPB5SEL 0x10 |
|
||||||
|
|
||||||
#define BCSR1_SMC1CTS 0x40 /* Added by SAM. */ |
|
||||||
#define BCSR1_SMC1TRS 0x80 /* Added by SAM. */ |
|
||||||
|
|
||||||
#define BCSR2_ENRTCIRQ 0x01 /* Added by SAM. */ |
|
||||||
#define BCSR2_ENBRG1 0x04 /* Added by SAM. */ |
|
||||||
|
|
||||||
#define BCSR2_ENPA5HDR 0x08 /* USB Control */ |
|
||||||
#define BCSR2_ENUSBCLK 0x10 |
|
||||||
#define BCSR2_USBPWREN 0x20 |
|
||||||
#define BCSR2_USBSPD 0x40 |
|
||||||
#define BCSR2_USBSUSP 0x80 |
|
||||||
|
|
||||||
#define BCSR3_BWKAPWR 0x01 /* Changed by SAM. Backup battery situation */ |
|
||||||
#define BCSR3_IRQRTC 0x02 /* Changed by SAM. NVRAM Battery */ |
|
||||||
#define BCSR3_RDY_BSY 0x04 /* Changed by SAM. Flash Operation */ |
|
||||||
#define BCSR3_MPLX_LIN 0x08 /* Changed by SAM. Linear or Multiplexed address Mode */ |
|
||||||
|
|
||||||
#define BCSR3_D27 0x10 /* Dip Switch settings */ |
|
||||||
#define BCSR3_D26 0x20 |
|
||||||
#define BCSR3_D25 0x40 |
|
||||||
#define BCSR3_D24 0x80 |
|
||||||
|
|
||||||
/*
|
|
||||||
* Environment setting |
|
||||||
*/ |
|
||||||
#define CONFIG_ETHADDR 00:10:EC:00:37:5B |
|
||||||
#define CONFIG_IPADDR 172.16.115.7 |
|
||||||
#define CONFIG_SERVERIP 172.16.115.6 |
|
||||||
#define CONFIG_ROOTPATH "/workspace/myfilesystem/target/" |
|
||||||
#define CONFIG_BOOTFILE "uImage.rpxusb" |
|
||||||
#define CONFIG_HOSTNAME LITE_H1_DW |
|
||||||
|
|
||||||
#endif /* __CONFIG_H */ |
|
||||||
@ -1,430 +0,0 @@ |
|||||||
/*
|
|
||||||
* (C) Copyright 2003-2010 |
|
||||||
* Wolfgang Denk, DENX Software Engineering, wd@denx.de. |
|
||||||
* |
|
||||||
* SPDX-License-Identifier: GPL-2.0+ |
|
||||||
*/ |
|
||||||
|
|
||||||
/*
|
|
||||||
* board/config.h - configuration options, board specific |
|
||||||
* changes for 16M board |
|
||||||
*/ |
|
||||||
|
|
||||||
#ifndef __CONFIG_H |
|
||||||
#define __CONFIG_H |
|
||||||
|
|
||||||
/*
|
|
||||||
* High Level Configuration Options |
|
||||||
* (easy to change) |
|
||||||
*/ |
|
||||||
|
|
||||||
#undef CONFIG_MPC860 |
|
||||||
#define CONFIG_MPC850 1 /* This is a MPC850 CPU */ |
|
||||||
#define CONFIG_RPXLITE 1 /* QUANTUM is the RPXlite clone */ |
|
||||||
#define CONFIG_RMU 1 /* The QUNATUM is based on our RMU */ |
|
||||||
|
|
||||||
#define CONFIG_SYS_TEXT_BASE 0xfff00000 |
|
||||||
|
|
||||||
#define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */ |
|
||||||
#undef CONFIG_8xx_CONS_SMC2 |
|
||||||
#undef CONFIG_8xx_CONS_NONE |
|
||||||
#define CONFIG_BAUDRATE 9600 /* console baudrate = 9600bps */ |
|
||||||
#if 0 |
|
||||||
#define CONFIG_BOOTDELAY -1 /* autoboot disabled */ |
|
||||||
#else |
|
||||||
#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ |
|
||||||
#endif |
|
||||||
|
|
||||||
/* default developmenmt environment */ |
|
||||||
|
|
||||||
#define CONFIG_ETHADDR 00:0B:17:00:00:00 |
|
||||||
|
|
||||||
#define CONFIG_IPADDR 10.10.69.10 |
|
||||||
#define CONFIG_SERVERIP 10.10.69.49 |
|
||||||
#define CONFIG_NETMASK 255.255.255.0 |
|
||||||
#define CONFIG_HOSTNAME QUANTUM |
|
||||||
#define CONFIG_ROOTPATH "/opt/eldk/pcc_8xx" |
|
||||||
|
|
||||||
#define CONFIG_BOOTARGS "root=/dev/ram rw" |
|
||||||
|
|
||||||
#define CONFIG_BOOTCOMMAND "bootm ff000000" |
|
||||||
|
|
||||||
#define CONFIG_EXTRA_ENV_SETTINGS \ |
|
||||||
"serial#=12345\0" \
|
|
||||||
"nfsargs=setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath}\0" \
|
|
||||||
"ramargs=setenv bootargs root=/dev/ram rw\0" \
|
|
||||||
"addip=setenv bootargs ${bootargs} ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off\0" |
|
||||||
|
|
||||||
/*
|
|
||||||
* Select the more full-featured memory test (Barr embedded systems) |
|
||||||
*/ |
|
||||||
#define CONFIG_SYS_ALT_MEMTEST |
|
||||||
|
|
||||||
#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ |
|
||||||
#undef CONFIG_SYS_LOADS_BAUD_CHANGE /* don't allow baudrate change */ |
|
||||||
|
|
||||||
|
|
||||||
/* M48T02 Paralled access timekeeper with same interface as the M48T35A*/ |
|
||||||
#define CONFIG_RTC_M48T35A 1 |
|
||||||
|
|
||||||
#if 0 |
|
||||||
#define CONFIG_WATCHDOG 1 /* watchdog enabled */ |
|
||||||
#else |
|
||||||
#undef CONFIG_WATCHDOG |
|
||||||
#endif |
|
||||||
|
|
||||||
/* NVRAM and RTC */ |
|
||||||
#define CONFIG_SYS_NVRAM_BASE_ADDR 0xFA000000 |
|
||||||
#define CONFIG_SYS_NVRAM_SIZE 2048 |
|
||||||
|
|
||||||
|
|
||||||
/*
|
|
||||||
* Command line configuration. |
|
||||||
*/ |
|
||||||
#include <config_cmd_default.h> |
|
||||||
|
|
||||||
#define CONFIG_CMD_DATE |
|
||||||
#define CONFIG_CMD_DHCP |
|
||||||
#define CONFIG_CMD_NFS |
|
||||||
#define CONFIG_CMD_PING |
|
||||||
#define CONFIG_CMD_REGINFO |
|
||||||
#define CONFIG_CMD_SNTP |
|
||||||
|
|
||||||
|
|
||||||
/*
|
|
||||||
* BOOTP options |
|
||||||
*/ |
|
||||||
#define CONFIG_BOOTP_SUBNETMASK |
|
||||||
#define CONFIG_BOOTP_GATEWAY |
|
||||||
#define CONFIG_BOOTP_HOSTNAME |
|
||||||
#define CONFIG_BOOTP_BOOTPATH |
|
||||||
#define CONFIG_BOOTP_BOOTFILESIZE |
|
||||||
|
|
||||||
|
|
||||||
#define CONFIG_AUTOBOOT_KEYED /* Enable password protection */ |
|
||||||
#define CONFIG_AUTOBOOT_PROMPT \ |
|
||||||
"\nEnter password - autoboot in %d sec...\n", bootdelay |
|
||||||
#define CONFIG_AUTOBOOT_DELAY_STR "system" |
|
||||||
/*
|
|
||||||
* Miscellaneous configurable options |
|
||||||
*/ |
|
||||||
#define CONFIG_SYS_LONGHELP /* undef to save memory */ |
|
||||||
#if defined(CONFIG_CMD_KGDB) |
|
||||||
#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ |
|
||||||
#else |
|
||||||
#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ |
|
||||||
#endif |
|
||||||
#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ |
|
||||||
#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ |
|
||||||
#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ |
|
||||||
|
|
||||||
#define CONFIG_SYS_MEMTEST_START 0x00040000 /* memtest works on */ |
|
||||||
#define CONFIG_SYS_MEMTEST_END 0x01f00000 /* 256K ... 15 MB in DRAM */ |
|
||||||
|
|
||||||
#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */ |
|
||||||
|
|
||||||
/*
|
|
||||||
* Low Level Configuration Settings |
|
||||||
* (address mappings, register initial values, etc.) |
|
||||||
* You should know what you are doing if you make changes here. |
|
||||||
*/ |
|
||||||
/*-----------------------------------------------------------------------
|
|
||||||
* Internal Memory Mapped Register |
|
||||||
*/ |
|
||||||
#define CONFIG_SYS_IMMR 0xFA200000 |
|
||||||
|
|
||||||
/*-----------------------------------------------------------------------
|
|
||||||
* Definitions for initial stack pointer and data area (in DPRAM) |
|
||||||
*/ |
|
||||||
#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR |
|
||||||
#define CONFIG_SYS_INIT_RAM_SIZE 0x2F00 /* Size of used area in DPRAM */ |
|
||||||
#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) |
|
||||||
#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET |
|
||||||
|
|
||||||
/*-----------------------------------------------------------------------
|
|
||||||
* Start addresses for the final memory configuration |
|
||||||
* (Set up by the startup code) |
|
||||||
* Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 |
|
||||||
*/ |
|
||||||
#define CONFIG_SYS_SDRAM_BASE 0x00000000 |
|
||||||
#define CONFIG_SYS_FLASH_BASE 0xFF000000 |
|
||||||
|
|
||||||
#if 1 |
|
||||||
#define CONFIG_FLASH_CFI_DRIVER |
|
||||||
#else |
|
||||||
#undef CONFIG_FLASH_CFI_DRIVER |
|
||||||
#endif |
|
||||||
|
|
||||||
|
|
||||||
#ifdef CONFIG_FLASH_CFI_DRIVER |
|
||||||
#define CONFIG_SYS_FLASH_CFI 1 |
|
||||||
#undef CONFIG_SYS_FLASH_USE_BUFFER_WRITE |
|
||||||
#define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE} |
|
||||||
#endif |
|
||||||
|
|
||||||
/*%%% #define CONFIG_SYS_FLASH_BASE 0xFFF00000 */ |
|
||||||
#if defined(DEBUG) || defined(CONFIG_CMD_IDE) |
|
||||||
#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ |
|
||||||
#else |
|
||||||
#define CONFIG_SYS_MONITOR_LEN (128 << 10) /* Reserve 128 kB for Monitor */ |
|
||||||
#endif |
|
||||||
#define CONFIG_SYS_MONITOR_BASE 0xFFF00000 |
|
||||||
/*%%% #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE */ |
|
||||||
#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ |
|
||||||
|
|
||||||
/*
|
|
||||||
* For booting Linux, the board info and command line data |
|
||||||
* have to be in the first 8 MB of memory, since this is |
|
||||||
* the maximum mapped by the Linux kernel during initialization. |
|
||||||
*/ |
|
||||||
#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ |
|
||||||
|
|
||||||
/*-----------------------------------------------------------------------
|
|
||||||
* FLASH organization |
|
||||||
*/ |
|
||||||
#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */ |
|
||||||
#define CONFIG_SYS_MAX_FLASH_SECT 512 /* max number of sectors on one chip */ |
|
||||||
|
|
||||||
#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ |
|
||||||
#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ |
|
||||||
|
|
||||||
#define CONFIG_ENV_IS_IN_FLASH 1 |
|
||||||
#define CONFIG_ENV_OFFSET 0x00040000 /* Offset of Environment Sector absolute address 0xfff40000*/ |
|
||||||
#define CONFIG_ENV_SECT_SIZE 0x40000 /* Total Size of Environment Sector */ |
|
||||||
#define CONFIG_ENV_SIZE CONFIG_ENV_SECT_SIZE |
|
||||||
#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + CONFIG_ENV_OFFSET) |
|
||||||
|
|
||||||
/* Address and size of Redundant Environment Sector */ |
|
||||||
#define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET+CONFIG_ENV_SIZE) |
|
||||||
#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE) |
|
||||||
|
|
||||||
/* FPGA */ |
|
||||||
#define CONFIG_MISC_INIT_R |
|
||||||
#define CONFIG_SYS_FPGA_SPARTAN2 |
|
||||||
#define CONFIG_SYS_FPGA_PROG_FEEDBACK |
|
||||||
|
|
||||||
|
|
||||||
/*-----------------------------------------------------------------------
|
|
||||||
* Reset address |
|
||||||
*/ |
|
||||||
#define CONFIG_SYS_RESET_ADDRESS ((ulong)((((immap_t *)CONFIG_SYS_IMMR)->im_clkrst.res))) |
|
||||||
|
|
||||||
/*-----------------------------------------------------------------------
|
|
||||||
* Cache Configuration |
|
||||||
*/ |
|
||||||
#define CONFIG_SYS_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */ |
|
||||||
#if defined(CONFIG_CMD_KGDB) |
|
||||||
#define CONFIG_SYS_CACHELINE_SHIFT 4 /* log base 2 of the above value */ |
|
||||||
#endif |
|
||||||
|
|
||||||
/*-----------------------------------------------------------------------
|
|
||||||
* SYPCR - System Protection Control 11-9 |
|
||||||
* SYPCR can only be written once after reset! |
|
||||||
*----------------------------------------------------------------------- |
|
||||||
* Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze |
|
||||||
*/ |
|
||||||
#if defined(CONFIG_WATCHDOG) |
|
||||||
#define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \ |
|
||||||
SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP) |
|
||||||
#else |
|
||||||
#define CONFIG_SYS_SYPCR (SYPCR_SWTC | 0x00000600 | SYPCR_BME | SYPCR_SWF | SYPCR_SWP) |
|
||||||
#endif |
|
||||||
|
|
||||||
/*-----------------------------------------------------------------------
|
|
||||||
* SIUMCR - SIU Module Configuration 11-6 |
|
||||||
*----------------------------------------------------------------------- |
|
||||||
* PCMCIA config., multi-function pin tri-state |
|
||||||
*/ |
|
||||||
#define CONFIG_SYS_SIUMCR (SIUMCR_MLRC10) |
|
||||||
|
|
||||||
/*-----------------------------------------------------------------------
|
|
||||||
* TBSCR - Time Base Status and Control 11-26 |
|
||||||
*----------------------------------------------------------------------- |
|
||||||
* Clear Reference Interrupt Status, Timebase freezing enabled |
|
||||||
*/ |
|
||||||
#define CONFIG_SYS_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF | TBSCR_TBE) |
|
||||||
|
|
||||||
/*-----------------------------------------------------------------------
|
|
||||||
* RTCSC - Real-Time Clock Status and Control Register 11-27 |
|
||||||
*----------------------------------------------------------------------- |
|
||||||
*/ |
|
||||||
/*%%%#define CONFIG_SYS_RTCSC (RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE) */ |
|
||||||
#define CONFIG_SYS_RTCSC (RTCSC_SEC | RTCSC_RTE) |
|
||||||
|
|
||||||
/*-----------------------------------------------------------------------
|
|
||||||
* PISCR - Periodic Interrupt Status and Control 11-31 |
|
||||||
*----------------------------------------------------------------------- |
|
||||||
* Clear Periodic Interrupt Status, Interrupt Timer freezing enabled |
|
||||||
*/ |
|
||||||
#define CONFIG_SYS_PISCR (PISCR_PS | PISCR_PITF) |
|
||||||
|
|
||||||
/*-----------------------------------------------------------------------
|
|
||||||
* PLPRCR - PLL, Low-Power, and Reset Control Register 15-30 |
|
||||||
*----------------------------------------------------------------------- |
|
||||||
* Reset PLL lock status sticky bit, timer expired status bit and timer |
|
||||||
* interrupt status bit |
|
||||||
* |
|
||||||
* If this is a 80 MHz CPU, set PLL multiplication factor to 5 (5*16=80)! |
|
||||||
*/ |
|
||||||
/* up to 50 MHz we use a 1:1 clock */ |
|
||||||
#define CONFIG_SYS_PLPRCR ( (5 << PLPRCR_MF_SHIFT) | PLPRCR_TEXPS ) |
|
||||||
|
|
||||||
/*-----------------------------------------------------------------------
|
|
||||||
* SCCR - System Clock and reset Control Register 15-27 |
|
||||||
*----------------------------------------------------------------------- |
|
||||||
* Set clock output, timebase and RTC source and divider, |
|
||||||
* power management and some other internal clocks |
|
||||||
*/ |
|
||||||
#define SCCR_MASK SCCR_EBDF00 |
|
||||||
/* up to 50 MHz we use a 1:1 clock */ |
|
||||||
#define CONFIG_SYS_SCCR (SCCR_COM00 | SCCR_TBS) |
|
||||||
|
|
||||||
/*-----------------------------------------------------------------------
|
|
||||||
* PCMCIA stuff |
|
||||||
*----------------------------------------------------------------------- |
|
||||||
* |
|
||||||
*/ |
|
||||||
#define CONFIG_SYS_PCMCIA_MEM_ADDR (0xE0000000) |
|
||||||
#define CONFIG_SYS_PCMCIA_MEM_SIZE ( 64 << 20 ) |
|
||||||
#define CONFIG_SYS_PCMCIA_DMA_ADDR (0xE4000000) |
|
||||||
#define CONFIG_SYS_PCMCIA_DMA_SIZE ( 64 << 20 ) |
|
||||||
#define CONFIG_SYS_PCMCIA_ATTRB_ADDR (0xE8000000) |
|
||||||
#define CONFIG_SYS_PCMCIA_ATTRB_SIZE ( 64 << 20 ) |
|
||||||
#define CONFIG_SYS_PCMCIA_IO_ADDR (0xEC000000) |
|
||||||
#define CONFIG_SYS_PCMCIA_IO_SIZE ( 64 << 20 ) |
|
||||||
|
|
||||||
/*-----------------------------------------------------------------------
|
|
||||||
* IDE/ATA stuff (Supports IDE harddisk on PCMCIA Adapter) |
|
||||||
*----------------------------------------------------------------------- |
|
||||||
*/ |
|
||||||
|
|
||||||
#define CONFIG_IDE_PREINIT 1 /* Use preinit IDE hook */ |
|
||||||
#define CONFIG_IDE_8xx_PCCARD 1 /* Use IDE with PC Card Adapter */ |
|
||||||
|
|
||||||
#undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */ |
|
||||||
#undef CONFIG_IDE_LED /* LED for ide not supported */ |
|
||||||
#undef CONFIG_IDE_RESET /* reset for ide not supported */ |
|
||||||
|
|
||||||
#define CONFIG_SYS_IDE_MAXBUS 1 /* max. 1 IDE bus */ |
|
||||||
#define CONFIG_SYS_IDE_MAXDEVICE 1 /* max. 1 drive per IDE bus */ |
|
||||||
|
|
||||||
#define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000 |
|
||||||
|
|
||||||
#define CONFIG_SYS_ATA_BASE_ADDR CONFIG_SYS_PCMCIA_MEM_ADDR |
|
||||||
|
|
||||||
/* Offset for data I/O */ |
|
||||||
#define CONFIG_SYS_ATA_DATA_OFFSET (CONFIG_SYS_PCMCIA_MEM_SIZE + 0x320) |
|
||||||
|
|
||||||
/* Offset for normal register accesses */ |
|
||||||
#define CONFIG_SYS_ATA_REG_OFFSET (2 * CONFIG_SYS_PCMCIA_MEM_SIZE + 0x320) |
|
||||||
|
|
||||||
/* Offset for alternate registers */ |
|
||||||
#define CONFIG_SYS_ATA_ALT_OFFSET 0x0100 |
|
||||||
|
|
||||||
/*-----------------------------------------------------------------------
|
|
||||||
* |
|
||||||
*----------------------------------------------------------------------- |
|
||||||
* |
|
||||||
*/ |
|
||||||
/*#define CONFIG_SYS_DER 0x2002000F*/ |
|
||||||
#define CONFIG_SYS_DER 0 |
|
||||||
|
|
||||||
/*
|
|
||||||
* Init Memory Controller: |
|
||||||
* |
|
||||||
* BR0 and OR0 (FLASH) |
|
||||||
*/ |
|
||||||
|
|
||||||
#define FLASH_BASE_PRELIM 0xFE000000 /* FLASH base */ |
|
||||||
#define CONFIG_SYS_PRELIM_OR_AM 0xFE000000 /* OR addr mask */ |
|
||||||
|
|
||||||
/* FLASH timing: ACS = 0, TRLX = 0, CSNT = 0, SCY = 4, ETHR = 0, BIH = 1 */ |
|
||||||
#define CONFIG_SYS_OR_TIMING_FLASH (OR_SCY_4_CLK | OR_BI) |
|
||||||
|
|
||||||
#define CONFIG_SYS_OR0_PRELIM (CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_FLASH) |
|
||||||
#define CONFIG_SYS_BR0_PRELIM ((FLASH_BASE_PRELIM & BR_BA_MSK) | BR_V) |
|
||||||
|
|
||||||
/*
|
|
||||||
* BR1 and OR1 (SDRAM) |
|
||||||
* |
|
||||||
*/ |
|
||||||
#define SDRAM_BASE_PRELIM 0x00000000 /* SDRAM base */ |
|
||||||
#define SDRAM_MAX_SIZE 0x08000000 /* max 128 MB */ |
|
||||||
|
|
||||||
/* SDRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care) */ |
|
||||||
#define CONFIG_SYS_OR_TIMING_SDRAM 0x00000E00 |
|
||||||
|
|
||||||
#define CONFIG_SYS_OR1_PRELIM (0xF0000000 | CONFIG_SYS_OR_TIMING_SDRAM ) /* map 256 MB */ |
|
||||||
#define CONFIG_SYS_BR1_PRELIM ((SDRAM_BASE_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V ) |
|
||||||
|
|
||||||
/* RPXLITE mem setting */ |
|
||||||
#define CONFIG_SYS_BR3_PRELIM 0xFA400001 /* FPGA */ |
|
||||||
#define CONFIG_SYS_OR3_PRELIM 0xFFFF8910 |
|
||||||
|
|
||||||
#define CONFIG_SYS_BR4_PRELIM 0xFA000401 /* NVRAM&SRAM */ |
|
||||||
#define CONFIG_SYS_OR4_PRELIM 0xFFFE0970 |
|
||||||
|
|
||||||
/*
|
|
||||||
* Memory Periodic Timer Prescaler |
|
||||||
*/ |
|
||||||
|
|
||||||
/* periodic timer for refresh */ |
|
||||||
#define CONFIG_SYS_MAMR_PTA 20 |
|
||||||
|
|
||||||
/*
|
|
||||||
* Refresh clock Prescalar |
|
||||||
*/ |
|
||||||
#define CONFIG_SYS_MPTPR MPTPR_PTP_DIV2 |
|
||||||
|
|
||||||
/*
|
|
||||||
* MAMR settings for SDRAM |
|
||||||
*/ |
|
||||||
|
|
||||||
/* 9 column SDRAM */ |
|
||||||
#define CONFIG_SYS_MAMR_9COL ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \ |
|
||||||
MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 | \
|
|
||||||
MAMR_RLFA_16X | MAMR_WLFA_16X | MAMR_TLFA_16X) |
|
||||||
|
|
||||||
/*
|
|
||||||
* BCSRx |
|
||||||
* |
|
||||||
* Board Status and Control Registers |
|
||||||
* |
|
||||||
*/ |
|
||||||
|
|
||||||
#define BCSR0 0xFA400000 |
|
||||||
#define BCSR1 0xFA400001 |
|
||||||
#define BCSR2 0xFA400002 |
|
||||||
#define BCSR3 0xFA400003 |
|
||||||
|
|
||||||
#define BCSR0_ENMONXCVR 0x01 /* Monitor XVCR Control */ |
|
||||||
#define BCSR0_ENNVRAM 0x02 /* CS4# Control */ |
|
||||||
#define BCSR0_LED5 0x04 /* LED5 control 0='on' 1='off' */ |
|
||||||
#define BCSR0_LED4 0x08 /* LED4 control 0='on' 1='off' */ |
|
||||||
#define BCSR0_FULLDPLX 0x10 /* Ethernet XCVR Control */ |
|
||||||
#define BCSR0_COLTEST 0x20 |
|
||||||
#define BCSR0_ETHLPBK 0x40 |
|
||||||
#define BCSR0_ETHEN 0x80 |
|
||||||
|
|
||||||
#define BCSR1_PCVCTL7 0x01 /* PC Slot B Control */ |
|
||||||
#define BCSR1_PCVCTL6 0x02 |
|
||||||
#define BCSR1_PCVCTL5 0x04 |
|
||||||
#define BCSR1_PCVCTL4 0x08 |
|
||||||
#define BCSR1_IPB5SEL 0x10 |
|
||||||
|
|
||||||
#define BCSR2_ENPA5HDR 0x08 /* USB Control */ |
|
||||||
#define BCSR2_ENUSBCLK 0x10 |
|
||||||
#define BCSR2_USBPWREN 0x20 |
|
||||||
#define BCSR2_USBSPD 0x40 |
|
||||||
#define BCSR2_USBSUSP 0x80 |
|
||||||
|
|
||||||
#define BCSR3_BWRTC 0x01 /* Real Time Clock Battery */ |
|
||||||
#define BCSR3_BWNVR 0x02 /* NVRAM Battery */ |
|
||||||
#define BCSR3_RDY_BSY 0x04 /* Flash Operation */ |
|
||||||
#define BCSR3_RPXL 0x08 /* Reserved (reads back '1') */ |
|
||||||
#define BCSR3_D27 0x10 /* Dip Switch settings */ |
|
||||||
#define BCSR3_D26 0x20 |
|
||||||
#define BCSR3_D25 0x40 |
|
||||||
#define BCSR3_D24 0x80 |
|
||||||
|
|
||||||
#endif /* __CONFIG_H */ |
|
||||||
Loading…
Reference in new issue