Tom Rini
7 years ago
commit
0675f992db
@ -0,0 +1,95 @@ |
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/*
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* Copyright 2016 Freescale Semiconductor, Inc. |
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* Hou Zhiqiang <Zhiqiang.Hou@freescale.com> |
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* |
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* SPDX-License-Identifier: GPL-2.0+ |
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*/ |
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|
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#include <common.h> |
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#include <errno.h> |
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#include <i2c.h> |
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#include <power/pmic.h> |
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#include <power/mc34vr500_pmic.h> |
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static uint8_t swxvolt_addr[4] = { MC34VR500_SW1VOLT, |
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MC34VR500_SW2VOLT, |
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MC34VR500_SW3VOLT, |
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MC34VR500_SW4VOLT }; |
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static uint8_t swx_set_point_base[4] = { 13, 9, 9, 9 }; |
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int mc34vr500_get_sw_volt(uint8_t sw) |
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{ |
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struct pmic *p; |
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u32 swxvolt; |
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uint8_t spb; |
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int sw_volt; |
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int ret; |
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debug("%s: Get SW%u volt from swxvolt_addr = 0x%x\n", |
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__func__, sw + 1, swxvolt_addr[sw]); |
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if (sw > SW4) { |
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printf("%s: Unsupported SW(sw%d)\n", __func__, sw + 1); |
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return -EINVAL; |
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} |
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p = pmic_get("MC34VR500"); |
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if (!p) { |
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printf("%s: Did NOT find PMIC MC34VR500\n", __func__); |
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return -ENODEV; |
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} |
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ret = pmic_probe(p); |
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if (ret) |
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return ret; |
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ret = pmic_reg_read(p, swxvolt_addr[sw], &swxvolt); |
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if (ret) { |
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printf("%s: Failed to get SW%u volt\n", __func__, sw + 1); |
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return ret; |
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} |
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debug("%s: SW%d step point swxvolt = %u\n", __func__, sw + 1, swxvolt); |
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spb = swx_set_point_base[sw]; |
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/* The base of SW volt is 625mV and increase by step 25mV */ |
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sw_volt = 625 + (swxvolt - spb) * 25; |
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debug("%s: SW%u volt = %dmV\n", __func__, sw + 1, sw_volt); |
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return sw_volt; |
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} |
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int mc34vr500_set_sw_volt(uint8_t sw, int sw_volt) |
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{ |
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struct pmic *p; |
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u32 swxvolt; |
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uint8_t spb; |
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int ret; |
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debug("%s: Set SW%u volt to %dmV\n", __func__, sw + 1, sw_volt); |
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/* The least SW volt is 625mV, and only 4 SW outputs */ |
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if (sw > SW4 || sw_volt < 625) |
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return -EINVAL; |
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p = pmic_get("MC34VR500"); |
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if (!p) { |
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printf("%s: Did NOT find PMIC MC34VR500\n", __func__); |
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return -ENODEV; |
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} |
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ret = pmic_probe(p); |
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if (ret) |
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return ret; |
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spb = swx_set_point_base[sw]; |
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/* The base of SW volt is 625mV and increase by step 25mV */ |
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swxvolt = (sw_volt - 625) / 25 + spb; |
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debug("%s: SW%d step point swxvolt = %u\n", __func__, sw + 1, swxvolt); |
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if (swxvolt > 63) |
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return -EINVAL; |
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ret = pmic_reg_write(p, swxvolt_addr[sw], swxvolt); |
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if (ret) |
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return ret; |
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return 0; |
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} |
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File diff suppressed because it is too large
Load Diff
@ -0,0 +1,140 @@ |
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/*
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* Copyright 2014-2015 Freescale Semiconductor, Inc. |
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* Layerscape PCIe driver |
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* |
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* SPDX-License-Identifier: GPL-2.0+ |
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*/ |
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#ifndef _PCIE_LAYERSCAPE_H_ |
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#define _PCIE_LAYERSCAPE_H_ |
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#include <pci.h> |
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#include <dm.h> |
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#ifndef CONFIG_SYS_PCI_MEMORY_BUS |
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#define CONFIG_SYS_PCI_MEMORY_BUS CONFIG_SYS_SDRAM_BASE |
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#endif |
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#ifndef CONFIG_SYS_PCI_MEMORY_PHYS |
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#define CONFIG_SYS_PCI_MEMORY_PHYS CONFIG_SYS_SDRAM_BASE |
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#endif |
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#ifndef CONFIG_SYS_PCI_MEMORY_SIZE |
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#define CONFIG_SYS_PCI_MEMORY_SIZE (2 * 1024 * 1024 * 1024UL) /* 2G */ |
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#endif |
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#ifndef CONFIG_SYS_PCI_EP_MEMORY_BASE |
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#define CONFIG_SYS_PCI_EP_MEMORY_BASE CONFIG_SYS_LOAD_ADDR |
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#endif |
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|
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/* iATU registers */ |
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#define PCIE_ATU_VIEWPORT 0x900 |
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#define PCIE_ATU_REGION_INBOUND (0x1 << 31) |
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#define PCIE_ATU_REGION_OUTBOUND (0x0 << 31) |
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#define PCIE_ATU_REGION_INDEX0 (0x0 << 0) |
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#define PCIE_ATU_REGION_INDEX1 (0x1 << 0) |
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#define PCIE_ATU_REGION_INDEX2 (0x2 << 0) |
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#define PCIE_ATU_REGION_INDEX3 (0x3 << 0) |
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#define PCIE_ATU_REGION_NUM 6 |
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#define PCIE_ATU_CR1 0x904 |
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#define PCIE_ATU_TYPE_MEM (0x0 << 0) |
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#define PCIE_ATU_TYPE_IO (0x2 << 0) |
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#define PCIE_ATU_TYPE_CFG0 (0x4 << 0) |
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#define PCIE_ATU_TYPE_CFG1 (0x5 << 0) |
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#define PCIE_ATU_CR2 0x908 |
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#define PCIE_ATU_ENABLE (0x1 << 31) |
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#define PCIE_ATU_BAR_MODE_ENABLE (0x1 << 30) |
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#define PCIE_ATU_BAR_NUM(bar) ((bar) << 8) |
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#define PCIE_ATU_LOWER_BASE 0x90C |
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#define PCIE_ATU_UPPER_BASE 0x910 |
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#define PCIE_ATU_LIMIT 0x914 |
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#define PCIE_ATU_LOWER_TARGET 0x918 |
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#define PCIE_ATU_BUS(x) (((x) & 0xff) << 24) |
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#define PCIE_ATU_DEV(x) (((x) & 0x1f) << 19) |
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#define PCIE_ATU_FUNC(x) (((x) & 0x7) << 16) |
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#define PCIE_ATU_UPPER_TARGET 0x91C |
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/* DBI registers */ |
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#define PCIE_SRIOV 0x178 |
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#define PCIE_STRFMR1 0x71c /* Symbol Timer & Filter Mask Register1 */ |
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#define PCIE_DBI_RO_WR_EN 0x8bc |
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#define PCIE_LINK_CAP 0x7c |
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#define PCIE_LINK_SPEED_MASK 0xf |
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#define PCIE_LINK_WIDTH_MASK 0x3f0 |
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#define PCIE_LINK_STA 0x82 |
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#define LTSSM_STATE_MASK 0x3f |
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#define LTSSM_PCIE_L0 0x11 /* L0 state */ |
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#define PCIE_DBI_SIZE 0x100000 /* 1M */ |
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#define PCIE_LCTRL0_CFG2_ENABLE (1 << 31) |
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#define PCIE_LCTRL0_VF(vf) ((vf) << 22) |
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#define PCIE_LCTRL0_PF(pf) ((pf) << 16) |
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#define PCIE_LCTRL0_VF_ACTIVE (1 << 21) |
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#define PCIE_LCTRL0_VAL(pf, vf) (PCIE_LCTRL0_PF(pf) | \ |
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PCIE_LCTRL0_VF(vf) | \
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((vf) == 0 ? 0 : PCIE_LCTRL0_VF_ACTIVE) | \
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PCIE_LCTRL0_CFG2_ENABLE) |
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#define PCIE_NO_SRIOV_BAR_BASE 0x1000 |
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#define PCIE_PF_NUM 2 |
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#define PCIE_VF_NUM 64 |
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#define PCIE_BAR0_SIZE (4 * 1024) /* 4K */ |
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#define PCIE_BAR1_SIZE (8 * 1024) /* 8K for MSIX */ |
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#define PCIE_BAR2_SIZE (4 * 1024) /* 4K */ |
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#define PCIE_BAR4_SIZE (1 * 1024 * 1024) /* 1M */ |
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/* LUT registers */ |
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#define PCIE_LUT_UDR(n) (0x800 + (n) * 8) |
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#define PCIE_LUT_LDR(n) (0x804 + (n) * 8) |
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#define PCIE_LUT_ENABLE (1 << 31) |
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#define PCIE_LUT_ENTRY_COUNT 32 |
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/* PF Controll registers */ |
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#define PCIE_PF_VF_CTRL 0x7F8 |
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#define PCIE_PF_DBG 0x7FC |
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#define PCIE_SRDS_PRTCL(idx) (PCIE1 + (idx)) |
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#define PCIE_SYS_BASE_ADDR 0x3400000 |
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#define PCIE_CCSR_SIZE 0x0100000 |
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/* CS2 */ |
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#define PCIE_CS2_OFFSET 0x1000 /* For PCIe without SR-IOV */ |
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#define SVR_LS102XA 0 |
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#define SVR_VAR_PER_SHIFT 8 |
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#define SVR_LS102XA_MASK 0x700 |
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/* LS1021a PCIE space */ |
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#define LS1021_PCIE_SPACE_OFFSET 0x4000000000ULL |
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#define LS1021_PCIE_SPACE_SIZE 0x0800000000ULL |
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/* LS1021a PEX1/2 Misc Ports Status Register */ |
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#define LS1021_PEXMSCPORTSR(pex_idx) (0x94 + (pex_idx) * 4) |
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#define LS1021_LTSSM_STATE_SHIFT 20 |
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struct ls_pcie { |
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int idx; |
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struct list_head list; |
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struct udevice *bus; |
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struct fdt_resource dbi_res; |
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struct fdt_resource lut_res; |
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struct fdt_resource ctrl_res; |
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struct fdt_resource cfg_res; |
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void __iomem *dbi; |
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void __iomem *lut; |
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void __iomem *ctrl; |
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void __iomem *cfg0; |
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void __iomem *cfg1; |
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bool big_endian; |
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bool enabled; |
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int next_lut_index; |
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struct pci_controller hose; |
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}; |
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extern struct list_head ls_pcie_list; |
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#endif /* _PCIE_LAYERSCAPE_H_ */ |
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@ -0,0 +1,187 @@ |
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/*
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* Copyright 2014-2015 Freescale Semiconductor, Inc. |
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* Layerscape PCIe driver |
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* |
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* SPDX-License-Identifier: GPL-2.0+ |
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*/ |
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#include <common.h> |
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#include <pci.h> |
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#include <asm/arch/fsl_serdes.h> |
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#include <asm/io.h> |
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#include <errno.h> |
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#ifdef CONFIG_OF_BOARD_SETUP |
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#include <libfdt.h> |
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#include <fdt_support.h> |
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#include "pcie_layerscape.h" |
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#ifdef CONFIG_FSL_LSCH3 |
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/*
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* Return next available LUT index. |
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*/ |
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static int ls_pcie_next_lut_index(struct ls_pcie *pcie) |
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{ |
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if (pcie->next_lut_index < PCIE_LUT_ENTRY_COUNT) |
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return pcie->next_lut_index++; |
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else |
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return -ENOSPC; /* LUT is full */ |
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} |
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/* returns the next available streamid for pcie, -errno if failed */ |
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static int ls_pcie_next_streamid(void) |
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{ |
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static int next_stream_id = FSL_PEX_STREAM_ID_START; |
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if (next_stream_id > FSL_PEX_STREAM_ID_END) |
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return -EINVAL; |
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return next_stream_id++; |
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} |
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static void lut_writel(struct ls_pcie *pcie, unsigned int value, |
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unsigned int offset) |
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{ |
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if (pcie->big_endian) |
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out_be32(pcie->lut + offset, value); |
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else |
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out_le32(pcie->lut + offset, value); |
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} |
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|
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/*
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* Program a single LUT entry |
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*/ |
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static void ls_pcie_lut_set_mapping(struct ls_pcie *pcie, int index, u32 devid, |
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u32 streamid) |
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{ |
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/* leave mask as all zeroes, want to match all bits */ |
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lut_writel(pcie, devid << 16, PCIE_LUT_UDR(index)); |
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lut_writel(pcie, streamid | PCIE_LUT_ENABLE, PCIE_LUT_LDR(index)); |
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} |
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|
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/*
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* An msi-map is a property to be added to the pci controller |
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* node. It is a table, where each entry consists of 4 fields |
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* e.g.: |
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* |
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* msi-map = <[devid] [phandle-to-msi-ctrl] [stream-id] [count] |
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* [devid] [phandle-to-msi-ctrl] [stream-id] [count]>; |
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*/ |
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static void fdt_pcie_set_msi_map_entry(void *blob, struct ls_pcie *pcie, |
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u32 devid, u32 streamid) |
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{ |
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u32 *prop; |
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u32 phandle; |
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int nodeoffset; |
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|
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/* find pci controller node */ |
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nodeoffset = fdt_node_offset_by_compat_reg(blob, "fsl,ls-pcie", |
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pcie->dbi_res.start); |
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if (nodeoffset < 0) { |
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#ifdef CONFIG_FSL_PCIE_COMPAT /* Compatible with older version of dts node */ |
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nodeoffset = fdt_node_offset_by_compat_reg(blob, |
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CONFIG_FSL_PCIE_COMPAT, pcie->dbi_res.start); |
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if (nodeoffset < 0) |
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return; |
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#else |
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return; |
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#endif |
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} |
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|
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/* get phandle to MSI controller */ |
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prop = (u32 *)fdt_getprop(blob, nodeoffset, "msi-parent", 0); |
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if (prop == NULL) { |
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debug("\n%s: ERROR: missing msi-parent: PCIe%d\n", |
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__func__, pcie->idx); |
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return; |
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} |
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phandle = fdt32_to_cpu(*prop); |
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|
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/* set one msi-map row */ |
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fdt_appendprop_u32(blob, nodeoffset, "msi-map", devid); |
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fdt_appendprop_u32(blob, nodeoffset, "msi-map", phandle); |
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fdt_appendprop_u32(blob, nodeoffset, "msi-map", streamid); |
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fdt_appendprop_u32(blob, nodeoffset, "msi-map", 1); |
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} |
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|
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static void fdt_fixup_pcie(void *blob) |
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{ |
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struct udevice *dev, *bus; |
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struct ls_pcie *pcie; |
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int streamid; |
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int index; |
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pci_dev_t bdf; |
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|
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/* Scan all known buses */ |
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for (pci_find_first_device(&dev); |
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dev; |
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pci_find_next_device(&dev)) { |
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for (bus = dev; device_is_on_pci_bus(bus);) |
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bus = bus->parent; |
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pcie = dev_get_priv(bus); |
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|
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streamid = ls_pcie_next_streamid(); |
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if (streamid < 0) { |
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debug("ERROR: no stream ids free\n"); |
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continue; |
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} |
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|
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index = ls_pcie_next_lut_index(pcie); |
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if (index < 0) { |
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debug("ERROR: no LUT indexes free\n"); |
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continue; |
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} |
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|
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/* the DT fixup must be relative to the hose first_busno */ |
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bdf = dm_pci_get_bdf(dev) - PCI_BDF(bus->seq, 0, 0); |
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/* map PCI b.d.f to streamID in LUT */ |
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ls_pcie_lut_set_mapping(pcie, index, bdf >> 8, |
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streamid); |
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/* update msi-map in device tree */ |
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fdt_pcie_set_msi_map_entry(blob, pcie, bdf >> 8, |
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streamid); |
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} |
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} |
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#endif |
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|
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static void ft_pcie_ls_setup(void *blob, struct ls_pcie *pcie) |
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{ |
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int off; |
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|
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off = fdt_node_offset_by_compat_reg(blob, "fsl,ls-pcie", |
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pcie->dbi_res.start); |
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if (off < 0) { |
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#ifdef CONFIG_FSL_PCIE_COMPAT /* Compatible with older version of dts node */ |
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off = fdt_node_offset_by_compat_reg(blob, |
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CONFIG_FSL_PCIE_COMPAT, |
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pcie->dbi_res.start); |
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if (off < 0) |
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return; |
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#else |
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return; |
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#endif |
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} |
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|
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if (pcie->enabled) |
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fdt_set_node_status(blob, off, FDT_STATUS_OKAY, 0); |
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else |
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fdt_set_node_status(blob, off, FDT_STATUS_DISABLED, 0); |
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} |
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|
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/* Fixup Kernel DT for PCIe */ |
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void ft_pci_setup(void *blob, bd_t *bd) |
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{ |
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struct ls_pcie *pcie; |
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|
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list_for_each_entry(pcie, &ls_pcie_list, list) |
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ft_pcie_ls_setup(blob, pcie); |
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|
||||
#ifdef CONFIG_FSL_LSCH3 |
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fdt_fixup_pcie(blob); |
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#endif |
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} |
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|
||||
#else /* !CONFIG_OF_BOARD_SETUP */ |
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void ft_pci_setup(void *blob, bd_t *bd) |
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{ |
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} |
||||
#endif |
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