powerpc: mpc85xx: Implemente workaround for CPU erratum A-007907

Core hang occurs when using L1 stashes. Workaround is to disable L1
stashes so software uses L2 cache for stashes instead.

Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
Signed-off-by: Darwin Dingel <darwin.dingel@alliedtelesis.co.nz>
Cc: York Sun <york.sun@nxp.com>
[York S: Move SYS_FSL_ERRATUM_A007907 to Kconfig]
Reviewed-by: York Sun <york.sun@nxp.com>

arch/powerpc/cpu/mpc85xx/Kconfig

@@ -365,6 +365,7 @@ config ARCH_B4860
 	select SYS_FSL_ERRATUM_A007075
 	select SYS_FSL_ERRATUM_A007186
 	select SYS_FSL_ERRATUM_A007212
+	select SYS_FSL_ERRATUM_A007907
 	select SYS_FSL_ERRATUM_A009942
 	select SYS_FSL_HAS_DDR3
 	select SYS_FSL_HAS_SEC
@@ -830,6 +831,7 @@ config ARCH_T2080
 	select SYS_FSL_ERRATUM_A006593
 	select SYS_FSL_ERRATUM_A007186
 	select SYS_FSL_ERRATUM_A007212
+	select SYS_FSL_ERRATUM_A007907
 	select SYS_FSL_ERRATUM_A009942
 	select SYS_FSL_ERRATUM_ESDHC111
 	select SYS_FSL_HAS_DDR3
@@ -891,6 +893,7 @@ config ARCH_T4240
 	select SYS_FSL_ERRATUM_A006593
 	select SYS_FSL_ERRATUM_A007186
 	select SYS_FSL_ERRATUM_A007798
+	select SYS_FSL_ERRATUM_A007907
 	select SYS_FSL_ERRATUM_A009942
 	select SYS_FSL_HAS_DDR3
 	select SYS_FSL_HAS_SEC
@@ -1081,6 +1084,9 @@ config SYS_FSL_ERRATUM_A007212
 config SYS_FSL_ERRATUM_A007798
 	bool
 
+config SYS_FSL_ERRATUM_A007907
+	bool
+
 config SYS_FSL_ERRATUM_A008044
 	bool
 

arch/powerpc/cpu/mpc85xx/cmd_errata.c

@@ -330,7 +330,9 @@ static int do_errata(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
 #ifdef CONFIG_SYS_FSL_ERRATUM_A009663
 	puts("Work-around for Erratum A009663 enabled\n");
 #endif
-
+#ifdef CONFIG_SYS_FSL_ERRATUM_A007907
+	puts("Work-around for Erratum A007907 enabled\n");
+#endif
 	return 0;
 }
 

arch/powerpc/cpu/mpc85xx/cpu_init.c

@@ -777,6 +777,13 @@ int cpu_init_r(void)
 		sync();
 	}
 #endif
+
+#ifdef CONFIG_SYS_FSL_ERRATUM_A007907
+	flush_dcache();
+	mtspr(L1CSR2, (mfspr(L1CSR2) & ~L1CSR2_DCSTASHID));
+	sync();
+#endif
+
 #ifdef CONFIG_SYS_FSL_ERRATUM_A005812
 	/*
 	 * A-005812 workaround sets bit 32 of SPR 976 for SoCs running

arch/powerpc/include/asm/processor.h

@@ -501,6 +501,7 @@
 #define   L1CSR1_ICE		0x00000001	/* Instruction Cache Enable */
 #define SPRN_L1CSR2	0x25e	/* L1 Data Cache Control and Status Register 2 */
 #define   L1CSR2_DCWS		0x40000000	/* Data Cache Write Shadow */
+#define   L1CSR2_DCSTASHID  0x000003ff	/* Data Cache Stash ID */
 #define SPRN_L2CSR0	0x3f9	/* L2 Data Cache Control and Status Register 0 */
 #define   L2CSR0_L2E		0x80000000	/* L2 Cache Enable */
 #define   L2CSR0_L2PE		0x40000000	/* L2 Cache Parity/ECC Enable */