Wolfgang Denk
16 years ago
commit
06c2942218
@ -0,0 +1,51 @@ |
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#
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# (C) Copyright 2007
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# Stefan Roese, DENX Software Engineering, sr@denx.de.
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#
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# See file CREDITS for list of people who contributed to this
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# project.
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#
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# This program is free software; you can redistribute it and/or
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# modify it under the terms of the GNU General Public License as
|
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# published by the Free Software Foundation; either version 2 of
|
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# the License, or (at your option) any later version.
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#
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# This program is distributed in the hope that it will be useful,
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# but WITHOUT ANY WARRANTY; without even the implied warranty of
|
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# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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# GNU General Public License for more details.
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#
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# You should have received a copy of the GNU General Public License
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# along with this program; if not, write to the Free Software
|
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# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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# MA 02111-1307 USA
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#
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include $(TOPDIR)/config.mk |
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LIB = $(obj)lib$(BOARD).a
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COBJS = $(BOARD).o
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SOBJS =
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SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
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OBJS := $(addprefix $(obj),$(COBJS))
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SOBJS := $(addprefix $(obj),$(SOBJS))
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$(LIB): $(OBJS) $(SOBJS) |
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$(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS)
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clean: |
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rm -f $(SOBJS) $(OBJS)
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distclean: clean |
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rm -f $(LIB) core *.bak $(obj).depend
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#########################################################################
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# defines $(obj).depend target
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include $(SRCTREE)/rules.mk |
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sinclude $(obj).depend |
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#########################################################################
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@ -0,0 +1,24 @@ |
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#
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# (C) Copyright 2000
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# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
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#
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# See file CREDITS for list of people who contributed to this
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# project.
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#
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# This program is free software; you can redistribute it and/or
|
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# modify it under the terms of the GNU General Public License as
|
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# published by the Free Software Foundation; either version 2 of
|
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# the License, or (at your option) any later version.
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#
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# This program is distributed in the hope that it will be useful,
|
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# but WITHOUT ANY WARRANTY; without even the implied warranty of
|
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# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
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# GNU General Public License for more details.
|
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#
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# You should have received a copy of the GNU General Public License
|
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# along with this program; if not, write to the Free Software
|
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# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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# MA 02111-1307 USA
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#
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TEXT_BASE = 0xFFFC0000
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@ -0,0 +1,101 @@ |
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/*
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* (C) Copyright 2007-2008 |
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* Dirk Eibach, Guntermann & Drunck GmbH, eibach@gdsys.de |
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* |
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* See file CREDITS for list of people who contributed to this |
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* project. |
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* |
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* This program is free software; you can redistribute it and/or |
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* modify it under the terms of the GNU General Public License as |
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* published by the Free Software Foundation; either version 2 of |
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* the License, or (at your option) any later version. |
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* |
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* This program is distributed in the hope that it will be useful, |
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* but WITHOUT ANY WARRANTY; without even the implied warranty of |
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
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* GNU General Public License for more details. |
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* |
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* You should have received a copy of the GNU General Public License |
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* along with this program; if not, write to the Free Software |
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
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* MA 02111-1307 USA |
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*/ |
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#include <common.h> |
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#include <command.h> |
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#include <asm/processor.h> |
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#include <asm/io.h> |
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#define HWTYPE_CCX16 1 |
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#define HWREV_300 3 |
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int board_early_init_f(void) |
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{ |
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mtdcr(uicsr, 0xFFFFFFFF); /* clear all ints */ |
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mtdcr(uicer, 0x00000000); /* disable all ints */ |
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mtdcr(uiccr, 0x00000000); /* set all to be non-critical */ |
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mtdcr(uicpr, 0xFFFFFF80); /* set int polarities */ |
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mtdcr(uictr, 0x10000000); /* set int trigger levels */ |
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mtdcr(uicvcr, 0x00000001); /* set vect base=0,INT0 highest prio */ |
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mtdcr(uicsr, 0xFFFFFFFF); /* clear all ints */ |
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/*
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* EBC Configuration Register: set ready timeout to 512 ebc-clks |
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* -> ca. 15 us |
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*/ |
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mtebc(epcr, 0xa8400000); /* ebc always driven */ |
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return 0; |
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} |
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/*
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* Check Board Identity: |
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*/ |
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int checkboard(void) |
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{ |
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char *s = getenv("serial#"); |
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u16 val = in_le16((void *)CONFIG_FPGA_BASE + 2); |
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u8 unit_type; |
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u8 hardware_cpu_ports; |
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u8 hardware_con_ports; |
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u8 hardware_version; |
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printf("Board: CATCenter Neo"); |
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if (s != NULL) { |
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puts(", serial# "); |
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puts(s); |
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} |
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puts("\n "); |
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unit_type = (val & 0xf000) >> 12; |
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hardware_cpu_ports = ((val & 0x0f00) >> 8) * 8; |
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hardware_con_ports = ((val & 0x00f0) >> 4) * 2; |
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hardware_version = val & 0x000f; |
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switch (unit_type) { |
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case HWTYPE_CCX16: |
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printf("CCX16-FPGA (80 UARTs)"); |
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break; |
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default: |
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printf("UnitType %d, unsupported", unit_type); |
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break; |
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} |
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printf(", %d cpu ports, %d console ports,", |
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hardware_cpu_ports, hardware_con_ports); |
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switch (hardware_version) { |
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case HWREV_300: |
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printf(" HW-Ver 3.00\n"); |
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break; |
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default: |
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printf(" HW-Ver %d, unsupported\n", |
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hardware_version); |
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break; |
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} |
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return 0; |
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} |
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@ -0,0 +1,132 @@ |
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/* |
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* (C) Copyright 2000 |
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* Wolfgang Denk, DENX Software Engineering, wd@denx.de. |
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* |
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* See file CREDITS for list of people who contributed to this |
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* project. |
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* |
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* This program is free software; you can redistribute it and/or |
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* modify it under the terms of the GNU General Public License as |
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* published by the Free Software Foundation; either version 2 of |
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* the License, or (at your option) any later version. |
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* |
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* This program is distributed in the hope that it will be useful, |
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* but WITHOUT ANY WARRANTY; without even the implied warranty of |
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
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* GNU General Public License for more details. |
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* |
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* You should have received a copy of the GNU General Public License |
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* along with this program; if not, write to the Free Software |
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
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* MA 02111-1307 USA |
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*/ |
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OUTPUT_ARCH(powerpc) |
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/* Do we need any of these for elf? |
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__DYNAMIC = 0; */ |
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SECTIONS |
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{ |
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.resetvec 0xFFFFFFFC : |
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{ |
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*(.resetvec) |
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} = 0xffff |
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/* Read-only sections, merged into text segment: */ |
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. = + SIZEOF_HEADERS; |
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.interp : { *(.interp) } |
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.hash : { *(.hash) } |
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.dynsym : { *(.dynsym) } |
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.dynstr : { *(.dynstr) } |
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.rel.text : { *(.rel.text) } |
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.rela.text : { *(.rela.text) } |
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.rel.data : { *(.rel.data) } |
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.rela.data : { *(.rela.data) } |
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.rel.rodata : { *(.rel.rodata) } |
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.rela.rodata : { *(.rela.rodata) } |
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.rel.got : { *(.rel.got) } |
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.rela.got : { *(.rela.got) } |
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.rel.ctors : { *(.rel.ctors) } |
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.rela.ctors : { *(.rela.ctors) } |
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.rel.dtors : { *(.rel.dtors) } |
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.rela.dtors : { *(.rela.dtors) } |
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.rel.bss : { *(.rel.bss) } |
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.rela.bss : { *(.rela.bss) } |
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.rel.plt : { *(.rel.plt) } |
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.rela.plt : { *(.rela.plt) } |
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.init : { *(.init) } |
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.plt : { *(.plt) } |
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.text : |
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{ |
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cpu/ppc4xx/start.o (.text) |
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*(.text) |
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*(.fixup) |
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*(.got1) |
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} |
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_etext = .; |
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PROVIDE (etext = .); |
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.rodata : |
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{ |
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*(.rodata) |
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*(.rodata1) |
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*(.rodata.str1.4) |
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} |
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.fini : { *(.fini) } =0 |
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.ctors : { *(.ctors) } |
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.dtors : { *(.dtors) } |
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/* Read-write section, merged into data segment: */ |
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. = (. + 0x00FF) & 0xFFFFFF00; |
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_erotext = .; |
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PROVIDE (erotext = .); |
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.reloc : |
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{ |
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*(.got) |
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_GOT2_TABLE_ = .; |
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*(.got2) |
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_FIXUP_TABLE_ = .; |
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*(.fixup) |
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} |
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__got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2; |
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__fixup_entries = (. - _FIXUP_TABLE_)>>2; |
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.data : |
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{ |
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*(.data) |
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*(.data1) |
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*(.sdata) |
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*(.sdata2) |
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*(.dynamic) |
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CONSTRUCTORS |
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} |
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_edata = .; |
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PROVIDE (edata = .); |
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. = .; |
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__u_boot_cmd_start = .; |
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.u_boot_cmd : { *(.u_boot_cmd) } |
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__u_boot_cmd_end = .; |
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. = .; |
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__start___ex_table = .; |
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__ex_table : { *(__ex_table) } |
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__stop___ex_table = .; |
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. = ALIGN(256); |
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__init_begin = .; |
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.text.init : { *(.text.init) } |
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.data.init : { *(.data.init) } |
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. = ALIGN(256); |
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__init_end = .; |
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__bss_start = .; |
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.bss (NOLOAD) : |
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{ |
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*(.sbss) *(.scommon) |
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*(.dynbss) |
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*(.bss) |
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*(COMMON) |
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} |
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_end = . ; |
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PROVIDE (end = .); |
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} |
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@ -0,0 +1,231 @@ |
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/*
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* (C) Copyright 2007-2008 |
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* Dirk Eibach, Guntermann & Drunck GmbH, eibach@gdsys.de |
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* |
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* See file CREDITS for list of people who contributed to this |
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* project. |
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* |
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* This program is free software; you can redistribute it and/or |
||||
* modify it under the terms of the GNU General Public License as |
||||
* published by the Free Software Foundation; either version 2 of |
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* the License, or (at your option) any later version. |
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* |
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* This program is distributed in the hope that it will be useful, |
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of |
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
||||
* GNU General Public License for more details. |
||||
* |
||||
* You should have received a copy of the GNU General Public License |
||||
* along with this program; if not, write to the Free Software |
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
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* MA 02111-1307 USA |
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*/ |
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#ifndef __CONFIG_H |
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#define __CONFIG_H |
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#define CONFIG_405EP 1 /* this is a PPC405 CPU */ |
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#define CONFIG_4xx 1 /* member of PPC4xx family */ |
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#define CONFIG_NEO 1 /* on a Neo board */ |
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/*
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* Include common defines/options for all AMCC eval boards |
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*/ |
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#define CONFIG_HOSTNAME neo |
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#include "amcc-common.h" |
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#define CONFIG_BOARD_EARLY_INIT_F /* call board_early_init_f */ |
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#define CONFIG_SYS_CLK_FREQ 33333333 /* external frequency to pll */ |
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|
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/*
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* Configure PLL |
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*/ |
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#define PLLMR0_DEFAULT PLLMR0_266_133_66_33 |
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#define PLLMR1_DEFAULT PLLMR1_266_133_66_33 |
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|
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/* new uImage format support */ |
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#define CONFIG_FIT |
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#define CONFIG_FIT_VERBOSE /* enable fit_format_{error,warning}() */ |
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|
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#define CONFIG_ENV_IS_IN_FLASH /* use FLASH for environment vars */ |
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|
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/*
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* Default environment variables |
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*/ |
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#define CONFIG_EXTRA_ENV_SETTINGS \ |
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CONFIG_AMCC_DEF_ENV \
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CONFIG_AMCC_DEF_ENV_POWERPC \
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CONFIG_AMCC_DEF_ENV_NOR_UPD \
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"kernel_addr=fc000000\0" \
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"fdt_addr=fc1e0000\0" \
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"ramdisk_addr=fc200000\0" \
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"" |
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#define CONFIG_PHY_ADDR 4 /* PHY address */ |
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#define CONFIG_HAS_ETH0 |
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#define CONFIG_HAS_ETH1 |
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#define CONFIG_PHY1_ADDR 0xc /* EMAC1 PHY address */ |
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#define CONFIG_PHY_CLK_FREQ EMAC_STACR_CLK_66MHZ |
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|
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/*
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* Commands additional to the ones defined in amcc-common.h |
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*/ |
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#define CONFIG_CMD_CACHE |
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#define CONFIG_CMD_DATE |
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#define CONFIG_CMD_DTT |
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#undef CONFIG_CMD_EEPROM |
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/*
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* SDRAM configuration (please see cpu/ppc/sdram.[ch]) |
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*/ |
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#define CONFIG_SDRAM_BANK0 1 /* init onboard SDRAM bank 0 */ |
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|
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/* SDRAM timings used in datasheet */ |
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#define CONFIG_SYS_SDRAM_CL 3 /* CAS latency */ |
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#define CONFIG_SYS_SDRAM_tRP 20 /* PRECHARGE command period */ |
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#define CONFIG_SYS_SDRAM_tRC 66 /* ACTIVE-to-ACTIVE command period */ |
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#define CONFIG_SYS_SDRAM_tRCD 20 /* ACTIVE-to-READ delay */ |
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#define CONFIG_SYS_SDRAM_tRFC 66 /* Auto refresh period */ |
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|
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/*
|
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* If CONFIG_SYS_EXT_SERIAL_CLOCK, then the UART divisor is 1. |
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* If CONFIG_SYS_405_UART_ERRATA_59, then UART divisor is 31. |
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* Otherwise, UART divisor is determined by CPU Clock and CONFIG_SYS_BASE_BAUD value. |
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* The Linux BASE_BAUD define should match this configuration. |
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* baseBaud = cpuClock/(uartDivisor*16) |
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* If CONFIG_SYS_405_UART_ERRATA_59 and 200MHz CPU clock, |
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* set Linux BASE_BAUD to 403200. |
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*/ |
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#undef CONFIG_SERIAL_SOFTWARE_FIFO |
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#undef CONFIG_SYS_EXT_SERIAL_CLOCK /* external serial clock */ |
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#undef CONFIG_SYS_405_UART_ERRATA_59 /* 405GP/CR Rev. D silicon */ |
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#define CONFIG_SYS_BASE_BAUD 691200 |
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|
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/*
|
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* I2C stuff |
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*/ |
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#define CONFIG_SYS_I2C_SPEED 100000 /* I2C speed and slave address */ |
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|
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/* RTC */ |
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#define CONFIG_RTC_DS1337 |
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#define CONFIG_SYS_I2C_RTC_ADDR 0x68 |
||||
|
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/* Temp sensor/hwmon/dtt */ |
||||
#define CONFIG_DTT_LM63 1 /* National LM63 */ |
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#define CONFIG_DTT_SENSORS { 0 } /* Sensor addresses */ |
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#define CONFIG_DTT_PWM_LOOKUPTABLE \ |
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{ { 40, 10 }, { 50, 20 }, { 60, 40 } } |
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#define CONFIG_DTT_TACH_LIMIT 0xa10 |
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|
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/*
|
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* FLASH organization |
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*/ |
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#define CONFIG_SYS_FLASH_CFI /* The flash is CFI compatible */ |
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#define CONFIG_FLASH_CFI_DRIVER /* Use common CFI driver */ |
||||
|
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#define CONFIG_SYS_FLASH_BASE 0xFC000000 |
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#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE } |
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|
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#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */ |
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#define CONFIG_SYS_MAX_FLASH_SECT 512 /* max number of sectors on one chip */ |
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|
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#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ |
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#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ |
||||
|
||||
#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 /* use buffered writes (20x faster) */ |
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#define CONFIG_SYS_FLASH_PROTECTION 1 /* use hardware flash protection */ |
||||
|
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#define CONFIG_SYS_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */ |
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#define CONFIG_SYS_FLASH_QUIET_TEST 1 /* don't warn upon unknown flash */ |
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|
||||
#ifdef CONFIG_ENV_IS_IN_FLASH |
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#define CONFIG_ENV_SECT_SIZE 0x20000 /* size of one complete sector */ |
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#define CONFIG_ENV_ADDR ((-CONFIG_SYS_MONITOR_LEN)-CONFIG_ENV_SECT_SIZE) |
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#define CONFIG_ENV_SIZE 0x2000 /* Total Size of Environment Sector */ |
||||
|
||||
/* Address and size of Redundant Environment Sector */ |
||||
#define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR-CONFIG_ENV_SECT_SIZE) |
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#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE) |
||||
#endif |
||||
|
||||
/*
|
||||
* PPC405 GPIO Configuration |
||||
*/ |
||||
#define CONFIG_SYS_4xx_GPIO_TABLE { /* GPIO Alternate1 */ \ |
||||
{ \
|
||||
/* GPIO Core 0 */ \
|
||||
{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO0 PerBLast */ \
|
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{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO1 TS1E */ \
|
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{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO2 TS2E */ \
|
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{ GPIO_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO3 TS1O */ \
|
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{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO4 TS2O */ \
|
||||
{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO5 TS3 */ \
|
||||
{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO6 TS4 */ \
|
||||
{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO7 TS5 */ \
|
||||
{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO8 TS6 */ \
|
||||
{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO9 TrcClk */ \
|
||||
{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO10 PerCS1 */ \
|
||||
{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO11 PerCS2 */ \
|
||||
{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO12 PerCS3 */ \
|
||||
{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO13 PerCS4 */ \
|
||||
{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO14 PerAddr03 */ \
|
||||
{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO15 PerAddr04 */ \
|
||||
{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO16 PerAddr05 */ \
|
||||
{ GPIO_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO17 IRQ0 */ \
|
||||
{ GPIO_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO18 IRQ1 */ \
|
||||
{ GPIO_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO19 IRQ2 */ \
|
||||
{ GPIO_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO20 IRQ3 */ \
|
||||
{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO21 IRQ4 */ \
|
||||
{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO22 IRQ5 */ \
|
||||
{ GPIO_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO23 IRQ6 */ \
|
||||
{ GPIO_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO24 UART0_DCD */ \
|
||||
{ GPIO_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO25 UART0_DSR */ \
|
||||
{ GPIO_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO26 UART0_RI */ \
|
||||
{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO27 UART0_DTR */ \
|
||||
{ GPIO_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO28 UART1_Rx */ \
|
||||
{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO29 UART1_Tx */ \
|
||||
{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO30 RejectPkt0 */ \
|
||||
{ GPIO_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO31 RejectPkt1 */ \
|
||||
} \
|
||||
} |
||||
|
||||
/*
|
||||
* Definitions for initial stack pointer and data area (in data cache) |
||||
*/ |
||||
/* use on chip memory (OCM) for temperary stack until sdram is tested */ |
||||
#define CONFIG_SYS_TEMP_STACK_OCM 1 |
||||
|
||||
/* On Chip Memory location */ |
||||
#define CONFIG_SYS_OCM_DATA_ADDR 0xF8000000 |
||||
#define CONFIG_SYS_OCM_DATA_SIZE 0x1000 |
||||
#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_OCM_DATA_ADDR /* inside of SDRAM */ |
||||
#define CONFIG_SYS_INIT_RAM_END CONFIG_SYS_OCM_DATA_SIZE /* End of used area in RAM */ |
||||
|
||||
#define CONFIG_SYS_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */ |
||||
#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE) |
||||
#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET |
||||
|
||||
/*
|
||||
* External Bus Controller (EBC) Setup |
||||
*/ |
||||
|
||||
/* Memory Bank 0 (NOR-FLASH) initialization */ |
||||
#define CONFIG_SYS_EBC_PB0AP 0x92015480 |
||||
#define CONFIG_SYS_EBC_PB0CR 0xFC0DA000 /* BAS=0xFC0,BS=64MB,BU=R/W,BW=16bit */ |
||||
|
||||
/* Memory Bank 1 (NVRAM) initialization */ |
||||
#define CONFIG_SYS_EBC_PB1AP 0x92015480 |
||||
#define CONFIG_SYS_EBC_PB1CR 0xFB85A000 /* BAS=0xFF8,BS=4MB,BU=R/W,BW=8bit */ |
||||
|
||||
/* Memory Bank 2 (FPGA) initialization */ |
||||
#define CONFIG_FPGA_BASE 0x7f100000 |
||||
#define CONFIG_SYS_EBC_PB2AP 0x92015480 |
||||
#define CONFIG_SYS_EBC_PB2CR 0x7f11a000 /* BAS=0x7f1,BS=1MB,BU=R/W,BW=16bit */ |
||||
|
||||
/* Memory Bank 3 (Latches) initialization */ |
||||
#define CONFIG_SYS_EBC_PB3AP 0x92015480 |
||||
#define CONFIG_SYS_EBC_PB3CR 0x7f21a000 /* BAS=0x7f2,BS=1MB,BU=R/W,BW=16bit */ |
||||
|
||||
#endif /* __CONFIG_H */ |
||||
@ -0,0 +1,255 @@ |
||||
/*
|
||||
* (C) Copyright 2008 |
||||
* Niklaus Giger, Netstal Maschinen AG, niklaus.giger@netstal.com |
||||
* adapted from amcc-common.h by |
||||
* (C) Copyright 2008 |
||||
* * Stefan Roese, DENX Software Engineering, sr@denx.de. |
||||
* |
||||
* Common configuration options for all Netstal boards |
||||
* |
||||
* This program is free software; you can redistribute it and/or |
||||
* modify it under the terms of the GNU General Public License as |
||||
* published by the Free Software Foundation; either version 2 of |
||||
* the License, or (at your option) any later version. |
||||
* |
||||
* This program is distributed in the hope that it will be useful, |
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of |
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
||||
* GNU General Public License for more details. |
||||
* |
||||
* You should have received a copy of the GNU General Public License |
||||
* along with this program; if not, write to the Free Software |
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
||||
* MA 02111-1307 USA |
||||
*/ |
||||
|
||||
#ifndef __NETSTAL_COMMON_H |
||||
#define __NETSTAL_COMMON_H |
||||
|
||||
#define CONFIG_SYS_SDRAM_BASE 0x00000000 /* _must_ be 0 */ |
||||
#define CONFIG_SYS_MONITOR_BASE TEXT_BASE /* Start of U-Boot */ |
||||
#define CONFIG_SYS_MONITOR_LEN (320 * 1024) /* Reserve 320 kB for Monitor */ |
||||
#define CONFIG_SYS_MALLOC_LEN (256 * 1024) /* Reserve 256 kB for malloc() */ |
||||
|
||||
/*
|
||||
* UART |
||||
*/ |
||||
#define CONFIG_SERIAL_MULTI |
||||
#define CONFIG_SYS_BAUDRATE_TABLE \ |
||||
{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200, 230400} |
||||
|
||||
/*
|
||||
* I2C |
||||
*/ |
||||
#define CONFIG_HARD_I2C 1 /* I2C with hardware support */ |
||||
#define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */ |
||||
#define CONFIG_SYS_I2C_SLAVE 0x7F |
||||
|
||||
/* This is the 7bit address of the device, not including P. */ |
||||
#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 |
||||
#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 |
||||
|
||||
/* The EEPROM can do 16byte ( 1 << 4 ) page writes. */ |
||||
#define CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW 0x07 |
||||
#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 4 |
||||
#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 |
||||
#define CONFIG_SYS_EEPROM_PAGE_WRITE_ENABLE |
||||
|
||||
/*
|
||||
* Ethernet/EMAC/PHY |
||||
*/ |
||||
#define CONFIG_MII /* MII PHY management */ |
||||
#define CONFIG_PHY_ADDR 1 /* PHY address */ |
||||
#if defined(CONFIG_440) |
||||
#define CONFIG_NET_MULTI 1 |
||||
#define CONFIG_NETCONSOLE /* include NetConsole support */ |
||||
#define CONFIG_SYS_RX_ETH_BUFFER 32 /* number of eth rx buffers */ |
||||
#else |
||||
#define CONFIG_SYS_RX_ETH_BUFFER 16 /* number of eth rx buffers */ |
||||
#endif |
||||
#define CONFIG_HAS_ETH0 |
||||
|
||||
/*
|
||||
* Commands |
||||
*/ |
||||
#include <config_cmd_default.h> |
||||
|
||||
#define CONFIG_CMD_ASKENV |
||||
#if defined(CONFIG_440) |
||||
#define CONFIG_CMD_CACHE |
||||
#endif |
||||
#define CONFIG_CMD_DHCP |
||||
#define CONFIG_CMD_DIAG |
||||
#define CONFIG_CMD_EEPROM |
||||
#define CONFIG_CMD_ELF |
||||
#define CONFIG_CMD_I2C |
||||
#define CONFIG_CMD_IRQ |
||||
#define CONFIG_CMD_MII |
||||
#define CONFIG_CMD_NET |
||||
#define CONFIG_CMD_NFS |
||||
#define CONFIG_CMD_PING |
||||
#define CONFIG_CMD_REGINFO |
||||
#define CONFIG_BOOT_RETRY_TIME 30 |
||||
#define CONFIG_RESET_TO_RETRY |
||||
/*
|
||||
* Miscellaneous configurable options |
||||
*/ |
||||
#define CONFIG_BOOTDELAY 1 /* autoboot after 1 second */ |
||||
#define CONFIG_SYS_LONGHELP /* undef to save memory */ |
||||
#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ |
||||
#if defined(CONFIG_CMD_KGDB) |
||||
#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ |
||||
#else |
||||
#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ |
||||
#endif |
||||
#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) |
||||
#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ |
||||
#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ |
||||
|
||||
#define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */ |
||||
#define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ |
||||
|
||||
#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */ |
||||
#define CONFIG_SYS_EXTBDINFO /* To use extended board_into (bd_t) */ |
||||
|
||||
#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */ |
||||
|
||||
#define CONFIG_CMDLINE_EDITING /* add command line history */ |
||||
#define CONFIG_AUTO_COMPLETE /* add autocompletion support */ |
||||
#define CONFIG_LOOPW /* enable loopw command */ |
||||
#define CONFIG_MX_CYCLIC /* enable mdc/mwc commands */ |
||||
#define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */ |
||||
#define CONFIG_VERSION_VARIABLE /* include version env variable */ |
||||
#define CONFIG_SYS_CONSOLE_INFO_QUIET /* don't print console @ startup*/ |
||||
|
||||
#define CONFIG_SYS_HUSH_PARSER /* Use the HUSH parser */ |
||||
#ifdef CONFIG_SYS_HUSH_PARSER |
||||
#define CONFIG_SYS_PROMPT_HUSH_PS2 "> " |
||||
#endif |
||||
|
||||
#define CONFIG_LOADS_ECHO /* echo on for serial download */ |
||||
#define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */ |
||||
|
||||
/*
|
||||
* BOOTP options |
||||
*/ |
||||
#define CONFIG_BOOTP_BOOTFILESIZE |
||||
#define CONFIG_BOOTP_BOOTPATH |
||||
#define CONFIG_BOOTP_GATEWAY |
||||
#define CONFIG_BOOTP_HOSTNAME |
||||
#define CONFIG_BOOTP_SUBNETMASK |
||||
|
||||
/*
|
||||
* For booting Linux, the board info and command line data |
||||
* have to be in the first 8 MB of memory, since this is |
||||
* the maximum mapped by the Linux kernel during initialization. |
||||
*/ |
||||
#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ |
||||
|
||||
/*
|
||||
* Internal Definitions |
||||
*/ |
||||
#if defined(CONFIG_CMD_KGDB) |
||||
#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port*/ |
||||
#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ |
||||
#endif |
||||
|
||||
/*
|
||||
* Pass open firmware flat tree |
||||
*/ |
||||
#define CONFIG_OF_LIBFDT |
||||
#define CONFIG_OF_BOARD_SETUP |
||||
|
||||
/*
|
||||
* Booting and default environment |
||||
*/ |
||||
#define CONFIG_PREBOOT "echo;" \ |
||||
"echo Type \"run net_nfs\" to mount root filesystem over NFS;" \
|
||||
"echo" |
||||
#define CONFIG_BOOTCOMMAND "run vx" |
||||
|
||||
/*
|
||||
* Only very few boards have default console not on ttyS0 (like Taishan) |
||||
*/ |
||||
#if !defined(CONFIG_USE_TTY) |
||||
#define CONFIG_USE_TTY ttyS0 |
||||
#endif |
||||
|
||||
/*
|
||||
* Only some 4xx PPC's are equipped with an FPU |
||||
*/ |
||||
#if defined(CONFIG_440EP) || defined(CONFIG_440EPX) || \ |
||||
defined(CONFIG_460EX) || defined(CONFIG_460GT) |
||||
#define CONFIG_NETSTAL_DEF_ENV_ROOTPATH "rootpath=/opt/eldk/ppc_4xxFP\0" |
||||
#else |
||||
#define CONFIG_NETSTAL_DEF_ENV_ROOTPATH "rootpath=/opt/eldk/ppc_4xx\0" |
||||
#endif |
||||
|
||||
/*
|
||||
* Only some boards need to extend the bootargs by some additional |
||||
* parameters (like Makalu) |
||||
*/ |
||||
#if !defined(CONFIG_ADDMISC) |
||||
#define CONFIG_ADDMISC "addmisc=setenv bootargs ${bootargs}\0" |
||||
#endif |
||||
|
||||
#define xstr(s) str(s) |
||||
#define str(s) #s |
||||
|
||||
/* Setup some values for the default environment variables */ |
||||
#define CONFIG_SERVERIP 172.25.1.1 |
||||
#define CONFIG_ETHADDR 00:60:13:00:00:00 /* Netstal Machines AG MAC */ |
||||
#define CONFIG_OVERWRITE_ETHADDR_ONCE |
||||
|
||||
#define CONFIG_SYS_TFTP_LOADADDR 0x01000000 |
||||
|
||||
/*
|
||||
* General common environment variables shared by all boards produced by Netstal Maschinen |
||||
*/ |
||||
#define CONFIG_NETSTAL_DEF_ENV \ |
||||
"netdev=eth0\0" \
|
||||
"nfsargs=setenv bootargs root=/dev/nfs rw " \
|
||||
"nfsroot=${serverip}:${rootpath}\0" \
|
||||
"ramargs=setenv bootargs root=/dev/ram rw\0" \
|
||||
"addip=setenv bootargs ${bootargs} " \
|
||||
"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
|
||||
":${hostname}:${netdev}:off panic=1\0" \
|
||||
"addtty=setenv bootargs ${bootargs}" \
|
||||
" console=" xstr(CONFIG_USE_TTY) ",${baudrate}\0" \
|
||||
CONFIG_ADDMISC \
|
||||
"initrd_high=30000000\0" \
|
||||
"kernel_addr_r=400000\0" \
|
||||
"fdt_addr_r=800000\0" \
|
||||
"hostname=" xstr(CONFIG_HOSTNAME) "\0" \
|
||||
"bootfile=" xstr(CONFIG_HOSTNAME) "/uImage\0" \
|
||||
"load=tftp 200000 " xstr(CONFIG_HOSTNAME) "/u-boot.bin\0" \
|
||||
"update=protect off " xstr(CONFIG_SYS_MONITOR_BASE) " FFFFFFFF;" \
|
||||
"era " xstr(CONFIG_SYS_MONITOR_BASE) " FFFFFFFF;" \
|
||||
"cp.b ${fileaddr} " xstr(CONFIG_SYS_MONITOR_BASE) " ${filesize};" \
|
||||
"setenv filesize\0" \
|
||||
"upd=run load update\0" \
|
||||
"vx_rom=" xstr(CONFIG_HOSTNAME) "/" \
|
||||
xstr(CONFIG_HOSTNAME) "_vx_rom\0" \
|
||||
"vx=tftp " xstr(CONFIG_SYS_TFTP_LOADADDR) " ${vx_rom};run vxargs;" \
|
||||
"bootvx\0" \
|
||||
"vxargs=setenv bootargs emac(0,0)c:${vx_rom} e=${ipaddr}" \
|
||||
" h=${serverip} u=dpu pw=netstal8752 " \
|
||||
"tn=" xstr(CONFIG_HOSTNAME) " f=0x3008\0" \
|
||||
CONFIG_NETSTAL_DEF_ENV_ROOTPATH |
||||
|
||||
/*
|
||||
* Default environment for arch/powerpc booting |
||||
* for boards that are ported to arch/powerpc |
||||
*/ |
||||
#define CONFIG_NETSTAL_DEF_ENV_POWERPC \ |
||||
"flash_self=run ramargs addip addtty addmisc;" \
|
||||
"bootm ${kernel_addr} ${ramdisk_addr} ${fdt_addr}\0" \
|
||||
"flash_nfs=run nfsargs addip addtty addmisc;" \
|
||||
"bootm ${kernel_addr} - ${fdt_addr}\0" \
|
||||
"net_nfs=tftp ${kernel_addr_r} ${bootfile}; " \
|
||||
"tftp ${fdt_addr_r} ${fdt_file}; " \
|
||||
"run nfsargs addip addtty addmisc;" \
|
||||
"bootm ${kernel_addr_r} - ${fdt_addr_r}\0" \
|
||||
"fdt_file=" xstr(CONFIG_HOSTNAME) "/" xstr(CONFIG_HOSTNAME) ".dtb\0" |
||||
|
||||
#endif /* __NETSTAL_COMMON_H */ |
||||
Loading…
Reference in new issue