Add support for S3C44B0 processor and DAVE B2 board * Patch by Steven Scholz, 20 Feb 2004: - Add support for MII commands on AT91RM9200 boards - some cleanup in AT91RM9200 ethernet codemaster
parent
028ab6b598
commit
074cff0d28
@ -0,0 +1,48 @@ |
||||
#
|
||||
# (C) Copyright 2002
|
||||
# Sysgo Real-Time Solutions, GmbH <www.elinos.com>
|
||||
# Marius Groeger <mgroeger@sysgo.de>
|
||||
#
|
||||
# See file CREDITS for list of people who contributed to this
|
||||
# project.
|
||||
#
|
||||
# This program is free software; you can redistribute it and/or
|
||||
# modify it under the terms of the GNU General Public License as
|
||||
# published by the Free Software Foundation; either version 2 of
|
||||
# the License, or (at your option) any later version.
|
||||
#
|
||||
# This program is distributed in the hope that it will be useful,
|
||||
# but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
# GNU General Public License for more details.
|
||||
#
|
||||
# You should have received a copy of the GNU General Public License
|
||||
# along with this program; if not, write to the Free Software
|
||||
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
# MA 02111-1307 USA
|
||||
#
|
||||
|
||||
include $(TOPDIR)/config.mk |
||||
|
||||
LIB = lib$(BOARD).a
|
||||
|
||||
OBJS := B2.o flash.o
|
||||
SOBJS := memsetup.o
|
||||
|
||||
$(LIB): $(OBJS) $(SOBJS) |
||||
$(AR) crv $@ $(OBJS) $(SOBJS)
|
||||
|
||||
clean: |
||||
rm -f $(SOBJS) $(OBJS)
|
||||
|
||||
distclean: clean |
||||
rm -f $(LIB) core *.bak .depend
|
||||
|
||||
#########################################################################
|
||||
|
||||
.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) |
||||
$(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
|
||||
|
||||
-include .depend |
||||
|
||||
#########################################################################
|
@ -0,0 +1,30 @@ |
||||
#
|
||||
# (C) Copyright 2000
|
||||
# Sysgo Real-Time Solutions, GmbH <www.elinos.com>
|
||||
# Marius Groeger <mgroeger@sysgo.de>
|
||||
#
|
||||
# (C) Copyright 2000-2004
|
||||
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
|
||||
#
|
||||
# See file CREDITS for list of people who contributed to this
|
||||
# project.
|
||||
#
|
||||
# This program is free software; you can redistribute it and/or
|
||||
# modify it under the terms of the GNU General Public License as
|
||||
# published by the Free Software Foundation; either version 2 of
|
||||
# the License, or (at your option) any later version.
|
||||
#
|
||||
# This program is distributed in the hope that it will be useful,
|
||||
# but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
# GNU General Public License for more details.
|
||||
#
|
||||
# You should have received a copy of the GNU General Public License
|
||||
# along with this program; if not, write to the Free Software
|
||||
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
# MA 02111-1307 USA
|
||||
#
|
||||
|
||||
TEXT_BASE = 0x0C100000
|
||||
|
||||
PLATFORM_CPPFLAGS += -Uarm
|
@ -0,0 +1,79 @@ |
||||
/*
|
||||
* (C) Copyright 2001 |
||||
* Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com |
||||
* |
||||
* See file CREDITS for list of people who contributed to this |
||||
* project. |
||||
* |
||||
* This program is free software; you can redistribute it and/or |
||||
* modify it under the terms of the GNU General Public License as |
||||
* published by the Free Software Foundation; either version 2 of |
||||
* the License, or (at your option) any later version. |
||||
* |
||||
* This program is distributed in the hope that it will be useful, |
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of |
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
||||
* GNU General Public License for more details. |
||||
* |
||||
* You should have received a copy of the GNU General Public License |
||||
* along with this program; if not, write to the Free Software |
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
||||
* MA 02111-1307 USA |
||||
*/ |
||||
|
||||
#include <common.h> |
||||
#include <asm/hardware.h> |
||||
|
||||
/*
|
||||
* include common flash code (for esd boards) |
||||
*/ |
||||
#include "../common/flash.c" |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Functions |
||||
*/ |
||||
static ulong flash_get_size (vu_long * addr, flash_info_t * info); |
||||
static void flash_get_offsets (ulong base, flash_info_t * info); |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
*/ |
||||
|
||||
unsigned long flash_init (void) |
||||
{ |
||||
#ifdef __DEBUG_START_FROM_SRAM__ |
||||
return CFG_DUMMY_FLASH_SIZE; |
||||
#else |
||||
unsigned long size_b0; |
||||
int i; |
||||
uint pbcr; |
||||
unsigned long base_b0; |
||||
int size_val = 0; |
||||
|
||||
/* Init: no FLASHes known */ |
||||
for (i=0; i<CFG_MAX_FLASH_BANKS; ++i) { |
||||
flash_info[i].flash_id = FLASH_UNKNOWN; |
||||
} |
||||
|
||||
/* Static FLASH Bank configuration here - FIXME XXX */ |
||||
|
||||
size_b0 = flash_get_size((vu_long *)CFG_FLASH_BASE, &flash_info[0]); |
||||
|
||||
if (flash_info[0].flash_id == FLASH_UNKNOWN) { |
||||
printf ("## Unknown FLASH on Bank 0 - Size = 0x%08lx = %ld MB\n", |
||||
size_b0, size_b0<<20); |
||||
} |
||||
|
||||
/* Setup offsets */ |
||||
flash_get_offsets (0, &flash_info[0]); |
||||
|
||||
/* Monitor protection ON by default */ |
||||
(void)flash_protect(FLAG_PROTECT_SET, |
||||
-CFG_MONITOR_LEN, |
||||
0xffffffff, |
||||
&flash_info[0]); |
||||
|
||||
flash_info[0].size = size_b0; |
||||
|
||||
return (size_b0); |
||||
#endif |
||||
} |
@ -0,0 +1,167 @@ |
||||
/* |
||||
* (C) Copyright 2004 |
||||
* DAVE Srl |
||||
* |
||||
* http://www.dave-tech.it |
||||
* http://www.wawnet.biz |
||||
* mailto:info@wawnet.biz
|
||||
* |
||||
* memsetup-sa1110.S (blob): memory setup for various SA1110 architectures |
||||
* Modified By MATTO |
||||
* |
||||
* Copyright (C) 2001 Erik Mouw (J.A.K.Mouw@its.tudelft.nl)
|
||||
* |
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by |
||||
* the Free Software Foundation; either version 2 of the License, or
|
||||
* (at your option) any later version. |
||||
* |
||||
* This program is distributed in the hope that it will be useful, |
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
||||
* GNU General Public License for more details. |
||||
* |
||||
* You should have received a copy of the GNU General Public License |
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA |
||||
* |
||||
*/ |
||||
|
||||
/* |
||||
* Documentation: |
||||
* Intel Corporation, "Intel StrongARM SA-1110 Microprocessor |
||||
* Advanced Developer's manual, December 1999 |
||||
* |
||||
* Intel has a very hard to find SDRAM configurator on their web site: |
||||
* http://appzone.intel.com/hcd/sa1110/memory/index.asp |
||||
* |
||||
* NOTE: This code assumes that an SA1110 CPU *always* uses SDRAM. This |
||||
* appears to be true, but it might be possible that somebody designs a |
||||
* board with mixed EDODRAM/SDRAM memory (which is a bad idea). -- Erik |
||||
* |
||||
* 04-10-2001: SELETZ |
||||
* - separated memory config for multiple platform support |
||||
* - perform SA1110 Hardware Reset Procedure |
||||
* |
||||
*/ |
||||
|
||||
.equ B0_Tacs, 0x0 /* 0clk */ |
||||
.equ B0_Tcos, 0x0 /* 0clk */ |
||||
.equ B0_Tacc, 0x4 /* 6clk */ |
||||
.equ B0_Tcoh, 0x0 /* 0clk */ |
||||
.equ B0_Tah, 0x0 /* 0clk */ |
||||
.equ B0_Tacp, 0x0 /* 0clk */ |
||||
.equ B0_PMC, 0x0 /* normal(1data) */ |
||||
/* Bank 1 parameter */ |
||||
.equ B1_Tacs, 0x3 /* 4clk */ |
||||
.equ B1_Tcos, 0x3 /* 4clk */ |
||||
.equ B1_Tacc, 0x7 /* 14clkv */ |
||||
.equ B1_Tcoh, 0x3 /* 4clk */ |
||||
.equ B1_Tah, 0x3 /* 4clk */ |
||||
.equ B1_Tacp, 0x3 /* 6clk */ |
||||
.equ B1_PMC, 0x0 /* normal(1data) */ |
||||
|
||||
/* Bank 2 parameter - LAN91C96 */ |
||||
.equ B2_Tacs, 0x3 /* 4clk */ |
||||
.equ B2_Tcos, 0x3 /* 4clk */ |
||||
.equ B2_Tacc, 0x7 /* 14clk */ |
||||
.equ B2_Tcoh, 0x3 /* 4clk */ |
||||
.equ B2_Tah, 0x3 /* 4clk */ |
||||
.equ B2_Tacp, 0x3 /* 6clk */ |
||||
.equ B2_PMC, 0x0 /* normal(1data) */ |
||||
|
||||
/* Bank 3 parameter */ |
||||
.equ B3_Tacs, 0x3 /* 4clk */ |
||||
.equ B3_Tcos, 0x3 /* 4clk */ |
||||
.equ B3_Tacc, 0x7 /* 14clk */ |
||||
.equ B3_Tcoh, 0x3 /* 4clk */ |
||||
.equ B3_Tah, 0x3 /* 4clk */ |
||||
.equ B3_Tacp, 0x3 /* 6clk */ |
||||
.equ B3_PMC, 0x0 /* normal(1data) */ |
||||
|
||||
/* Bank 4 parameter */ |
||||
.equ B4_Tacs, 0x3 /* 4clk */ |
||||
.equ B4_Tcos, 0x3 /* 4clk */ |
||||
.equ B4_Tacc, 0x7 /* 14clk */ |
||||
.equ B4_Tcoh, 0x3 /* 4clk */ |
||||
.equ B4_Tah, 0x3 /* 4clk */ |
||||
.equ B4_Tacp, 0x3 /* 6clk */ |
||||
.equ B4_PMC, 0x0 /* normal(1data) */ |
||||
|
||||
/* Bank 5 parameter */ |
||||
.equ B5_Tacs, 0x3 /* 4clk */ |
||||
.equ B5_Tcos, 0x3 /* 4clk */ |
||||
.equ B5_Tacc, 0x7 /* 14clk */ |
||||
.equ B5_Tcoh, 0x3 /* 4clk */ |
||||
.equ B5_Tah, 0x3 /* 4clk */ |
||||
.equ B5_Tacp, 0x3 /* 6clk */ |
||||
.equ B5_PMC, 0x0 /* normal(1data) */ |
||||
|
||||
/* Bank 6(if SROM) parameter */ |
||||
.equ B6_Tacs, 0x3 /* 4clk */ |
||||
.equ B6_Tcos, 0x3 /* 4clk */ |
||||
.equ B6_Tacc, 0x7 /* 14clk */ |
||||
.equ B6_Tcoh, 0x3 /* 4clk */ |
||||
.equ B6_Tah, 0x3 /* 4clk */ |
||||
.equ B6_Tacp, 0x3 /* 6clk */ |
||||
.equ B6_PMC, 0x0 /* normal(1data) */ |
||||
|
||||
/* Bank 7(if SROM) parameter */ |
||||
.equ B7_Tacs, 0x3 /* 4clk */ |
||||
.equ B7_Tcos, 0x3 /* 4clk */ |
||||
.equ B7_Tacc, 0x7 /* 14clk */ |
||||
.equ B7_Tcoh, 0x3 /* 4clk */ |
||||
.equ B7_Tah, 0x3 /* 4clk */ |
||||
.equ B7_Tacp, 0x3 /* 6clk */ |
||||
.equ B7_PMC, 0x0 /* normal(1data) */ |
||||
|
||||
/* Bank 6 parameter */ |
||||
.equ B6_MT, 0x3 /* SDRAM */ |
||||
.equ B6_Trcd, 0x0 /* 2clk */ |
||||
.equ B6_SCAN, 0x0 /* 10bit */ |
||||
|
||||
.equ B7_MT, 0x3 /* SDRAM */ |
||||
.equ B7_Trcd, 0x0 /* 2clk */ |
||||
.equ B7_SCAN, 0x0 /* 10bit */ |
||||
|
||||
|
||||
/* REFRESH parameter */ |
||||
.equ REFEN, 0x1 /* Refresh enable */ |
||||
.equ TREFMD, 0x0 /* CBR(CAS before RAS)/Auto refresh */ |
||||
.equ Trp, 0x0 /* 2clk */ |
||||
.equ Trc, 0x3 /* 0x1=5clk 0x3=11clk*/ |
||||
.equ Tchr, 0x0 /* 0x2=3clk 0x0=0clks */ |
||||
.equ REFCNT, 879 |
||||
|
||||
MEMORY_CONFIG: |
||||
.long 0x12111900 /* Bank0 = OM[1:0] , Bank1-7 16bit, Bank2=Nowait,UB/LB*/ |
||||
.word ((B0_Tacs<<13)+(B0_Tcos<<11)+(B0_Tacc<<8)+(B0_Tcoh<<6)+(B0_Tah<<4)+(B0_Tacp<<2)+(B0_PMC)) /*GCS0*/ |
||||
.word ((B1_Tacs<<13)+(B1_Tcos<<11)+(B1_Tacc<<8)+(B1_Tcoh<<6)+(B1_Tah<<4)+(B1_Tacp<<2)+(B1_PMC)) /*GCS1*/ |
||||
.word ((B2_Tacs<<13)+(B2_Tcos<<11)+(B2_Tacc<<8)+(B2_Tcoh<<6)+(B2_Tah<<4)+(B2_Tacp<<2)+(B2_PMC)) /*GCS2*/ |
||||
.word ((B3_Tacs<<13)+(B3_Tcos<<11)+(B3_Tacc<<8)+(B3_Tcoh<<6)+(B3_Tah<<4)+(B3_Tacp<<2)+(B3_PMC)) /*GCS3*/ |
||||
.word ((B4_Tacs<<13)+(B4_Tcos<<11)+(B4_Tacc<<8)+(B4_Tcoh<<6)+(B4_Tah<<4)+(B4_Tacp<<2)+(B4_PMC)) /*GCS4*/ |
||||
.word ((B5_Tacs<<13)+(B5_Tcos<<11)+(B5_Tacc<<8)+(B5_Tcoh<<6)+(B5_Tah<<4)+(B5_Tacp<<2)+(B5_PMC)) /*GCS5*/ |
||||
.word ((B6_MT<<15)+(B6_Trcd<<2)+(B6_SCAN)) /*GCS6*/ |
||||
.word ((B7_MT<<15)+(B7_Trcd<<2)+(B7_SCAN)) /*GCS7*/ |
||||
.word ((REFEN<<23)+(TREFMD<<22)+(Trp<<20)+(Trc<<18)+(Tchr<<16)+REFCNT) /*REFRESH RFEN=1, TREFMD=0, trp=3clk, trc=5clk, tchr=3clk,count=1019*/ |
||||
.word 0x17 /*SCLK power down mode, BANKSIZE 16M/16M*/ |
||||
.word 0x20 /*MRSR6 CL=2clk*/ |
||||
.word 0x20 /*MRSR7*/ |
||||
|
||||
|
||||
.globl memsetup
|
||||
memsetup: |
||||
|
||||
/* |
||||
the next instruction fail due memory relocation... |
||||
we'll find the right MEMORY_CONFIG address with the next 3 lines... |
||||
*/ |
||||
/*ldr r0, =MEMORY_CONFIG*/ |
||||
mov r0, pc |
||||
ldr r1, =(0x38+4) |
||||
sub r0, r0, r1 |
||||
|
||||
ldmia r0, {r1-r13} |
||||
ldr r0, =0x01c80000 |
||||
stmia r0, {r1-r13} |
||||
mov pc, lr |
@ -0,0 +1,57 @@ |
||||
/* |
||||
* (C) Copyright 2000-2004 |
||||
* Wolfgang Denk, DENX Software Engineering, wd@denx.de. |
||||
* |
||||
* See file CREDITS for list of people who contributed to this |
||||
* project. |
||||
* |
||||
* This program is free software; you can redistribute it and/or |
||||
* modify it under the terms of the GNU General Public License as |
||||
* published by the Free Software Foundation; either version 2 of |
||||
* the License, or (at your option) any later version. |
||||
* |
||||
* This program is distributed in the hope that it will be useful, |
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of |
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
||||
* GNU General Public License for more details. |
||||
* |
||||
* You should have received a copy of the GNU General Public License |
||||
* along with this program; if not, write to the Free Software |
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
||||
* MA 02111-1307 USA |
||||
*/ |
||||
|
||||
OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") |
||||
OUTPUT_ARCH(arm) |
||||
ENTRY(_start) |
||||
SECTIONS |
||||
{ |
||||
. = 0x00000000; |
||||
|
||||
. = ALIGN(4); |
||||
.text : |
||||
{ |
||||
cpu/s3c44b0/start.o (.text) |
||||
*(.text) |
||||
} |
||||
|
||||
. = ALIGN(4); |
||||
.rodata : { *(.rodata) } |
||||
|
||||
. = ALIGN(4); |
||||
.data : { *(.data) } |
||||
|
||||
. = ALIGN(4); |
||||
.got : { *(.got) } |
||||
|
||||
__u_boot_cmd_start = .; |
||||
.u_boot_cmd : { *(.u_boot_cmd) } |
||||
__u_boot_cmd_end = .; |
||||
|
||||
armboot_end_data = .; |
||||
|
||||
. = ALIGN(4); |
||||
.bss : { *(.bss) } |
||||
|
||||
armboot_end = .; |
||||
} |
@ -0,0 +1,43 @@ |
||||
#
|
||||
# (C) Copyright 2000-2004
|
||||
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
|
||||
#
|
||||
# See file CREDITS for list of people who contributed to this
|
||||
# project.
|
||||
#
|
||||
# This program is free software; you can redistribute it and/or
|
||||
# modify it under the terms of the GNU General Public License as
|
||||
# published by the Free Software Foundation; either version 2 of
|
||||
# the License, or (at your option) any later version.
|
||||
#
|
||||
# This program is distributed in the hope that it will be useful,
|
||||
# but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
# GNU General Public License for more details.
|
||||
#
|
||||
# You should have received a copy of the GNU General Public License
|
||||
# along with this program; if not, write to the Free Software
|
||||
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
# MA 02111-1307 USA
|
||||
#
|
||||
|
||||
include $(TOPDIR)/config.mk |
||||
|
||||
LIB = lib$(CPU).a
|
||||
|
||||
START = start.o
|
||||
OBJS = serial.o interrupts.o cpu.o
|
||||
|
||||
all: .depend $(START) $(LIB) |
||||
|
||||
$(LIB): $(OBJS) |
||||
$(AR) crv $@ $(OBJS)
|
||||
|
||||
#########################################################################
|
||||
|
||||
.depend: Makefile $(START:.o=.S) $(OBJS:.o=.c) |
||||
$(CC) -M $(CFLAGS) $(START:.o=.S) $(OBJS:.o=.c) > $@
|
||||
|
||||
sinclude .depend |
||||
|
||||
#########################################################################
|
@ -0,0 +1,28 @@ |
||||
#
|
||||
# (C) Copyright 2002
|
||||
# Sysgo Real-Time Solutions, GmbH <www.elinos.com>
|
||||
# Marius Groeger <mgroeger@sysgo.de>
|
||||
#
|
||||
# See file CREDITS for list of people who contributed to this
|
||||
# project.
|
||||
#
|
||||
# This program is free software; you can redistribute it and/or
|
||||
# modify it under the terms of the GNU General Public License as
|
||||
# published by the Free Software Foundation; either version 2 of
|
||||
# the License, or (at your option) any later version.
|
||||
#
|
||||
# This program is distributed in the hope that it will be useful,
|
||||
# but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
# GNU General Public License for more details.
|
||||
#
|
||||
# You should have received a copy of the GNU General Public License
|
||||
# along with this program; if not, write to the Free Software
|
||||
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
# MA 02111-1307 USA
|
||||
#
|
||||
|
||||
PLATFORM_RELFLAGS += -fno-strict-aliasing -fno-common -ffixed-r8 \
|
||||
-mshort-load-bytes -msoft-float
|
||||
|
||||
PLATFORM_CPPFLAGS += -mapcs-32 -march=armv4 -mtune=arm7tdmi -msoft-float
|
@ -0,0 +1,511 @@ |
||||
/*
|
||||
* (C) Copyright 2004 |
||||
* DAVE Srl |
||||
* http://www.dave-tech.it
|
||||
* http://www.wawnet.biz
|
||||
* mailto:info@wawnet.biz |
||||
* |
||||
* See file CREDITS for list of people who contributed to this |
||||
* project. |
||||
* |
||||
* This program is free software; you can redistribute it and/or |
||||
* modify it under the terms of the GNU General Public License as |
||||
* published by the Free Software Foundation; either version 2 of |
||||
* the License, or (at your option) any later version. |
||||
* |
||||
* This program is distributed in the hope that it will be useful, |
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of |
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
||||
* GNU General Public License for more details. |
||||
* |
||||
* You should have received a copy of the GNU General Public License |
||||
* along with this program; if not, write to the Free Software |
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
||||
* MA 02111-1307 USA |
||||
*/ |
||||
|
||||
/*
|
||||
* S3C44B0 CPU specific code |
||||
*/ |
||||
|
||||
#include <common.h> |
||||
#include <command.h> |
||||
#include <asm/hardware.h> |
||||
|
||||
static void s3c44b0_flush_cache(void) |
||||
{ |
||||
volatile int i; |
||||
/* flush cycle */ |
||||
for(i=0x10002000;i<0x10004800;i+=16) |
||||
{ |
||||
*((int *)i)=0x0; |
||||
} |
||||
} |
||||
|
||||
|
||||
int cpu_init (void) |
||||
{ |
||||
icache_enable(); |
||||
|
||||
return 0; |
||||
} |
||||
|
||||
int cleanup_before_linux (void) |
||||
{ |
||||
/*
|
||||
cache memory should be enabled before calling |
||||
Linux to make the kernel uncompression faster |
||||
*/ |
||||
icache_enable(); |
||||
|
||||
disable_interrupts (); |
||||
|
||||
return 0; |
||||
} |
||||
|
||||
void reset_cpu (ulong addr) |
||||
{ |
||||
/*
|
||||
reset the cpu using watchdog |
||||
*/ |
||||
|
||||
/* Disable the watchdog.*/ |
||||
WTCON&=~(1<<5); |
||||
|
||||
/* set the timeout value to a short time... */ |
||||
WTCNT = 0x1; |
||||
|
||||
/* Enable the watchdog. */ |
||||
WTCON|=1; |
||||
WTCON|=(1<<5); |
||||
|
||||
while(1) { |
||||
/*NOP*/ |
||||
} |
||||
} |
||||
|
||||
int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) |
||||
{ |
||||
extern void reset_cpu (ulong addr); |
||||
|
||||
disable_interrupts (); |
||||
reset_cpu (0); |
||||
|
||||
/*NOTREACHED*/ |
||||
return (0); |
||||
} |
||||
|
||||
void icache_enable (void) |
||||
{ |
||||
ulong reg; |
||||
|
||||
s3c44b0_flush_cache(); |
||||
|
||||
/*
|
||||
Init cache |
||||
Non-cacheable area (everything outside RAM) |
||||
0x0000:0000 - 0x0C00:0000 |
||||
*/ |
||||
NCACHBE0 = 0xC0000000; |
||||
NCACHBE1 = 0x00000000; |
||||
|
||||
/*
|
||||
Enable chache |
||||
*/ |
||||
reg = SYSCFG; |
||||
reg |= 0x00000006; /* 8kB */ |
||||
SYSCFG = reg; |
||||
} |
||||
|
||||
void icache_disable (void) |
||||
{ |
||||
ulong reg; |
||||
|
||||
reg = SYSCFG; |
||||
reg &= ~0x00000006; /* 8kB */ |
||||
SYSCFG = reg; |
||||
} |
||||
|
||||
int icache_status (void) |
||||
{ |
||||
return 0; |
||||
} |
||||
|
||||
void dcache_enable (void) |
||||
{ |
||||
icache_enable(); |
||||
} |
||||
|
||||
void dcache_disable (void) |
||||
{ |
||||
icache_disable(); |
||||
} |
||||
|
||||
int dcache_status (void) |
||||
{ |
||||
return dcache_status(); |
||||
} |
||||
|
||||
/*
|
||||
RTC stuff |
||||
*/ |
||||
#include <rtc.h> |
||||
#ifndef BCD2HEX |
||||
#define BCD2HEX(n) ((n>>4)*10+(n&0x0f)) |
||||
#endif |
||||
#ifndef HEX2BCD |
||||
#define HEX2BCD(x) ((((x) / 10) << 4) + (x) % 10) |
||||
#endif |
||||
|
||||
void rtc_get (struct rtc_time* tm) |
||||
{ |
||||
RTCCON |= 1; |
||||
tm->tm_year = BCD2HEX(BCDYEAR); |
||||
tm->tm_mon = BCD2HEX(BCDMON); |
||||
tm->tm_wday = BCD2HEX(BCDDATE); |
||||
tm->tm_mday = BCD2HEX(BCDDAY); |
||||
tm->tm_hour = BCD2HEX(BCDHOUR); |
||||
tm->tm_min = BCD2HEX(BCDMIN); |
||||
tm->tm_sec = BCD2HEX(BCDSEC); |
||||
|
||||
if (tm->tm_sec==0) { |
||||
/* we have to re-read the rtc data because of the "one second deviation" problem */ |
||||
/* see RTC datasheet for more info about it */ |
||||
tm->tm_year = BCD2HEX(BCDYEAR); |
||||
tm->tm_mon = BCD2HEX(BCDMON); |
||||
tm->tm_mday = BCD2HEX(BCDDAY); |
||||
tm->tm_wday = BCD2HEX(BCDDATE); |
||||
tm->tm_hour = BCD2HEX(BCDHOUR); |
||||
tm->tm_min = BCD2HEX(BCDMIN); |
||||
tm->tm_sec = BCD2HEX(BCDSEC); |
||||
} |
||||
|
||||
RTCCON &= ~1; |
||||
|
||||
if(tm->tm_year >= 70) |
||||
tm->tm_year += 1900; |
||||
else |
||||
tm->tm_year += 2000; |
||||
} |
||||
|
||||
void rtc_set (struct rtc_time* tm) |
||||
{ |
||||
if(tm->tm_year < 2000) |
||||
tm->tm_year -= 1900; |
||||
else |
||||
tm->tm_year -= 2000; |
||||
|
||||
RTCCON |= 1; |
||||
BCDYEAR = HEX2BCD(tm->tm_year); |
||||
BCDMON = HEX2BCD(tm->tm_mon); |
||||
BCDDAY = HEX2BCD(tm->tm_mday); |
||||
BCDDATE = HEX2BCD(tm->tm_wday); |
||||
BCDHOUR = HEX2BCD(tm->tm_hour); |
||||
BCDMIN = HEX2BCD(tm->tm_min); |
||||
BCDSEC = HEX2BCD(tm->tm_sec); |
||||
RTCCON &= 1; |
||||
} |
||||
|
||||
void rtc_reset (void) |
||||
{ |
||||
RTCCON |= 1; |
||||
BCDYEAR = 0; |
||||
BCDMON = 0; |
||||
BCDDAY = 0; |
||||
BCDDATE = 0; |
||||
BCDHOUR = 0; |
||||
BCDMIN = 0; |
||||
BCDSEC = 0; |
||||
RTCCON &= 1; |
||||
} |
||||
|
||||
|
||||
/*
|
||||
I2C stuff |
||||
*/ |
||||
|
||||
/*
|
||||
* Initialization, must be called once on start up, may be called |
||||
* repeatedly to change the speed and slave addresses. |
||||
*/ |
||||
void i2c_init(int speed, int slaveaddr) |
||||
{ |
||||
/*
|
||||
setting up I2C support |
||||
*/ |
||||
unsigned int save_F,save_PF,rIICCON,rPCONA,rPDATA,rPCONF,rPUPF; |
||||
|
||||
save_F = PCONF; |
||||
save_PF = PUPF; |
||||
|
||||
rPCONF = ((save_F & ~(0xF))| 0xa); |
||||
rPUPF = (save_PF | 0x3); |
||||
PCONF = rPCONF; /*PF0:IICSCL, PF1:IICSDA*/ |
||||
PUPF = rPUPF; /* Disable pull-up */ |
||||
|
||||
/* Configuring pin for WC pin of EEprom */ |
||||
rPCONA = PCONA; |
||||
rPCONA &= ~(1<<9); |
||||
PCONA = rPCONA; |
||||
|
||||
rPDATA = PDATA; |
||||
rPDATA &= ~(1<<9); |
||||
PDATA = rPDATA; |
||||
|
||||
/*
|
||||
Enable ACK, IICCLK=MCLK/16, enable interrupt |
||||
75Mhz/16/(12+1) = 390625 Hz |
||||
*/ |
||||
rIICCON=(1<<7)|(0<<6)|(1<<5)|(0xC); |
||||
IICCON = rIICCON; |
||||
|
||||
IICADD = slaveaddr; |
||||
} |
||||
|
||||
/*
|
||||
* Probe the given I2C chip address. Returns 0 if a chip responded, |
||||
* not 0 on failure. |
||||
*/ |
||||
int i2c_probe(uchar chip) |
||||
{ |
||||
/*
|
||||
not implemented |
||||
*/ |
||||
|
||||
printf(__FUNCTION__ " chip %d\n", (int) chip); |
||||
return -1; |
||||
} |
||||
|
||||
/*
|
||||
* Read/Write interface: |
||||
* chip: I2C chip address, range 0..127 |
||||
* addr: Memory (register) address within the chip |
||||
* alen: Number of bytes to use for addr (typically 1, 2 for larger |
||||
* memories, 0 for register type devices with only one |
||||
* register) |
||||
* buffer: Where to read/write the data |
||||
* len: How many bytes to read/write |
||||
* |
||||
* Returns: 0 on success, not 0 on failure |
||||
*/ |
||||
|
||||
#define S3C44B0X_rIIC_INTPEND (1<<4) |
||||
#define S3C44B0X_rIIC_LAST_RECEIV_BIT (1<<0) |
||||
#define S3C44B0X_rIIC_INTERRUPT_ENABLE (1<<5) |
||||
#define S3C44B0_IIC_TIMEOUT 100 |
||||
|
||||
int i2c_read(uchar chip, uint addr, int alen, uchar *buffer, int len) |
||||
{ |
||||
|
||||
int k, j, temp; |
||||
u32 rIICSTAT; |
||||
|
||||
/*
|
||||
send the device offset |
||||
*/ |
||||
|
||||
rIICSTAT = 0xD0; |
||||
IICSTAT = rIICSTAT; |
||||
|
||||
IICDS = chip; /* this is a write operation... */ |
||||
|
||||
rIICSTAT |= (1<<5); |
||||
IICSTAT = rIICSTAT; |
||||
|
||||
for(k=0; k<S3C44B0_IIC_TIMEOUT; k++) { |
||||
temp = IICCON; |
||||
if( (temp & S3C44B0X_rIIC_INTPEND) == S3C44B0X_rIIC_INTPEND) |
||||
break; |
||||
udelay(2000); |
||||
} |
||||
if (k==S3C44B0_IIC_TIMEOUT) |
||||
return -1; |
||||
|
||||
/* wait and check ACK */ |
||||
temp = IICSTAT; |
||||
if ((temp & S3C44B0X_rIIC_LAST_RECEIV_BIT) == S3C44B0X_rIIC_LAST_RECEIV_BIT ) |
||||
return -1; |
||||
|
||||
IICDS = addr; |
||||
IICCON = IICCON & ~(S3C44B0X_rIIC_INTPEND); |
||||
|
||||
/* wait and check ACK */ |
||||
for(k=0; k<S3C44B0_IIC_TIMEOUT; k++) { |
||||
temp = IICCON; |
||||
if( (temp & S3C44B0X_rIIC_INTPEND) == S3C44B0X_rIIC_INTPEND) |
||||
break; |
||||
udelay(2000); |
||||
} |
||||
if (k==S3C44B0_IIC_TIMEOUT) |
||||
return -1; |
||||
|
||||
temp = IICSTAT; |
||||
if ((temp & S3C44B0X_rIIC_LAST_RECEIV_BIT) == S3C44B0X_rIIC_LAST_RECEIV_BIT ) |
||||
return -1; |
||||
|
||||
/*
|
||||
now we can start with the read operation... |
||||
*/ |
||||
|
||||
IICDS = chip | 0x01; /* this is a read operation... */ |
||||
|
||||
rIICSTAT = 0x90; /*master recv*/ |
||||
rIICSTAT |= (1<<5); |
||||
IICSTAT = rIICSTAT; |
||||
|
||||
IICCON = IICCON & ~(S3C44B0X_rIIC_INTPEND); |
||||
|
||||
/* wait and check ACK */ |
||||
for(k=0; k<S3C44B0_IIC_TIMEOUT; k++) { |
||||
temp = IICCON; |
||||
if( (temp & S3C44B0X_rIIC_INTPEND) == S3C44B0X_rIIC_INTPEND) |
||||
break; |
||||
udelay(2000); |
||||
} |
||||
if (k==S3C44B0_IIC_TIMEOUT) |
||||
return -1; |
||||
|
||||
temp = IICSTAT; |
||||
if ((temp & S3C44B0X_rIIC_LAST_RECEIV_BIT) == S3C44B0X_rIIC_LAST_RECEIV_BIT ) |
||||
return -1; |
||||
|
||||
for (j=0; j<len-1; j++) { |
||||
|
||||
/*clear pending bit to resume */ |
||||
|
||||
temp = IICCON & ~(S3C44B0X_rIIC_INTPEND); |
||||
IICCON = temp; |
||||
|
||||
/* wait and check ACK */ |
||||
for(k=0; k<S3C44B0_IIC_TIMEOUT; k++) { |
||||
temp = IICCON; |
||||
if( (temp & S3C44B0X_rIIC_INTPEND) == S3C44B0X_rIIC_INTPEND) |
||||
break; |
||||
udelay(2000); |
||||
} |
||||
if (k==S3C44B0_IIC_TIMEOUT) |
||||
return -1; |
||||
|
||||
|
||||
buffer[j] = IICDS; /*save readed data*/ |
||||
|
||||
} /*end for(j)*/ |
||||
|
||||
/*
|
||||
reading the last data |
||||
unset ACK generation |
||||
*/ |
||||
temp = IICCON & ~(S3C44B0X_rIIC_INTPEND | (1<<7)); |
||||
IICCON = temp; |
||||
|
||||
/* wait but NOT check ACK */ |
||||
for(k=0; k<S3C44B0_IIC_TIMEOUT; k++) { |
||||
temp = IICCON; |
||||
if( (temp & S3C44B0X_rIIC_INTPEND) == S3C44B0X_rIIC_INTPEND) |
||||
break; |
||||
udelay(2000); |
||||
} |
||||
if (k==S3C44B0_IIC_TIMEOUT) |
||||
return -1; |
||||
|
||||
buffer[j] = IICDS; /*save readed data*/ |
||||
|
||||
rIICSTAT = 0x90; /*master recv*/ |
||||
|
||||
/* Write operation Terminate sending STOP */ |
||||
IICSTAT = rIICSTAT; |
||||
/*Clear Int Pending Bit to RESUME*/ |
||||
temp = IICCON; |
||||
IICCON = temp & (~S3C44B0X_rIIC_INTPEND); |
||||
|
||||
IICCON = IICCON | (1<<7); /*restore ACK generation*/ |
||||
|
||||
return 0; |
||||
} |
||||
|
||||
int i2c_write(uchar chip, uint addr, int alen, uchar *buffer, int len) |
||||
{ |
||||
int j, k; |
||||
u32 rIICSTAT, temp; |
||||
|
||||
|
||||
/*
|
||||
send the device offset |
||||
*/ |
||||
|
||||
rIICSTAT = 0xD0; |
||||
IICSTAT = rIICSTAT; |
||||
|
||||
IICDS = chip; /* this is a write operation... */ |
||||
|
||||
rIICSTAT |= (1<<5); |
||||
IICSTAT = rIICSTAT; |
||||
|
||||
IICCON = IICCON & ~(S3C44B0X_rIIC_INTPEND); |
||||
|
||||
/* wait and check ACK */ |
||||
for(k=0; k<S3C44B0_IIC_TIMEOUT; k++) { |
||||
temp = IICCON; |
||||
if( (temp & S3C44B0X_rIIC_INTPEND) == S3C44B0X_rIIC_INTPEND) |
||||
break; |
||||
udelay(2000); |
||||
} |
||||
if (k==S3C44B0_IIC_TIMEOUT) |
||||
return -1; |
||||
|
||||
temp = IICSTAT; |
||||
if ((temp & S3C44B0X_rIIC_LAST_RECEIV_BIT) == S3C44B0X_rIIC_LAST_RECEIV_BIT ) |
||||
return -1; |
||||
|
||||
IICDS = addr; |
||||
IICCON = IICCON & ~(S3C44B0X_rIIC_INTPEND); |
||||
|
||||
/* wait and check ACK */ |
||||
for(k=0; k<S3C44B0_IIC_TIMEOUT; k++) { |
||||
temp = IICCON; |
||||
if( (temp & S3C44B0X_rIIC_INTPEND) == S3C44B0X_rIIC_INTPEND) |
||||
break; |
||||
udelay(2000); |
||||
} |
||||
if (k==S3C44B0_IIC_TIMEOUT) |
||||
return -1; |
||||
|
||||
temp = IICSTAT; |
||||
if ((temp & S3C44B0X_rIIC_LAST_RECEIV_BIT) == S3C44B0X_rIIC_LAST_RECEIV_BIT ) |
||||
return -1; |
||||
|
||||
/*
|
||||
now we can start with the read write operation |
||||
*/ |
||||
for (j=0; j<len; j++) { |
||||
|
||||
IICDS = buffer[j]; /*prerare data to write*/ |
||||
|
||||
/*clear pending bit to resume*/ |
||||
|
||||
temp = IICCON & ~(S3C44B0X_rIIC_INTPEND); |
||||
IICCON = temp; |
||||
|
||||
/* wait but NOT check ACK */ |
||||
for(k=0; k<S3C44B0_IIC_TIMEOUT; k++) { |
||||
temp = IICCON; |
||||
if( (temp & S3C44B0X_rIIC_INTPEND) == S3C44B0X_rIIC_INTPEND) |
||||
break; |
||||
|
||||
udelay(2000); |
||||
} |
||||
|
||||
if (k==S3C44B0_IIC_TIMEOUT) |
||||
return -1; |
||||
|
||||
} /* end for(j) */ |
||||
|
||||
/* sending stop to terminate */ |
||||
rIICSTAT = 0xD0; /*master send*/ |
||||
IICSTAT = rIICSTAT; |
||||
/*Clear Int Pending Bit to RESUME*/ |
||||
temp = IICCON; |
||||
IICCON = temp & (~S3C44B0X_rIIC_INTPEND); |
||||
|
||||
return 0; |
||||
} |
@ -0,0 +1,235 @@ |
||||
/*
|
||||
* (C) Copyright 2004 |
||||
* DAVE Srl |
||||
* http://www.dave-tech.it
|
||||
* http://www.wawnet.biz
|
||||
* mailto:info@wawnet.biz |
||||
* |
||||
* See file CREDITS for list of people who contributed to this |
||||
* project. |
||||
* |
||||
* This program is free software; you can redistribute it and/or |
||||
* modify it under the terms of the GNU General Public License as |
||||
* published by the Free Software Foundation; either version 2 of |
||||
* the License, or (at your option) any later version. |
||||
* |
||||
* This program is distributed in the hope that it will be useful, |
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of |
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
||||
* GNU General Public License for more details. |
||||
* |
||||
* You should have received a copy of the GNU General Public License |
||||
* along with this program; if not, write to the Free Software |
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
||||
* MA 02111-1307 USA |
||||
*/ |
||||
|
||||
#include <common.h> |
||||
#include <asm/hardware.h> |
||||
|
||||
#include <asm/proc-armv/ptrace.h> |
||||
|
||||
extern void reset_cpu(ulong addr); |
||||
|
||||
/* we always count down the max. */ |
||||
#define TIMER_LOAD_VAL 0xffff |
||||
|
||||
/* macro to read the 16 bit timer */ |
||||
#define READ_TIMER (TCNTO1 & 0xffff) |
||||
|
||||
#ifdef CONFIG_USE_IRQ |
||||
#error CONFIG_USE_IRQ NOT supported |
||||
#else |
||||
void enable_interrupts (void) |
||||
{ |
||||
return; |
||||
} |
||||
int disable_interrupts (void) |
||||
{ |
||||
return 0; |
||||
} |
||||
#endif |
||||
|
||||
|
||||
void bad_mode (void) |
||||
{ |
||||
panic ("Resetting CPU ...\n"); |
||||
reset_cpu (0); |
||||
} |
||||
|
||||
void show_regs (struct pt_regs *regs) |
||||
{ |
||||
unsigned long flags; |
||||
const char *processor_modes[] = |
||||
{ "USER_26", "FIQ_26", "IRQ_26", "SVC_26", "UK4_26", "UK5_26", |
||||
"UK6_26", "UK7_26", |
||||
"UK8_26", "UK9_26", "UK10_26", "UK11_26", "UK12_26", "UK13_26", |
||||
"UK14_26", "UK15_26", |
||||
"USER_32", "FIQ_32", "IRQ_32", "SVC_32", "UK4_32", "UK5_32", |
||||
"UK6_32", "ABT_32", |
||||
"UK8_32", "UK9_32", "UK10_32", "UND_32", "UK12_32", "UK13_32", |
||||
"UK14_32", "SYS_32" |
||||
}; |
||||
|
||||
flags = condition_codes (regs); |
||||
|
||||
printf ("pc : [<%08lx>] lr : [<%08lx>]\n" |
||||
"sp : %08lx ip : %08lx fp : %08lx\n", |
||||
instruction_pointer (regs), |
||||
regs->ARM_lr, regs->ARM_sp, regs->ARM_ip, regs->ARM_fp); |
||||
printf ("r10: %08lx r9 : %08lx r8 : %08lx\n", |
||||
regs->ARM_r10, regs->ARM_r9, regs->ARM_r8); |
||||
printf ("r7 : %08lx r6 : %08lx r5 : %08lx r4 : %08lx\n", |
||||
regs->ARM_r7, regs->ARM_r6, regs->ARM_r5, regs->ARM_r4); |
||||
printf ("r3 : %08lx r2 : %08lx r1 : %08lx r0 : %08lx\n", |
||||
regs->ARM_r3, regs->ARM_r2, regs->ARM_r1, regs->ARM_r0); |
||||
printf ("Flags: %c%c%c%c", |
||||
flags & CC_N_BIT ? 'N' : 'n', |
||||
flags & CC_Z_BIT ? 'Z' : 'z', |
||||
flags & CC_C_BIT ? 'C' : 'c', flags & CC_V_BIT ? 'V' : 'v'); |
||||
printf (" IRQs %s FIQs %s Mode %s%s\n", |
||||
interrupts_enabled (regs) ? "on" : "off", |
||||
fast_interrupts_enabled (regs) ? "on" : "off", |
||||
processor_modes[processor_mode (regs)], |
||||
thumb_mode (regs) ? " (T)" : ""); |
||||
} |
||||
|
||||
void do_undefined_instruction (struct pt_regs *pt_regs) |
||||
{ |
||||
printf ("undefined instruction\n"); |
||||
show_regs (pt_regs); |
||||
bad_mode (); |
||||
} |
||||
|
||||
void do_software_interrupt (struct pt_regs *pt_regs) |
||||
{ |
||||
printf ("software interrupt\n"); |
||||
show_regs (pt_regs); |
||||
bad_mode (); |
||||
} |
||||
|
||||
void do_prefetch_abort (struct pt_regs *pt_regs) |
||||
{ |
||||
printf ("prefetch abort\n"); |
||||
show_regs (pt_regs); |
||||
bad_mode (); |
||||
} |
||||
|
||||
void do_data_abort (struct pt_regs *pt_regs) |
||||
{ |
||||
printf ("data abort\n"); |
||||
show_regs (pt_regs); |
||||
bad_mode (); |
||||
} |
||||
|
||||
void do_not_used (struct pt_regs *pt_regs) |
||||
{ |
||||
printf ("not used\n"); |
||||
show_regs (pt_regs); |
||||
bad_mode (); |
||||
} |
||||
|
||||
void do_fiq (struct pt_regs *pt_regs) |
||||
{ |
||||
printf ("fast interrupt request\n"); |
||||
show_regs (pt_regs); |
||||
bad_mode (); |
||||
} |
||||
|
||||
void do_irq (struct pt_regs *pt_regs) |
||||
{ |
||||
printf ("interrupt request\n"); |
||||
show_regs (pt_regs); |
||||
bad_mode (); |
||||
} |
||||
|
||||
static ulong timestamp; |
||||
static ulong lastdec; |
||||
|
||||
int interrupt_init (void) |
||||
{ |
||||
TCFG0 = 0x000000E9; |
||||
TCFG1 = 0x00000004; |
||||
TCON = 0x00000900; |
||||
TCNTB1 = TIMER_LOAD_VAL; |
||||
TCMPB1 = 0; |
||||
TCON = 0x00000B00; |
||||
TCON = 0x00000900; |
||||
|
||||
|
||||
lastdec = TCNTB1 = TIMER_LOAD_VAL; |
||||
timestamp = 0; |
||||
return 0; |
||||
} |
||||
|
||||
/*
|
||||
* timer without interrupts |
||||
*/ |
||||
|
||||
void reset_timer (void) |
||||
{ |
||||
reset_timer_masked (); |
||||
} |
||||
|
||||
ulong get_timer (ulong base) |
||||
{ |
||||
return get_timer_masked () - base; |
||||
} |
||||
|
||||
void set_timer (ulong t) |
||||
{ |
||||
timestamp = t; |
||||
} |
||||
|
||||
void udelay (unsigned long usec) |
||||
{ |
||||
ulong tmo; |
||||
|
||||
tmo = usec / 1000; |
||||
tmo *= CFG_HZ; |
||||
tmo /= 8; |
||||
|
||||
tmo += get_timer (0); |
||||
|
||||
while (get_timer_masked () < tmo) |
||||
/*NOP*/; |
||||
} |
||||
|
||||
void reset_timer_masked (void) |
||||
{ |
||||
/* reset time */ |
||||
lastdec = READ_TIMER; |
||||
timestamp = 0; |
||||
} |
||||
|
||||
ulong get_timer_masked (void) |
||||
{ |
||||
ulong now = READ_TIMER; |
||||
|
||||
if (lastdec >= now) { |
||||
/* normal mode */ |
||||
timestamp += lastdec - now; |
||||
} else { |
||||
/* we have an overflow ... */ |
||||
timestamp += lastdec + TIMER_LOAD_VAL - now; |
||||
} |
||||
lastdec = now; |
||||
|
||||
return timestamp; |
||||
} |
||||
|
||||
void udelay_masked (unsigned long usec) |
||||
{ |
||||
ulong tmo; |
||||
|
||||
tmo = usec / 1000; |
||||
tmo *= CFG_HZ; |
||||
tmo /= 8; |
||||
|
||||
tmo += get_timer (0); |
||||
|
||||
reset_timer_masked (); |
||||
|
||||
while (get_timer_masked () < tmo) |
||||
/*NOP*/; |
||||
} |
@ -0,0 +1,218 @@ |
||||
/*
|
||||
* (C) Copyright 2004 |
||||
* DAVE Srl |
||||
* http://www.dave-tech.it
|
||||
* http://www.wawnet.biz
|
||||
* mailto:info@wawnet.biz |
||||
* |
||||
* (C) Copyright 2002-2004 |
||||
* Wolfgang Denk, DENX Software Engineering, <wd@denx.de> |
||||
* |
||||
* (C) Copyright 2002 |
||||
* Sysgo Real-Time Solutions, GmbH <www.elinos.com> |
||||
* Marius Groeger <mgroeger@sysgo.de> |
||||
* |
||||
* (C) Copyright 2002 |
||||
* Sysgo Real-Time Solutions, GmbH <www.elinos.com> |
||||
* Alex Zuepke <azu@sysgo.de> |
||||
* |
||||
* Copyright (C) 1999 2000 2001 Erik Mouw (J.A.K.Mouw@its.tudelft.nl) |
||||
* |
||||
* This program is free software; you can redistribute it and/or modify |
||||
* it under the terms of the GNU General Public License as published by |
||||
* the Free Software Foundation; either version 2 of the License, or |
||||
* (at your option) any later version. |
||||
* |
||||
* This program is distributed in the hope that it will be useful, |
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of |
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
||||
* GNU General Public License for more details. |
||||
* |
||||
* You should have received a copy of the GNU General Public License |
||||
* along with this program; if not, write to the Free Software |
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA |
||||
* |
||||
*/ |
||||
|
||||
#include <common.h> |
||||
#include <asm/hardware.h> |
||||
|
||||
/* flush serial input queue. returns 0 on success or negative error
|
||||
* number otherwise |
||||
*/ |
||||
static int serial_flush_input(void) |
||||
{ |
||||
volatile u32 tmp; |
||||
|
||||
/* keep on reading as long as the receiver is not empty */ |
||||
while(UTRSTAT0&0x01) { |
||||
tmp = REGB(URXH0); |
||||
} |
||||
|
||||
return 0; |
||||
} |
||||
|
||||
|
||||
/* flush output queue. returns 0 on success or negative error number
|
||||
* otherwise |
||||
*/ |
||||
static int serial_flush_output(void) |
||||
{ |
||||
/* wait until the transmitter is no longer busy */ |
||||
while(!(UTRSTAT0 & 0x02)) { |
||||
} |
||||
|
||||
return 0; |
||||
} |
||||
|
||||
|
||||
void serial_setbrg (void) |
||||
{ |
||||
DECLARE_GLOBAL_DATA_PTR; |
||||
|
||||
u32 divisor = 0; |
||||
|
||||
/* get correct divisor */ |
||||
switch(gd->baudrate) { |
||||
|
||||
case 1200: |
||||
#if CONFIG_S3C44B0_CLOCK_SPEED==66 |
||||
divisor = 3124; |
||||
#elif CONFIG_S3C44B0_CLOCK_SPEED==75 |
||||
divisor = 3905; |
||||
#else |
||||
# error CONFIG_S3C44B0_CLOCK_SPEED undefined |
||||
#endif |
||||
break; |
||||
|
||||
case 9600: |
||||
#if CONFIG_S3C44B0_CLOCK_SPEED==66 |
||||
divisor = 390; |
||||
#elif CONFIG_S3C44B0_CLOCK_SPEED==75 |
||||
divisor = 487; |
||||
#else |
||||
# error CONFIG_S3C44B0_CLOCK_SPEED undefined |
||||
#endif |
||||
break; |
||||
|
||||
case 19200: |
||||
#if CONFIG_S3C44B0_CLOCK_SPEED==66 |
||||
divisor = 194; |
||||
#elif CONFIG_S3C44B0_CLOCK_SPEED==75 |
||||
divisor = 243; |
||||
#else |
||||
# error CONFIG_S3C44B0_CLOCK_SPEED undefined |
||||
#endif |
||||
break; |
||||
|
||||
case 38400: |
||||
#if CONFIG_S3C44B0_CLOCK_SPEED==66 |
||||
divisor = 97; |
||||
#elif CONFIG_S3C44B0_CLOCK_SPEED==75 |
||||
divisor = 121; |
||||
#else |
||||
# error CONFIG_S3C44B0_CLOCK_SPEED undefined |
||||
#endif break; |
||||
|
||||
case 57600: |
||||
#if CONFIG_S3C44B0_CLOCK_SPEED==66 |
||||
divisor = 64; |
||||
#elif CONFIG_S3C44B0_CLOCK_SPEED==75 |
||||
divisor = 80; |
||||
#else |
||||
# error CONFIG_S3C44B0_CLOCK_SPEED undefined |
||||
#endif break; |
||||
|
||||
case 115200: |
||||
#if CONFIG_S3C44B0_CLOCK_SPEED==66 |
||||
divisor = 32; |
||||
#elif CONFIG_S3C44B0_CLOCK_SPEED==75 |
||||
divisor = 40; |
||||
#else |
||||
# error CONFIG_S3C44B0_CLOCK_SPEED undefined |
||||
#endif break; |
||||
} |
||||
|
||||
serial_flush_output(); |
||||
serial_flush_input(); |
||||
UFCON0 = 0x0; |
||||
ULCON0 = 0x03; |
||||
UCON0 = 0x05; |
||||
UBRDIV0 = divisor; |
||||
|
||||
UFCON1 = 0x0; |
||||
ULCON1 = 0x03; |
||||
UCON1 = 0x05; |
||||
UBRDIV1 = divisor; |
||||
|
||||
for(divisor=0; divisor<100; divisor++) { |
||||
/* NOP */ |
||||
} |
||||
} |
||||
|
||||
|
||||
/*
|
||||
* Initialise the serial port with the given baudrate. The settings |
||||
* are always 8 data bits, no parity, 1 stop bit, no start bits. |
||||
* |
||||
*/ |
||||
int serial_init (void) |
||||
{ |
||||
serial_setbrg (); |
||||
|
||||
return (0); |
||||
} |
||||
|
||||
|
||||
/*
|
||||
* Output a single byte to the serial port. |
||||
*/ |
||||
void serial_putc (const char c) |
||||
{ |
||||
/* wait for room in the transmit FIFO */ |
||||
while(!(UTRSTAT0 & 0x02)); |
||||
|
||||
UTXH0 = (unsigned char)c; |
||||
|
||||
/*
|
||||
to be polite with serial console add a line feed |
||||
to the carriage return character |
||||
*/ |
||||
if (c=='\n') |
||||
serial_putc('\r'); |
||||
} |
||||
|
||||
/*
|
||||
* Read a single byte from the serial port. Returns 1 on success, 0 |
||||
* otherwise. When the function is succesfull, the character read is |
||||
* written into its argument c. |
||||
*/ |
||||
int serial_tstc (void) |
||||
{ |
||||
return (UTRSTAT0 & 0x01); |
||||
} |
||||
|
||||
/*
|
||||
* Read a single byte from the serial port. Returns 1 on success, 0 |
||||
* otherwise. When the function is succesfull, the character read is |
||||
* written into its argument c. |
||||
*/ |
||||
int serial_getc (void) |
||||
{ |
||||
int rv; |
||||
|
||||
for(;;) { |
||||
rv = serial_tstc(); |
||||
|
||||
if(rv > 0) |
||||
return URXH0; |
||||
} |
||||
} |
||||
|
||||
void |
||||
serial_puts (const char *s) |
||||
{ |
||||
while (*s) { |
||||
serial_putc (*s++); |
||||
} |
||||
} |
@ -0,0 +1,271 @@ |
||||
/* |
||||
* Startup Code for S3C44B0 CPU-core |
||||
* |
||||
* (C) Copyright 2004 |
||||
* DAVE Srl |
||||
* |
||||
* http://www.dave-tech.it |
||||
* http://www.wawnet.biz |
||||
* mailto:info@wawnet.biz
|
||||
* |
||||
* See file CREDITS for list of people who contributed to this |
||||
* project. |
||||
* |
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as |
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version. |
||||
* |
||||
* This program is distributed in the hope that it will be useful, |
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
||||
* GNU General Public License for more details. |
||||
* |
||||
* You should have received a copy of the GNU General Public License |
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
||||
* MA 02111-1307 USA |
||||
*/ |
||||
|
||||
|
||||
#include <config.h> |
||||
#include <version.h> |
||||
|
||||
|
||||
/* |
||||
* Jump vector table |
||||
*/ |
||||
|
||||
|
||||
.globl _start
|
||||
_start: b reset |
||||
add pc, pc, #0x0c000000 |
||||
add pc, pc, #0x0c000000 |
||||
add pc, pc, #0x0c000000 |
||||
add pc, pc, #0x0c000000 |
||||
add pc, pc, #0x0c000000 |
||||
add pc, pc, #0x0c000000 |
||||
add pc, pc, #0x0c000000 |
||||
|
||||
.balignl 16,0xdeadbeef |
||||
|
||||
|
||||
/* |
||||
************************************************************************* |
||||
* |
||||
* Startup Code (reset vector) |
||||
* |
||||
* do important init only if we don't start from memory! |
||||
* relocate u-boot to ram |
||||
* setup stack |
||||
* jump to second stage |
||||
* |
||||
************************************************************************* |
||||
*/ |
||||
|
||||
_TEXT_BASE: |
||||
.word TEXT_BASE
|
||||
|
||||
.globl _armboot_start
|
||||
_armboot_start: |
||||
.word _start
|
||||
|
||||
/* |
||||
* Note: _armboot_end_data and _armboot_end are defined |
||||
* by the (board-dependent) linker script. |
||||
* _armboot_end_data is the first usable FLASH address after armboot |
||||
*/ |
||||
.globl _armboot_end_data
|
||||
_armboot_end_data: |
||||
.word armboot_end_data
|
||||
.globl _armboot_end
|
||||
_armboot_end: |
||||
.word armboot_end
|
||||
|
||||
#ifdef CONFIG_USE_IRQ |
||||
/* IRQ stack memory (calculated at run-time) */ |
||||
.globl IRQ_STACK_START
|
||||
IRQ_STACK_START: |
||||
.word 0x0badc0de
|
||||
|
||||
/* IRQ stack memory (calculated at run-time) */ |
||||
.globl FIQ_STACK_START
|
||||
FIQ_STACK_START: |
||||
.word 0x0badc0de
|
||||
#endif |
||||
|
||||
|
||||
/* |
||||
* the actual reset code |
||||
*/ |
||||
|
||||
reset: |
||||
/* |
||||
* set the cpu to SVC32 mode |
||||
*/ |
||||
mrs r0,cpsr |
||||
bic r0,r0,#0x1f |
||||
orr r0,r0,#0x13 |
||||
msr cpsr,r0 |
||||
|
||||
/* |
||||
* we do sys-critical inits only at reboot, |
||||
* not when booting from ram! |
||||
*/ |
||||
|
||||
#ifdef CONFIG_INIT_CRITICAL |
||||
bl cpu_init_crit |
||||
/* |
||||
* before relocating, we have to setup RAM timing |
||||
* because memory timing is board-dependend, you will |
||||
* find a memsetup.S in your board directory. |
||||
*/ |
||||
bl memsetup |
||||
#endif |
||||
|
||||
relocate: /* relocate U-Boot to RAM */ |
||||
adr r0, _start /* r0 <- current position of code */ |
||||
ldr r1, _TEXT_BASE /* test if we run from flash or RAM */ |
||||
cmp r0, r1 /* don't reloc during debug */ |
||||
beq stack_setup |
||||
|
||||
ldr r2, _armboot_start |
||||
ldr r3, _armboot_end |
||||
sub r2, r3, r2 /* r2 <- size of armboot */ |
||||
add r2, r0, r2 /* r2 <- source end address */ |
||||
|
||||
copy_loop: |
||||
ldmia r0!, {r3-r10} /* copy from source address [r0] */ |
||||
stmia r1!, {r3-r10} /* copy to target address [r1] */ |
||||
cmp r0, r2 /* until source end addreee [r2] */ |
||||
ble copy_loop |
||||
|
||||
/* |
||||
now copy to sram the interrupt vector |
||||
*/ |
||||
adr r0, real_vectors |
||||
add r2, r0, #1024 |
||||
ldr r1, =0x0c000000 |
||||
add r1, r1, #0x08 |
||||
vector_copy_loop: |
||||
ldmia r0!, {r3-r10} |
||||
stmia r1!, {r3-r10} |
||||
cmp r0, r2 |
||||
ble vector_copy_loop |
||||
|
||||
/* Set up the stack */ |
||||
stack_setup: |
||||
ldr r0, _TEXT_BASE /* upper 128 KiB: relocated uboot */ |
||||
sub r0, r0, #CFG_MALLOC_LEN /* malloc area */ |
||||
sub r0, r0, #CFG_GBL_DATA_SIZE /* bdinfo */ |
||||
#ifdef CONFIG_USE_IRQ |
||||
sub r0, r0, #(CONFIG_STACKSIZE_IRQ+CONFIG_STACKSIZE_FIQ) |
||||
#endif |
||||
sub sp, r0, #12 /* leave 3 words for abort-stack */ |
||||
|
||||
ldr pc, _start_armboot |
||||
|
||||
_start_armboot: .word start_armboot |
||||
|
||||
|
||||
/* |
||||
************************************************************************* |
||||
* |
||||
* CPU_init_critical registers |
||||
* |
||||
* setup important registers |
||||
* setup memory timing |
||||
* |
||||
************************************************************************* |
||||
*/ |
||||
|
||||
#define INTCON (0x01c00000+0x200000) |
||||
#define INTMSK (0x01c00000+0x20000c) |
||||
#define LOCKTIME (0x01c00000+0x18000c) |
||||
#define PLLCON (0x01c00000+0x180000) |
||||
#define CLKCON (0x01c00000+0x180004) |
||||
#define WTCON (0x01c00000+0x130000) |
||||
cpu_init_crit: |
||||
/* disable watch dog */ |
||||
ldr r0, =WTCON |
||||
ldr r1, =0x0 |
||||
str r1, [r0] |
||||
|
||||
/* |
||||
* mask all IRQs by clearing all bits in the INTMRs |
||||
*/ |
||||
ldr r1,=INTMSK |
||||
ldr r0, =0x03fffeff |
||||
str r0, [r1] |
||||
|
||||
ldr r1, =INTCON |
||||
ldr r0, =0x05 |
||||
str r0, [r1] |
||||
|
||||
/* Set Clock Control Register */ |
||||
ldr r1, =LOCKTIME |
||||
ldrb r0, =800 |
||||
strb r0, [r1] |
||||
|
||||
ldr r1, =PLLCON |
||||
|
||||
#if CONFIG_S3C44B0_CLOCK_SPEED==66 |
||||
ldr r0, =0x34031 /* 66MHz (Quartz=11MHz) */ |
||||
#elif CONFIG_S3C44B0_CLOCK_SPEED==75 |
||||
ldr r0, =0x610c1 /*B2: Xtal=20mhz Fclk=75MHz */ |
||||
#else |
||||
# error CONFIG_S3C44B0_CLOCK_SPEED undefined |
||||
#endif |
||||
|
||||
str r0, [r1] |
||||
|
||||
ldr r1,=CLKCON |
||||
ldr r0, =0x7ff8 |
||||
str r0, [r1] |
||||
|
||||
mov pc, lr |
||||
|
||||
|
||||
/*************************************************/ |
||||
/* interrupt vectors */ |
||||
/*************************************************/ |
||||
real_vectors: |
||||
b reset |
||||
b undefined_instruction |
||||
b software_interrupt |
||||
b prefetch_abort |
||||
b data_abort |
||||
b not_used |
||||
b irq |
||||
b fiq |
||||
|
||||
/*************************************************/ |
||||
|
||||
undefined_instruction: |
||||
mov r6, #3 |
||||
b reset |
||||
|
||||
software_interrupt: |
||||
mov r6, #4 |
||||
b reset |
||||
|
||||
prefetch_abort: |
||||
mov r6, #5 |
||||
b reset |
||||
|
||||
data_abort: |
||||
mov r6, #6 |
||||
b reset |
||||
|
||||
not_used: |
||||
/* we *should* never reach this */ |
||||
mov r6, #7 |
||||
b reset |
||||
|
||||
irq: |
||||
mov r6, #8 |
||||
b reset |
||||
|
||||
fiq: |
||||
mov r6, #9 |
||||
b reset |
@ -0,0 +1,281 @@ |
||||
/********************************************************/ |
||||
/* */ |
||||
/* Samsung S3C44B0 */ |
||||
/* tpu <tapu@371.net> */ |
||||
/* */ |
||||
/********************************************************/ |
||||
#ifndef __ASM_ARCH_HARDWARE_H |
||||
#define __ASM_ARCH_HARDWARE_H |
||||
|
||||
#define REGBASE 0x01c00000 |
||||
#define REGL(addr) (*(volatile unsigned int *)(REGBASE+addr)) |
||||
#define REGW(addr) (*(volatile unsigned short *)(REGBASE+addr)) |
||||
#define REGB(addr) (*(volatile unsigned char *)(REGBASE+addr)) |
||||
|
||||
|
||||
/*****************************/ |
||||
/* CPU Wrapper Registers */ |
||||
/*****************************/ |
||||
|
||||
#define SYSCFG REGL(0x000000) |
||||
#define NCACHBE0 REGL(0x000004) |
||||
#define NCACHBE1 REGL(0x000008) |
||||
#define SBUSCON REGL(0x040000) |
||||
|
||||
/************************************/ |
||||
/* Memory Controller Registers */ |
||||
/************************************/ |
||||
|
||||
#define BWSCON REGL(0x080000) |
||||
#define BANKCON0 REGL(0x080004) |
||||
#define BANKCON1 REGL(0x080008) |
||||
#define BANKCON2 REGL(0x08000c) |
||||
#define BANKCON3 REGL(0x080010) |
||||
#define BANKCON4 REGL(0x080014) |
||||
#define BANKCON5 REGL(0x080018) |
||||
#define BANKCON6 REGL(0x08001c) |
||||
#define BANKCON7 REGL(0x080020) |
||||
#define REFRESH REGL(0x080024) |
||||
#define BANKSIZE REGL(0x080028) |
||||
#define MRSRB6 REGL(0x08002c) |
||||
#define MRSRB7 REGL(0x080030) |
||||
|
||||
/*********************/ |
||||
/* UART Registers */ |
||||
/*********************/ |
||||
|
||||
#define ULCON0 REGL(0x100000) |
||||
#define ULCON1 REGL(0x104000) |
||||
#define UCON0 REGL(0x100004) |
||||
#define UCON1 REGL(0x104004) |
||||
#define UFCON0 REGL(0x100008) |
||||
#define UFCON1 REGL(0x104008) |
||||
#define UMCON0 REGL(0x10000c) |
||||
#define UMCON1 REGL(0x10400c) |
||||
#define UTRSTAT0 REGL(0x100010) |
||||
#define UTRSTAT1 REGL(0x104010) |
||||
#define UERSTAT0 REGL(0x100014) |
||||
#define UERSTAT1 REGL(0x104014) |
||||
#define UFSTAT0 REGL(0x100018) |
||||
#define UFSTAT1 REGL(0x104018) |
||||
#define UMSTAT0 REGL(0x10001c) |
||||
#define UMSTAT1 REGL(0x10401c) |
||||
#define UTXH0 REGB(0x100020) |
||||
#define UTXH1 REGB(0x104020) |
||||
#define URXH0 REGB(0x100024) |
||||
#define URXH1 REGB(0x104024) |
||||
#define UBRDIV0 REGL(0x100028) |
||||
#define UBRDIV1 REGL(0x104028) |
||||
|
||||
/*******************/ |
||||
/* SIO Registers */ |
||||
/*******************/ |
||||
|
||||
#define SIOCON REGL(0x114000) |
||||
#define SIODAT REGL(0x114004) |
||||
#define SBRDR REGL(0x114008) |
||||
#define ITVCNT REGL(0x11400c) |
||||
#define DCNTZ REGL(0x114010) |
||||
|
||||
/********************/ |
||||
/* IIS Registers */ |
||||
/********************/ |
||||
|
||||
#define IISCON REGL(0x118000) |
||||
#define IISMOD REGL(0x118004) |
||||
#define IISPSR REGL(0x118008) |
||||
#define IISFIFCON REGL(0x11800c) |
||||
#define IISFIF REGW(0x118010) |
||||
|
||||
/**************************/ |
||||
/* I/O Ports Registers */ |
||||
/**************************/ |
||||
|
||||
#define PCONA REGL(0x120000) |
||||
#define PDATA REGL(0x120004) |
||||
#define PCONB REGL(0x120008) |
||||
#define PDATB REGL(0x12000c) |
||||
#define PCONC REGL(0x120010) |
||||
#define PDATC REGL(0x120014) |
||||
#define PUPC REGL(0x120018) |
||||
#define PCOND REGL(0x12001c) |
||||
#define PDATD REGL(0x120020) |
||||
#define PUPD REGL(0x120024) |
||||
#define PCONE REGL(0x120028) |
||||
#define PDATE REGL(0x12002c) |
||||
#define PUPE REGL(0x120030) |
||||
#define PCONF REGL(0x120034) |
||||
#define PDATF REGL(0x120038) |
||||
#define PUPF REGL(0x12003c) |
||||
#define PCONG REGL(0x120040) |
||||
#define PDATG REGL(0x120044) |
||||
#define PUPG REGL(0x120048) |
||||
#define SPUCR REGL(0x12004c) |
||||
#define EXTINT REGL(0x120050) |
||||
#define EXTINTPND REGL(0x120054) |
||||
|
||||
/*********************************/ |
||||
/* WatchDog Timers Registers */ |
||||
/*********************************/ |
||||
|
||||
#define WTCON REGL(0x130000) |
||||
#define WTDAT REGL(0x130004) |
||||
#define WTCNT REGL(0x130008) |
||||
|
||||
/*********************************/ |
||||
/* A/D Converter Registers */ |
||||
/*********************************/ |
||||
|
||||
#define ADCCON REGL(0x140000) |
||||
#define ADCPSR REGL(0x140004) |
||||
#define ADCDAT REGL(0x140008) |
||||
|
||||
/***************************/ |
||||
/* PWM Timer Registers */ |
||||
/***************************/ |
||||
|
||||
#define TCFG0 REGL(0x150000) |
||||
#define TCFG1 REGL(0x150004) |
||||
#define TCON REGL(0x150008) |
||||
#define TCNTB0 REGL(0x15000c) |
||||
#define TCMPB0 REGL(0x150010) |
||||
#define TCNTO0 REGL(0x150014) |
||||
#define TCNTB1 REGL(0x150018) |
||||
#define TCMPB1 REGL(0x15001c) |
||||
#define TCNTO1 REGL(0x150020) |
||||
#define TCNTB2 REGL(0x150024) |
||||
#define TCMPB2 REGL(0x150028) |
||||
#define TCNTO2 REGL(0x15002c) |
||||
#define TCNTB3 REGL(0x150030) |
||||
#define TCMPB3 REGL(0x150034) |
||||
#define TCNTO3 REGL(0x150038) |
||||
#define TCNTB4 REGL(0x15003c) |
||||
#define TCMPB4 REGL(0x150040) |
||||
#define TCNTO4 REGL(0x150044) |
||||
#define TCNTB5 REGL(0x150048) |
||||
#define TCNTO5 REGL(0x15004c) |
||||
|
||||
/*********************/ |
||||
/* IIC Registers */ |
||||
/*********************/ |
||||
|
||||
#define IICCON REGL(0x160000) |
||||
#define IICSTAT REGL(0x160004) |
||||
#define IICADD REGL(0x160008) |
||||
#define IICDS REGL(0x16000c) |
||||
|
||||
/*********************/ |
||||
/* RTC Registers */ |
||||
/*********************/ |
||||
|
||||
#define RTCCON REGB(0x170040) |
||||
#define RTCALM REGB(0x170050) |
||||
#define ALMSEC REGB(0x170054) |
||||
#define ALMMIN REGB(0x170058) |
||||
#define ALMHOUR REGB(0x17005c) |
||||
#define ALMDAY REGB(0x170060) |
||||
#define ALMMON REGB(0x170064) |
||||
#define ALMYEAR REGB(0x170068) |
||||
#define RTCRST REGB(0x17006c) |
||||
#define BCDSEC REGB(0x170070) |
||||
#define BCDMIN REGB(0x170074) |
||||
#define BCDHOUR REGB(0x170078) |
||||
#define BCDDAY REGB(0x17007c) |
||||
#define BCDDATE REGB(0x170080) |
||||
#define BCDMON REGB(0x170084) |
||||
#define BCDYEAR REGB(0x170088) |
||||
#define TICINT REGB(0x17008c) |
||||
|
||||
/*********************************/ |
||||
/* Clock & Power Registers */ |
||||
/*********************************/ |
||||
|
||||
#define PLLCON REGL(0x180000) |
||||
#define CLKCON REGL(0x180004) |
||||
#define CLKSLOW REGL(0x180008) |
||||
#define LOCKTIME REGL(0x18000c) |
||||
|
||||
/**************************************/ |
||||
/* Interrupt Controller Registers */ |
||||
/**************************************/ |
||||
|
||||
#define INTCON REGL(0x200000) |
||||
#define INTPND REGL(0x200004) |
||||
#define INTMOD REGL(0x200008) |
||||
#define INTMSK REGL(0x20000c) |
||||
#define I_PSLV REGL(0x200010) |
||||
#define I_PMST REGL(0x200014) |
||||
#define I_CSLV REGL(0x200018) |
||||
#define I_CMST REGL(0x20001c) |
||||
#define I_ISPR REGL(0x200020) |
||||
#define I_ISPC REGL(0x200024) |
||||
#define F_ISPR REGL(0x200038) |
||||
#define F_ISPC REGL(0x20003c) |
||||
|
||||
/********************************/ |
||||
/* LCD Controller Registers */ |
||||
/********************************/ |
||||
|
||||
#define LCDCON1 REGL(0x300000) |
||||
#define LCDCON2 REGL(0x300004) |
||||
#define LCDSADDR1 REGL(0x300008) |
||||
#define LCDSADDR2 REGL(0x30000c) |
||||
#define LCDSADDR3 REGL(0x300010) |
||||
#define REDLUT REGL(0x300014) |
||||
#define GREENLUT REGL(0x300018) |
||||
#define BLUELUT REGL(0x30001c) |
||||
#define DP1_2 REGL(0x300020) |
||||
#define DP4_7 REGL(0x300024) |
||||
#define DP3_5 REGL(0x300028) |
||||
#define DP2_3 REGL(0x30002c) |
||||
#define DP5_7 REGL(0x300030) |
||||
#define DP3_4 REGL(0x300034) |
||||
#define DP4_5 REGL(0x300038) |
||||
#define DP6_7 REGL(0x30003c) |
||||
#define LCDCON3 REGL(0x300040) |
||||
#define DITHMODE REGL(0x300044) |
||||
|
||||
/*********************/ |
||||
/* DMA Registers */ |
||||
/*********************/ |
||||
|
||||
#define ZDCON0 REGL(0x280000) |
||||
#define ZDISRC0 REGL(0x280004) |
||||
#define ZDIDES0 REGL(0x280008) |
||||
#define ZDICNT0 REGL(0x28000c) |
||||
#define ZDCSRC0 REGL(0x280010) |
||||
#define ZDCDES0 REGL(0x280014) |
||||
#define ZDCCNT0 REGL(0x280018) |
||||
|
||||
#define ZDCON1 REGL(0x280020) |
||||
#define ZDISRC1 REGL(0x280024) |
||||
#define ZDIDES1 REGL(0x280028) |
||||
#define ZDICNT1 REGL(0x28002c) |
||||
#define ZDCSRC1 REGL(0x280030) |
||||
#define ZDCDES1 REGL(0x280034) |
||||
#define ZDCCNT1 REGL(0x280038) |
||||
|
||||
#define BDCON0 REGL(0x380000) |
||||
#define BDISRC0 REGL(0x380004) |
||||
#define BDIDES0 REGL(0x380008) |
||||
#define BDICNT0 REGL(0x38000c) |
||||
#define BDCSRC0 REGL(0x380010) |
||||
#define BDCDES0 REGL(0x380014) |
||||
#define BDCCNT0 REGL(0x380018) |
||||
|
||||
#define BDCON1 REGL(0x380020) |
||||
#define BDISRC1 REGL(0x380024) |
||||
#define BDIDES1 REGL(0x380028) |
||||
#define BDICNT1 REGL(0x38002c) |
||||
#define BDCSRC1 REGL(0x380030) |
||||
#define BDCDES1 REGL(0x380034) |
||||
#define BDCCNT1 REGL(0x380038) |
||||
|
||||
|
||||
#define CLEAR_PEND_INT(n) I_ISPC = (1<<(n)) |
||||
#define INT_ENABLE(n) INTMSK &= ~(1<<(n)) |
||||
#define INT_DISABLE(n) INTMSK |= (1<<(n)) |
||||
|
||||
#define HARD_RESET_NOW() |
||||
|
||||
#endif /* __ASM_ARCH_HARDWARE_H */ |
@ -0,0 +1,209 @@ |
||||
/*
|
||||
* (C) Copyright 2004 |
||||
* DAVE Srl |
||||
* |
||||
* http://www.dave-tech.it
|
||||
* http://www.wawnet.biz
|
||||
* mailto:info@wawnet.biz |
||||
* |
||||
* Configuation settings for the B2 board. |
||||
* |
||||
* See file CREDITS for list of people who contributed to this |
||||
* project. |
||||
* |
||||
* This program is free software; you can redistribute it and/or |
||||
* modify it under the terms of the GNU General Public License as |
||||
* published by the Free Software Foundation; either version 2 of |
||||
* the License, or (at your option) any later version. |
||||
* |
||||
* This program is distributed in the hope that it will be useful, |
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of |
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
||||
* GNU General Public License for more details. |
||||
* |
||||
* You should have received a copy of the GNU General Public License |
||||
* along with this program; if not, write to the Free Software |
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
||||
* MA 02111-1307 USA |
||||
*/ |
||||
|
||||
#ifndef __CONFIG_H |
||||
#define __CONFIG_H |
||||
|
||||
/*
|
||||
* If we are developing, we might want to start armboot from ram |
||||
* so we MUST NOT initialize critical regs like mem-timing ... |
||||
*/ |
||||
#define CONFIG_INIT_CRITICAL /* undef for developing */ |
||||
|
||||
/*
|
||||
* High Level Configuration Options |
||||
* (easy to change) |
||||
*/ |
||||
#define CONFIG_ARM7 1 /* This is a ARM7 CPU */ |
||||
#define CONFIG_B2 1 /* on an B2 Board */ |
||||
#define CONFIG_ARM_THUMB 1 /* this is an ARM7TDMI */ |
||||
#undef CONFIG_ARM7_REVD /* disable ARM720 REV.D Workarounds */ |
||||
|
||||
#define CONFIG_S3C44B0_CLOCK_SPEED 75 /* we have a 75Mhz S3C44B0*/ |
||||
|
||||
|
||||
#undef CONFIG_USE_IRQ /* don't need them anymore */ |
||||
|
||||
|
||||
/*
|
||||
* Size of malloc() pool |
||||
*/ |
||||
#define CFG_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Monitor */ |
||||
#define CFG_ENV_SIZE 1024 /* 1024 bytes may be used for env vars*/ |
||||
#define CFG_MALLOC_LEN (CFG_ENV_SIZE + 128*1024 ) |
||||
#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */ |
||||
|
||||
/*
|
||||
* Hardware drivers |
||||
*/ |
||||
#define CONFIG_DRIVER_LAN91C96 |
||||
#define CONFIG_LAN91C96_BASE 0x04000300 /* base address */ |
||||
#define CONFIG_SMC_USE_32_BIT |
||||
#undef CONFIG_SHOW_ACTIVITY |
||||
#define CONFIG_NET_RETRY_COUNT 10 /* # of retries */ |
||||
|
||||
/*
|
||||
* select serial console configuration |
||||
*/ |
||||
#define CONFIG_SERIAL1 1 /* we use Serial line 1 */ |
||||
|
||||
/* allow to overwrite serial and ethaddr */ |
||||
#define CONFIG_ENV_OVERWRITE |
||||
|
||||
#define CONFIG_BAUDRATE 115200 |
||||
|
||||
#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT|CONFIG_BOOTP_BOOTFILESIZE) |
||||
|
||||
#define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \ |
||||
CFG_CMD_DATE | \
|
||||
CFG_CMD_ELF | \
|
||||
CFG_CMD_EEPROM | \
|
||||
CFG_CMD_I2C ) |
||||
|
||||
/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ |
||||
#include <cmd_confdefs.h> |
||||
|
||||
#define CONFIG_BOOTDELAY 5 |
||||
#define CONFIG_ETHADDR 00:50:c2:1e:af:fb |
||||
#define CONFIG_BOOTARGS "setenv bootargs root=/dev/ram ip=192.168.0.70:::::eth0:off \ |
||||
ether=25,0,0,0,eth0 ethaddr=00:50:c2:1e:af:fb" |
||||
#define CONFIG_NETMASK 255.255.0.0 |
||||
#define CONFIG_IPADDR 192.168.0.70 |
||||
#define CONFIG_SERVERIP 192.168.0.23 |
||||
#define CONFIG_BOOTFILE "B2-rootfs/usr/B2-zImage.u-boot" |
||||
#define CONFIG_BOOTCOMMAND "bootm 20000 f0000" |
||||
|
||||
/*
|
||||
* Miscellaneous configurable options |
||||
*/ |
||||
#define CFG_LONGHELP /* undef to save memory */ |
||||
#define CFG_PROMPT "=> " /* Monitor Command Prompt */ |
||||
#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ |
||||
#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ |
||||
#define CFG_MAXARGS 16 /* max number of command args */ |
||||
#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ |
||||
|
||||
#define CFG_MEMTEST_START 0x0C400000 /* memtest works on */ |
||||
#define CFG_MEMTEST_END 0x0C800000 /* 4 ... 8 MB in DRAM */ |
||||
|
||||
#undef CFG_CLKS_IN_HZ /* everything, incl board info, in Hz */ |
||||
|
||||
#define CFG_LOAD_ADDR 0x0c700000 /* default load address */ |
||||
|
||||
#define CFG_HZ 1000 /* 1 kHz */ |
||||
|
||||
/* valid baudrates */ |
||||
#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Stack sizes |
||||
* |
||||
* The stack sizes are set up in start.S using the settings below |
||||
*/ |
||||
#define CONFIG_STACKSIZE (128*1024) /* regular stack */ |
||||
#ifdef CONFIG_USE_IRQ |
||||
#define CONFIG_STACKSIZE_IRQ (4*1024) /* IRQ stack */ |
||||
#define CONFIG_STACKSIZE_FIQ (4*1024) /* FIQ stack */ |
||||
#endif |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Physical Memory Map |
||||
*/ |
||||
#define CONFIG_NR_DRAM_BANKS 1 /* we have 1 banks of DRAM */ |
||||
#define PHYS_SDRAM_1 0xc0000000 /* SDRAM Bank #1 */ |
||||
#define PHYS_SDRAM_1_SIZE 0x01000000 /* 16 MB */ |
||||
|
||||
#define PHYS_FLASH_1 0x00000000 /* Flash Bank #1 */ |
||||
#define PHYS_FLASH_SIZE 0x00400000 /* 4 MB */ |
||||
|
||||
#define CFG_FLASH_BASE PHYS_FLASH_1 |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* FLASH and environment organization |
||||
*/ |
||||
/*-----------------------------------------------------------------------
|
||||
* FLASH organization |
||||
*/ |
||||
#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */ |
||||
#define CFG_MAX_FLASH_SECT 256 /* max number of sectors on one chip */ |
||||
|
||||
#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ |
||||
#define CFG_FLASH_WRITE_TOUT 1000 /* Timeout for Flash Write (in ms) */ |
||||
|
||||
#define CFG_FLASH_WORD_SIZE unsigned short /* flash word size (width) */ |
||||
#define CFG_FLASH_ADDR0 0x5555 /* 1st address for flash config cycles */ |
||||
#define CFG_FLASH_ADDR1 0x2AAA /* 2nd address for flash config cycles */ |
||||
/*
|
||||
* The following defines are added for buggy IOP480 byte interface. |
||||
* All other boards should use the standard values (CPCI405 etc.) |
||||
*/ |
||||
#define CFG_FLASH_READ0 0x0000 /* 0 is standard */ |
||||
#define CFG_FLASH_READ1 0x0001 /* 1 is standard */ |
||||
#define CFG_FLASH_READ2 0x0002 /* 2 is standard */ |
||||
|
||||
#define CFG_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */ |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Environment Variable setup |
||||
*/ |
||||
#define CFG_ENV_IS_IN_EEPROM 1 /* use EEPROM for environment vars */ |
||||
#define CFG_ENV_OFFSET 0x0 /* environment starts at the beginning of the EEPROM */ |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* I2C EEPROM (STM24C02W6) for environment |
||||
*/ |
||||
#define CONFIG_HARD_I2C /* I2c with hardware support */ |
||||
#define CFG_I2C_SPEED 400000 /* I2C speed and slave address */ |
||||
#define CFG_I2C_SLAVE 0xFE |
||||
|
||||
#define CFG_I2C_EEPROM_ADDR 0xA8 /* EEPROM STM24C02W6 */ |
||||
#define CFG_I2C_EEPROM_ADDR_LEN 1 /* Bytes of address */ |
||||
/* mask of address bits that overflow into the "EEPROM chip address" */ |
||||
/*#define CFG_I2C_EEPROM_ADDR_OVERFLOW 0x07*/ |
||||
#define CFG_EEPROM_PAGE_WRITE_BITS 4 /* The Catalyst CAT24WC08 has */ |
||||
/* 16 byte page write mode using*/ |
||||
/* last 4 bits of the address */ |
||||
#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */ |
||||
#define CFG_EEPROM_PAGE_WRITE_ENABLE |
||||
|
||||
/* Flash banks JFFS2 should use */ |
||||
/*
|
||||
#define CFG_JFFS2_FIRST_BANK 0 |
||||
#define CFG_JFFS2_FIRST_SECTOR 2 |
||||
#define CFG_JFFS2_NUM_BANKS 1 |
||||
*/ |
||||
|
||||
/*
|
||||
Linux TAGs (see lib_arm/armlinux.c) |
||||
*/ |
||||
#define CONFIG_CMDLINE_TAG |
||||
#undef CONFIG_SETUP_MEMORY_TAGS |
||||
#define CONFIG_INITRD_TAG |
||||
|
||||
#endif /* __CONFIG_H */ |
Loading…
Reference in new issue