@ -41,11 +41,8 @@ struct crlapb_regs {
# define crlapb_base ((struct crlapb_regs *)ZYNQMP_CRL_APB_BASEADDR)
# if defined(CONFIG_SECURE_IOU)
# define ZYNQMP_IOU_SCNTR 0xFF260000
# else
# define ZYNQMP_IOU_SCNTR_SECURE 0xFF260000
# define ZYNQMP_IOU_SCNTR 0xFF250000
# endif
# define ZYNQMP_IOU_SCNTR_COUNTER_CONTROL_REGISTER_EN 0x1
# define ZYNQMP_IOU_SCNTR_COUNTER_CONTROL_REGISTER_HDBG 0x2
@ -57,6 +54,14 @@ struct iou_scntr {
# define iou_scntr ((struct iou_scntr *)ZYNQMP_IOU_SCNTR)
struct iou_scntr_secure {
u32 counter_control_register ;
u32 reserved0 [ 7 ] ;
u32 base_frequency_id_register ;
} ;
# define iou_scntr_secure ((struct iou_scntr_secure *)ZYNQMP_IOU_SCNTR_SECURE)
/* Bootmode setting values */
# define BOOT_MODES_MASK 0x0000000F
# define SD_MODE 0x00000003
@ -106,9 +111,20 @@ struct apu_regs {
# define apu_base ((struct apu_regs *)ZYNQMP_APU_BASEADDR)
/* Board version value */
# define ZYNQMP_CSU_BASEADDR 0xFFCA0000
# define ZYNQMP_CSU_VERSION_SILICON 0x0
# define ZYNQMP_CSU_VERSION_EP108 0x1
# define ZYNQMP_CSU_VERSION_VELOCE 0x2
# define ZYNQMP_CSU_VERSION_QEMU 0x3
# define ZYNQMP_SILICON_VER_MASK 0xF000
# define ZYNQMP_SILICON_VER_SHIFT 12
struct csu_regs {
u32 reserved0 [ 17 ] ;
u32 version ;
} ;
# define csu_base ((struct csu_regs *)ZYNQMP_CSU_BASEADDR)
# endif /* _ASM_ARCH_HARDWARE_H */