20 years ago
parent
f1340e2273
commit
0841565cc7
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#
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# (C) Copyright 2005
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# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
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#
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# See file CREDITS for list of people who contributed to this
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# project.
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#
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# This program is free software; you can redistribute it and/or
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# modify it under the terms of the GNU General Public License as
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# published by the Free Software Foundation; either version 2 of
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# the License, or (at your option) any later version.
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#
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# This program is distributed in the hope that it will be useful,
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# but WITHOUT ANY WARRANTY; without even the implied warranty of
|
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# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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# GNU General Public License for more details.
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#
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# You should have received a copy of the GNU General Public License
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# along with this program; if not, write to the Free Software
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# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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# MA 02111-1307 USA
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#
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include $(TOPDIR)/config.mk |
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LIB = lib$(BOARD).a
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OBJS := $(BOARD).o flash.o
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$(LIB): $(OBJS) $(SOBJS) |
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$(AR) crv $@ $(OBJS)
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clean: |
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rm -f $(SOBJS) $(OBJS)
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distclean: clean |
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rm -f $(LIB) core *.bak .depend
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#########################################################################
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.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) |
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$(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
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-include .depend |
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#########################################################################
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@ -0,0 +1,27 @@ |
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#
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# (C) Copyright 2005
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# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
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#
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# See file CREDITS for list of people who contributed to this
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# project.
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#
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# This program is free software; you can redistribute it and/or
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# modify it under the terms of the GNU General Public License as
|
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# published by the Free Software Foundation; either version 2 of
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# the License, or (at your option) any later version.
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#
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# This program is distributed in the hope that it will be useful,
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# but WITHOUT ANY WARRANTY; without even the implied warranty of
|
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# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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# GNU General Public License for more details.
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#
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# You should have received a copy of the GNU General Public License
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# along with this program; if not, write to the Free Software
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# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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# MA 02111-1307 USA
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#
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# boot low for 16 MiB boards
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TEXT_BASE = 0xFF000000
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PLATFORM_CPPFLAGS += -DTEXT_BASE=$(TEXT_BASE) -I$(TOPDIR)/board
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@ -0,0 +1,423 @@ |
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/*
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* (C) Copyright 2005 |
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* Wolfgang Denk, DENX Software Engineering, wd@denx.de. |
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* |
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* See file CREDITS for list of people who contributed to this |
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* project. |
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* |
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* This program is free software; you can redistribute it and/or |
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* modify it under the terms of the GNU General Public License as |
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* published by the Free Software Foundation; either version 2 of |
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* the License, or (at your option) any later version. |
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* |
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* This program is distributed in the hope that it will be useful, |
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* but WITHOUT ANY WARRANTY; without even the implied warranty of |
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
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* GNU General Public License for more details. |
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* |
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* You should have received a copy of the GNU General Public License |
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* along with this program; if not, write to the Free Software |
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
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* MA 02111-1307 USA |
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*/ |
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#include <common.h> |
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flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */ |
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/* NOTE - CONFIG_FLASH_16BIT means the CPU interface is 16-bit, it
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* has nothing to do with the flash chip being 8-bit or 16-bit. |
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*/ |
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#ifdef CONFIG_FLASH_16BIT |
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typedef unsigned short FLASH_PORT_WIDTH; |
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typedef volatile unsigned short FLASH_PORT_WIDTHV; |
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#define FLASH_ID_MASK 0xFFFF |
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#else |
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typedef unsigned char FLASH_PORT_WIDTH; |
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typedef volatile unsigned char FLASH_PORT_WIDTHV; |
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#define FLASH_ID_MASK 0xFF |
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#endif |
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#define FPW FLASH_PORT_WIDTH |
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#define FPWV FLASH_PORT_WIDTHV |
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#define ORMASK(size) ((-size) & OR_AM_MSK) |
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#define FLASH_CYCLE1 0x0555 |
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#define FLASH_CYCLE2 0x02aa |
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/*-----------------------------------------------------------------------
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* Functions |
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*/ |
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static ulong flash_get_size(FPWV *addr, flash_info_t *info); |
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static void flash_reset(flash_info_t *info); |
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static flash_info_t *flash_get_info(ulong base); |
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static int write_data (flash_info_t *info, FPWV *dest, FPW data); /* O2D */ |
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/*-----------------------------------------------------------------------
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* flash_init() |
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* |
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* sets up flash_info and returns size of FLASH (bytes) |
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*/ |
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unsigned long flash_init (void) |
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{ |
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unsigned long size = 0; |
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int i; |
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extern void flash_preinit(void); |
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extern void flash_afterinit(ulong); |
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flash_preinit(); |
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/* Init: no FLASHes known */ |
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for (i = 0; i < CFG_MAX_FLASH_BANKS; ++i) { |
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memset(&flash_info[i], 0, sizeof(flash_info_t)); |
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flash_info[i].flash_id = FLASH_UNKNOWN; |
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} |
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/* Query flash chip */ |
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flash_info[0].size = |
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flash_get_size((FPW *)CFG_FLASH_BASE, &flash_info[0]); |
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size += flash_info[0].size; |
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#if CFG_MONITOR_BASE >= CFG_FLASH_BASE |
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/* monitor protection ON by default */ |
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flash_protect(FLAG_PROTECT_SET, |
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CFG_MONITOR_BASE, |
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CFG_MONITOR_BASE+monitor_flash_len-1, |
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flash_get_info(CFG_MONITOR_BASE)); |
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#endif |
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#ifdef CFG_ENV_IS_IN_FLASH |
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/* ENV protection ON by default */ |
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flash_protect(FLAG_PROTECT_SET, |
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CFG_ENV_ADDR, |
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CFG_ENV_ADDR+CFG_ENV_SIZE-1, |
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flash_get_info(CFG_ENV_ADDR)); |
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#endif |
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flash_afterinit(size); |
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return (size ? size : 1); |
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} |
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/*-----------------------------------------------------------------------
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*/ |
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static void flash_reset(flash_info_t *info) |
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{ |
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FPWV *base = (FPWV *)(info->start[0]); |
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/* Put FLASH back in read mode */ |
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if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_INTEL) |
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*base = (FPW)0x00FF00FF; /* Intel Read Mode */ |
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} |
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/*-----------------------------------------------------------------------
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*/ |
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static flash_info_t *flash_get_info(ulong base) |
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{ |
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int i; |
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flash_info_t * info; |
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for (i = 0; i < CFG_MAX_FLASH_BANKS; i ++) { |
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info = & flash_info[i]; |
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if (info->size && |
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info->start[0] <= base && |
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base <= info->start[0] + info->size - 1) |
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break; |
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} |
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return (i == CFG_MAX_FLASH_BANKS ? 0 : info); |
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} |
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/*-----------------------------------------------------------------------
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*/ |
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void flash_print_info (flash_info_t *info) |
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{ |
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int i; |
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uchar *boottype; |
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uchar *bootletter; |
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uchar *fmt; |
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uchar botbootletter[] = "B"; |
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uchar topbootletter[] = "T"; |
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uchar botboottype[] = "bottom boot sector"; |
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uchar topboottype[] = "top boot sector"; |
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if (info->flash_id == FLASH_UNKNOWN) { |
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printf ("missing or unknown FLASH type\n"); |
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return; |
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} |
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switch (info->flash_id & FLASH_VENDMASK) { |
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case FLASH_MAN_INTEL: |
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printf ("INTEL "); |
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break; |
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default: |
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printf ("Unknown Vendor "); |
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break; |
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} |
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/* check for top or bottom boot, if it applies */ |
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if (info->flash_id & FLASH_BTYPE) { |
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boottype = botboottype; |
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bootletter = botbootletter; |
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} else { |
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boottype = topboottype; |
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bootletter = topbootletter; |
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} |
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switch (info->flash_id & FLASH_TYPEMASK) { |
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case FLASH_28F128J3A: |
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fmt = "28F128J3 (128 Mbit, uniform sectors)\n"; |
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break; |
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default: |
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fmt = "Unknown Chip Type\n"; |
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break; |
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} |
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printf (fmt, bootletter, boottype); |
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printf (" Size: %ld MB in %d Sectors\n", |
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info->size >> 20, |
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info->sector_count); |
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printf (" Sector Start Addresses:"); |
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for (i=0; i<info->sector_count; ++i) { |
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if ((i % 5) == 0) |
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printf ("\n "); |
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printf (" %08lX%s", info->start[i], |
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info->protect[i] ? " (RO)" : " "); |
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} |
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printf ("\n"); |
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} |
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/*-----------------------------------------------------------------------
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*/ |
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/*
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* The following code cannot be run from FLASH! |
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*/ |
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ulong flash_get_size (FPWV *addr, flash_info_t *info) |
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{ |
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int i; |
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/* Write auto select command: read Manufacturer ID */ |
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/* Write auto select command sequence and test FLASH answer */ |
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addr[FLASH_CYCLE1] = (FPW)0x00900090; /* selects Intel or AMD */ |
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/* The manufacturer codes are only 1 byte, so just use 1 byte.
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* This works for any bus width and any FLASH device width. |
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*/ |
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udelay(100); |
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switch (addr[0] & 0xff) { |
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case (uchar)INTEL_MANUFACT: |
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info->flash_id = FLASH_MAN_INTEL; |
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break; |
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default: |
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info->flash_id = FLASH_UNKNOWN; |
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info->sector_count = 0; |
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info->size = 0; |
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break; |
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} |
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/* Strataflash is configurable to 8/16bit Bus,
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* but the Query-Structure is Word-orientated */ |
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if (info->flash_id != FLASH_UNKNOWN) { |
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switch ((FPW)addr[2]) { |
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case (FPW)INTEL_ID_28F128J3: |
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info->flash_id += FLASH_28F128J3A; |
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info->sector_count = 128; |
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info->size = 0x01000000; |
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for( i = 0; i < info->sector_count; i++ ) |
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info->start[i] = (ulong)addr + (i * 0x20000); |
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break; /* => Intel Strataflash 16MB */ |
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default: |
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printf("Flash_id != %xd\n", (FPW)addr[2]); |
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info->flash_id = FLASH_UNKNOWN; |
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info->sector_count = 0; |
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info->size = 0; |
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return (0); /* => no or unknown flash */ |
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} |
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} |
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/* Put FLASH back in read mode */ |
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flash_reset(info); |
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return (info->size); |
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} |
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/*-----------------------------------------------------------------------
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*/ |
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int flash_erase (flash_info_t *info, int s_first, int s_last) |
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{ |
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FPWV *addr; |
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int flag, prot, sect; |
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ulong start, now, last; |
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int rcode = 0; |
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if ((s_first < 0) || (s_first > s_last)) { |
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if (info->flash_id == FLASH_UNKNOWN) { |
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printf ("- missing\n"); |
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} else { |
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printf ("- no sectors to erase\n"); |
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} |
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return 1; |
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} |
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switch (info->flash_id & FLASH_TYPEMASK) { |
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case FLASH_28F128J3A: |
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break; |
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case FLASH_UNKNOWN: |
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default: |
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printf ("Can't erase unknown flash type %08lx - aborted\n", |
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info->flash_id); |
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return 1; |
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} |
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prot = 0; |
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for (sect = s_first; sect <= s_last; ++sect) |
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if (info->protect[sect]) |
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prot++; |
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if (prot) |
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printf ("- Warning: %d protected sectors will not be erased!", |
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prot); |
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printf ("\n"); |
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last = get_timer(0); |
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/* Start erase on unprotected sectors */ |
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for (sect = s_first; sect <= s_last && rcode == 0; sect++) { |
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if (info->protect[sect] != 0) /* protected, skip it */ |
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continue; |
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/* Disable interrupts which might cause a timeout here */ |
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flag = disable_interrupts(); |
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addr = (FPWV *)(info->start[sect]); |
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*addr = (FPW)0x00500050; /* clear status register */ |
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*addr = (FPW)0x00200020; /* erase setup */ |
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*addr = (FPW)0x00D000D0; /* erase confirm */ |
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/* re-enable interrupts if necessary */ |
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if (flag) |
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enable_interrupts(); |
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start = get_timer(0); |
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/* wait at least 80us for Intel - let's wait 1 ms */ |
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udelay (1000); |
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while ((*addr & (FPW)0x00800080) != (FPW)0x00800080) { |
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if ((now = get_timer(start)) > CFG_FLASH_ERASE_TOUT) { |
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printf ("Timeout\n"); |
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*addr = (FPW)0x00B000B0;/* suspend erase */ |
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flash_reset(info); /* reset to read mode */ |
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rcode = 1; /* failed */ |
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break; |
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} |
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/* show that we're waiting */ |
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if ((get_timer(last)) > CFG_HZ) { /* every second */ |
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putc ('.'); |
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last = get_timer(0); |
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} |
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} |
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flash_reset(info); /* reset to read mode */ |
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} |
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printf (" done\n"); |
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return rcode; |
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} |
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/*-----------------------------------------------------------------------
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* Copy memory to flash, returns: |
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* 0 - OK |
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* 1 - write timeout |
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* 2 - Flash not erased |
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*/ |
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int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt) |
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{ |
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FPW data = 0; /* 16 or 32 bit word, matches flash bus width on MPC8XX */ |
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int bytes; /* number of bytes to program in current word */ |
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int left; /* number of bytes left to program */ |
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int i, res; |
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for (left = cnt, res = 0; |
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left > 0 && res == 0; |
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addr += sizeof(data), left -= sizeof(data) - bytes) { |
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bytes = addr & (sizeof(data) - 1); |
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addr &= ~(sizeof(data) - 1); |
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/* combine source and destination data so can program
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* an entire word of 16 or 32 bits */ |
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for (i = 0; i < sizeof(data); i++) { |
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data <<= 8; |
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if (i < bytes || i - bytes >= left ) |
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data += *((uchar *)addr + i); |
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else |
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data += *src++; |
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} |
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|
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/* write one word to the flash */ |
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switch (info->flash_id & FLASH_VENDMASK) { |
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case FLASH_MAN_INTEL: |
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res = write_data(info, (FPWV *)addr, data); |
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break; |
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default: |
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/* unknown flash type, error! */ |
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printf ("missing or unknown FLASH type\n"); |
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res = 1; /* not really a timeout, but gives error */ |
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break; |
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} |
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} |
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return (res); |
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} |
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|
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/*-----------------------------------------------------------------------
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* Write a word or halfword to Flash, returns: |
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* 0 - OK |
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* 1 - write timeout |
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* 2 - Flash not erased |
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*/ |
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static int write_data (flash_info_t *info, FPWV *dest, FPW data) |
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{ |
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FPWV *addr = dest; |
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ulong status; |
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ulong start; |
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int flag; |
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|
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/* Check if Flash is (sufficiently) erased */ |
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if ((*addr & data) != data) { |
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printf ("not erased at %08lx (%lx)\n", (ulong) addr, *addr); |
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return (2); |
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} |
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/* Disable interrupts which might cause a timeout here */ |
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flag = disable_interrupts (); |
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|
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*addr = (FPW) 0x00400040; /* write setup */ |
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*addr = data; |
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|
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/* arm simple, non interrupt dependent timer */ |
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start = get_timer(0); |
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|
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/* wait while polling the status register */ |
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while (((status = *addr) & (FPW) 0x00800080) != (FPW) 0x00800080) { |
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if (get_timer(start) > CFG_FLASH_WRITE_TOUT) { |
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*addr = (FPW) 0x00FF00FF; /* restore read mode */ |
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return (1); |
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} |
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} |
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*addr = (FPW) 0x00FF00FF; /* restore read mode */ |
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if (flag) |
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enable_interrupts(); |
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return (0); |
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} |
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@ -0,0 +1,182 @@ |
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/*
|
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* (C) Copyright 2005 |
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* Wolfgang Denk, DENX Software Engineering, wd@denx.de. |
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* |
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* (C) Copyright 2004 |
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* Mark Jonas, Freescale Semiconductor, mark.jonas@motorola.com. |
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* |
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* See file CREDITS for list of people who contributed to this |
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* project. |
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* |
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* This program is free software; you can redistribute it and/or |
||||
* modify it under the terms of the GNU General Public License as |
||||
* published by the Free Software Foundation; either version 2 of |
||||
* the License, or (at your option) any later version. |
||||
* |
||||
* This program is distributed in the hope that it will be useful, |
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of |
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
||||
* GNU General Public License for more details. |
||||
* |
||||
* You should have received a copy of the GNU General Public License |
||||
* along with this program; if not, write to the Free Software |
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
||||
* MA 02111-1307 USA |
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*/ |
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|
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#include <common.h> |
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#include <mpc5xxx.h> |
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#include <pci.h> |
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|
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#define SDRAM_MODE 0x00CD0000 |
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#define SDRAM_CONTROL 0x504F0000 |
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#define SDRAM_CONFIG1 0xD2322800 |
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#define SDRAM_CONFIG2 0x8AD70000 |
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|
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static void sdram_start (int hi_addr) |
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{ |
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long hi_addr_bit = hi_addr ? 0x01000000 : 0; |
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|
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/* unlock mode register */ |
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*(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000000 | hi_addr_bit; |
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__asm__ volatile ("sync"); |
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|
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/* precharge all banks */ |
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*(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000002 | hi_addr_bit; |
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__asm__ volatile ("sync"); |
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|
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/* precharge all banks */ |
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*(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000002 | hi_addr_bit; |
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__asm__ volatile ("sync"); |
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|
||||
/* auto refresh */ |
||||
*(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000004 | hi_addr_bit; |
||||
__asm__ volatile ("sync"); |
||||
|
||||
/* set mode register */ |
||||
*(vu_long *)MPC5XXX_SDRAM_MODE = SDRAM_MODE; |
||||
__asm__ volatile ("sync"); |
||||
|
||||
/* normal operation */ |
||||
*(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | hi_addr_bit; |
||||
__asm__ volatile ("sync"); |
||||
} |
||||
|
||||
/*
|
||||
* ATTENTION: Although partially referenced initdram does NOT make real use |
||||
* use of CFG_SDRAM_BASE. The code does not work if CFG_SDRAM_BASE |
||||
* is something else than 0x00000000. |
||||
*/ |
||||
long int initdram (int board_type) |
||||
{ |
||||
ulong dramsize = 0; |
||||
ulong dramsize2 = 0; |
||||
ulong test1, test2; |
||||
|
||||
/* setup SDRAM chip selects */ |
||||
*(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0x0000001e;/* 2G at 0x0 */ |
||||
*(vu_long *)MPC5XXX_SDRAM_CS1CFG = 0x80000000;/* disabled */ |
||||
__asm__ volatile ("sync"); |
||||
|
||||
/* setup config registers */ |
||||
*(vu_long *)MPC5XXX_SDRAM_CONFIG1 = SDRAM_CONFIG1; |
||||
*(vu_long *)MPC5XXX_SDRAM_CONFIG2 = SDRAM_CONFIG2; |
||||
__asm__ volatile ("sync"); |
||||
|
||||
/* find RAM size using SDRAM CS0 only */ |
||||
sdram_start(0); |
||||
test1 = get_ram_size((ulong *)CFG_SDRAM_BASE, 0x80000000); |
||||
sdram_start(1); |
||||
test2 = get_ram_size((ulong *)CFG_SDRAM_BASE, 0x80000000); |
||||
if (test1 > test2) { |
||||
sdram_start(0); |
||||
dramsize = test1; |
||||
} else { |
||||
dramsize = test2; |
||||
} |
||||
|
||||
/* memory smaller than 1MB is impossible */ |
||||
if (dramsize < (1 << 20)) { |
||||
dramsize = 0; |
||||
} |
||||
|
||||
/* set SDRAM CS0 size according to the amount of RAM found */ |
||||
if (dramsize > 0) |
||||
*(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0x13 + __builtin_ffs(dramsize >> 20) - 1; |
||||
else |
||||
*(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0; /* disabled */ |
||||
|
||||
/* let SDRAM CS1 start right after CS0 */ |
||||
*(vu_long *)MPC5XXX_SDRAM_CS1CFG = dramsize + 0x0000001e;/* 2G */ |
||||
|
||||
/* find RAM size using SDRAM CS1 only */ |
||||
if (!dramsize) |
||||
sdram_start(0); |
||||
|
||||
test2 = test1 = get_ram_size((ulong *)(CFG_SDRAM_BASE + dramsize), 0x80000000); |
||||
|
||||
if (!dramsize) { |
||||
sdram_start(1); |
||||
test2 = get_ram_size((ulong *)(CFG_SDRAM_BASE + dramsize), 0x80000000); |
||||
} |
||||
|
||||
if (test1 > test2) { |
||||
sdram_start(0); |
||||
dramsize2 = test1; |
||||
} else { |
||||
dramsize2 = test2; |
||||
} |
||||
|
||||
/* memory smaller than 1MB is impossible */ |
||||
if (dramsize2 < (1 << 20)) |
||||
dramsize2 = 0; |
||||
|
||||
/* set SDRAM CS1 size according to the amount of RAM found */ |
||||
if (dramsize2 > 0) { |
||||
*(vu_long *)MPC5XXX_SDRAM_CS1CFG = dramsize |
||||
| (0x13 + __builtin_ffs(dramsize2 >> 20) - 1); |
||||
} else { |
||||
*(vu_long *)MPC5XXX_SDRAM_CS1CFG = dramsize; /* disabled */ |
||||
} |
||||
|
||||
return dramsize + dramsize2; |
||||
} |
||||
|
||||
int checkboard (void) |
||||
{ |
||||
puts ("Board: O2DNT\n"); |
||||
return 0; |
||||
} |
||||
|
||||
void flash_preinit(void) |
||||
{ |
||||
/*
|
||||
* Now, when we are in RAM, enable flash write |
||||
* access for detection process. |
||||
* Note that CS_BOOT cannot be cleared when |
||||
* executing in flash. |
||||
*/ |
||||
*(vu_long *)MPC5XXX_BOOTCS_CFG &= ~0x1; /* clear RO */ |
||||
} |
||||
|
||||
void flash_afterinit(ulong size) |
||||
{ |
||||
if (size == 0x800000) { /* adjust mapping */ |
||||
*(vu_long *)MPC5XXX_BOOTCS_START = *(vu_long *)MPC5XXX_CS0_START = |
||||
START_REG(CFG_BOOTCS_START | size); |
||||
|
||||
*(vu_long *)MPC5XXX_BOOTCS_STOP = *(vu_long *)MPC5XXX_CS0_STOP = |
||||
STOP_REG(CFG_BOOTCS_START | size, size); |
||||
} |
||||
} |
||||
|
||||
#ifdef CONFIG_PCI |
||||
static struct pci_controller hose; |
||||
|
||||
extern void pci_mpc5xxx_init(struct pci_controller *); |
||||
|
||||
void pci_init_board(void) |
||||
{ |
||||
pci_mpc5xxx_init(&hose); |
||||
} |
||||
#endif |
||||
@ -0,0 +1,122 @@ |
||||
/* |
||||
* (C) Copyright 2005 |
||||
* Wolfgang Denk, DENX Software Engineering, wd@denx.de. |
||||
* |
||||
* See file CREDITS for list of people who contributed to this |
||||
* project. |
||||
* |
||||
* This program is free software; you can redistribute it and/or |
||||
* modify it under the terms of the GNU General Public License as |
||||
* published by the Free Software Foundation; either version 2 of |
||||
* the License, or (at your option) any later version. |
||||
* |
||||
* This program is distributed in the hope that it will be useful, |
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of |
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
||||
* GNU General Public License for more details. |
||||
* |
||||
* You should have received a copy of the GNU General Public License |
||||
* along with this program; if not, write to the Free Software |
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
||||
* MA 02111-1307 USA |
||||
*/ |
||||
|
||||
OUTPUT_ARCH(powerpc) |
||||
SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib); |
||||
/* Do we need any of these for elf? |
||||
__DYNAMIC = 0; */ |
||||
SECTIONS |
||||
{ |
||||
/* Read-only sections, merged into text segment: */ |
||||
. = + SIZEOF_HEADERS; |
||||
.interp : { *(.interp) } |
||||
.hash : { *(.hash) } |
||||
.dynsym : { *(.dynsym) } |
||||
.dynstr : { *(.dynstr) } |
||||
.rel.text : { *(.rel.text) } |
||||
.rela.text : { *(.rela.text) } |
||||
.rel.data : { *(.rel.data) } |
||||
.rela.data : { *(.rela.data) } |
||||
.rel.rodata : { *(.rel.rodata) } |
||||
.rela.rodata : { *(.rela.rodata) } |
||||
.rel.got : { *(.rel.got) } |
||||
.rela.got : { *(.rela.got) } |
||||
.rel.ctors : { *(.rel.ctors) } |
||||
.rela.ctors : { *(.rela.ctors) } |
||||
.rel.dtors : { *(.rel.dtors) } |
||||
.rela.dtors : { *(.rela.dtors) } |
||||
.rel.bss : { *(.rel.bss) } |
||||
.rela.bss : { *(.rela.bss) } |
||||
.rel.plt : { *(.rel.plt) } |
||||
.rela.plt : { *(.rela.plt) } |
||||
.init : { *(.init) } |
||||
.plt : { *(.plt) } |
||||
.text : |
||||
{ |
||||
cpu/mpc5xxx/start.o (.text) |
||||
*(.text) |
||||
*(.fixup) |
||||
*(.got1) |
||||
. = ALIGN(16); |
||||
*(.rodata) |
||||
*(.rodata1) |
||||
*(.rodata.str1.4) |
||||
} |
||||
.fini : { *(.fini) } =0 |
||||
.ctors : { *(.ctors) } |
||||
.dtors : { *(.dtors) } |
||||
|
||||
/* Read-write section, merged into data segment: */ |
||||
. = (. + 0x0FFF) & 0xFFFFF000; |
||||
_erotext = .; |
||||
PROVIDE (erotext = .); |
||||
.reloc : |
||||
{ |
||||
*(.got) |
||||
_GOT2_TABLE_ = .; |
||||
*(.got2) |
||||
_FIXUP_TABLE_ = .; |
||||
*(.fixup) |
||||
} |
||||
__got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >> 2; |
||||
__fixup_entries = (. - _FIXUP_TABLE_) >> 2; |
||||
|
||||
.data : |
||||
{ |
||||
*(.data) |
||||
*(.data1) |
||||
*(.sdata) |
||||
*(.sdata2) |
||||
*(.dynamic) |
||||
CONSTRUCTORS |
||||
} |
||||
_edata = .; |
||||
PROVIDE (edata = .); |
||||
|
||||
__u_boot_cmd_start = .; |
||||
.u_boot_cmd : { *(.u_boot_cmd) } |
||||
__u_boot_cmd_end = .; |
||||
|
||||
|
||||
__start___ex_table = .; |
||||
__ex_table : { *(__ex_table) } |
||||
__stop___ex_table = .; |
||||
|
||||
. = ALIGN(4096); |
||||
__init_begin = .; |
||||
.text.init : { *(.text.init) } |
||||
.data.init : { *(.data.init) } |
||||
. = ALIGN(4096); |
||||
__init_end = .; |
||||
|
||||
__bss_start = .; |
||||
.bss : |
||||
{ |
||||
*(.sbss) *(.scommon) |
||||
*(.dynbss) |
||||
*(.bss) |
||||
*(COMMON) |
||||
} |
||||
_end = . ; |
||||
PROVIDE (end = .); |
||||
} |
||||
@ -0,0 +1,265 @@ |
||||
/*
|
||||
* (C) Copyright 2005 |
||||
* Wolfgang Denk, DENX Software Engineering, wd@denx.de. |
||||
* |
||||
* See file CREDITS for list of people who contributed to this |
||||
* project. |
||||
* |
||||
* This program is free software; you can redistribute it and/or |
||||
* modify it under the terms of the GNU General Public License as |
||||
* published by the Free Software Foundation; either version 2 of |
||||
* the License, or (at your option) any later version. |
||||
* |
||||
* This program is distributed in the hope that it will be useful, |
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of |
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
||||
* GNU General Public License for more details. |
||||
* |
||||
* You should have received a copy of the GNU General Public License |
||||
* along with this program; if not, write to the Free Software |
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
||||
* MA 02111-1307 USA |
||||
*/ |
||||
|
||||
#ifndef __CONFIG_H |
||||
#define __CONFIG_H |
||||
|
||||
/*
|
||||
* High Level Configuration Options |
||||
* (easy to change) |
||||
*/ |
||||
#define CONFIG_MPC5xxx 1 /* This is an MPC5xxx CPU */ |
||||
#define CONFIG_MPC5200 |
||||
#define CONFIG_O2DNT 1 /* ... on O2DNT board */ |
||||
|
||||
#define CFG_MPC5XXX_CLKIN 33000000 /* ... running at 33.000000MHz */ |
||||
|
||||
#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ |
||||
#define BOOTFLAG_WARM 0x02 /* Software reboot */ |
||||
|
||||
#define CFG_CACHELINE_SIZE 32 /* For MPC5xxx CPUs */ |
||||
#if (CONFIG_COMMANDS & CFG_CMD_KGDB) |
||||
# define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ |
||||
#endif |
||||
|
||||
/*
|
||||
* Serial console configuration |
||||
*/ |
||||
#define CONFIG_PSC_CONSOLE 5 /* console is on PSC5 */ |
||||
#define CONFIG_BAUDRATE 115200 /* ... at 115200 bps */ |
||||
#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 } |
||||
|
||||
/*
|
||||
* PCI Mapping: |
||||
* 0x40000000 - 0x4fffffff - PCI Memory |
||||
* 0x50000000 - 0x50ffffff - PCI IO Space |
||||
*/ |
||||
#define CONFIG_PCI 1 |
||||
#define CONFIG_PCI_PNP 1 |
||||
#define CONFIG_PCI_SCAN_SHOW 1 |
||||
|
||||
#define CONFIG_PCI_MEM_BUS 0x40000000 |
||||
#define CONFIG_PCI_MEM_PHYS CONFIG_PCI_MEM_BUS |
||||
#define CONFIG_PCI_MEM_SIZE 0x10000000 |
||||
|
||||
#define CONFIG_PCI_IO_BUS 0x50000000 |
||||
#define CONFIG_PCI_IO_PHYS CONFIG_PCI_IO_BUS |
||||
#define CONFIG_PCI_IO_SIZE 0x01000000 |
||||
|
||||
#define CFG_XLB_PIPELINING 1 |
||||
|
||||
#define CONFIG_NET_MULTI 1 |
||||
#define CONFIG_EEPRO100 1 |
||||
#define CFG_RX_ETH_BUFFER 8 /* use 8 rx buffer on eepro100 */ |
||||
#define CONFIG_NS8382X 1 |
||||
|
||||
#define ADD_PCI_CMD CFG_CMD_PCI |
||||
|
||||
/* Partitions */ |
||||
#define CONFIG_MAC_PARTITION |
||||
#define CONFIG_DOS_PARTITION |
||||
#define CONFIG_ISO_PARTITION |
||||
|
||||
#define CONFIG_TIMESTAMP /* Print image info with timestamp */ |
||||
|
||||
/*
|
||||
* Supported commands |
||||
*/ |
||||
#define CONFIG_COMMANDS (CONFIG_CMD_DFL | \ |
||||
CFG_CMD_EEPROM | \
|
||||
CFG_CMD_FAT | \
|
||||
CFG_CMD_I2C | \
|
||||
CFG_CMD_NFS | \
|
||||
CFG_CMD_SNTP | \
|
||||
CFG_CMD_MII | \
|
||||
CFG_CMD_PING | \
|
||||
ADD_PCI_CMD ) |
||||
|
||||
/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ |
||||
#include <cmd_confdefs.h> |
||||
|
||||
#if (TEXT_BASE == 0xFF000000) /* Boot low with 16 MB Flash */ |
||||
# define CFG_LOWBOOT 1 |
||||
#else |
||||
# error "TEXT_BASE must be 0xFF000000" |
||||
#endif |
||||
|
||||
/*
|
||||
* Autobooting |
||||
*/ |
||||
#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ |
||||
|
||||
#define CONFIG_PREBOOT "echo;" \ |
||||
"echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \
|
||||
"echo" |
||||
|
||||
#undef CONFIG_BOOTARGS |
||||
|
||||
#define CONFIG_EXTRA_ENV_SETTINGS \ |
||||
"netdev=eth0\0" \
|
||||
"nfsargs=setenv bootargs root=/dev/nfs rw " \
|
||||
"nfsroot=$(serverip):$(rootpath)\0" \
|
||||
"ramargs=setenv bootargs root=/dev/ram rw\0" \
|
||||
"addip=setenv bootargs $(bootargs) " \
|
||||
"ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask)" \
|
||||
":$(hostname):$(netdev):off panic=1\0" \
|
||||
"flash_nfs=run nfsargs addip;" \
|
||||
"bootm $(kernel_addr)\0" \
|
||||
"flash_self=run ramargs addip;" \
|
||||
"bootm $(kernel_addr) $(ramdisk_addr)\0" \
|
||||
"net_nfs=tftp 200000 $(bootfile);run nfsargs addip;bootm\0" \
|
||||
"rootpath=/opt/eldk/ppc_82xx\0" \
|
||||
"bootfile=/tftpboot/MPC5200/uImage\0" \
|
||||
"" |
||||
|
||||
#define CONFIG_BOOTCOMMAND "run flash_self" |
||||
|
||||
#if defined(CONFIG_MPC5200) |
||||
/*
|
||||
* IPB Bus clocking configuration. |
||||
*/ |
||||
#undef CFG_IPBSPEED_133 /* define for 133MHz speed */ |
||||
#endif |
||||
/*
|
||||
* I2C configuration |
||||
*/ |
||||
#define CONFIG_HARD_I2C 1 /* I2C with hardware support */ |
||||
#define CFG_I2C_MODULE 1 /* Select I2C module #1 or #2 */ |
||||
|
||||
#define CFG_I2C_SPEED 100000 /* 100 kHz */ |
||||
#define CFG_I2C_SLAVE 0x7F |
||||
|
||||
/*
|
||||
* EEPROM configuration |
||||
*/ |
||||
#define CFG_I2C_EEPROM_ADDR 0x50 /* 1010000x */ |
||||
#define CFG_I2C_EEPROM_ADDR_LEN 1 |
||||
#define CFG_EEPROM_PAGE_WRITE_BITS 3 |
||||
#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 70 |
||||
|
||||
/*
|
||||
* Flash configuration |
||||
*/ |
||||
#define CFG_FLASH_BASE 0xFF000000 |
||||
#define CFG_FLASH_SIZE 0x01000000 |
||||
#define CFG_ENV_ADDR (CFG_FLASH_BASE + 0x00040000) |
||||
|
||||
#define CFG_MAX_FLASH_BANKS 1 /* max num of memory banks */ |
||||
#define CFG_MAX_FLASH_SECT 128 /* max num of sects on one chip */ |
||||
|
||||
#define CFG_FLASH_ERASE_TOUT 240000 /* Flash Erase Timeout (in ms) */ |
||||
#define CFG_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (in ms) */ |
||||
|
||||
#undef CONFIG_FLASH_16BIT /* Flash is 8-bit */ |
||||
|
||||
|
||||
/*
|
||||
* Environment settings |
||||
*/ |
||||
#define CFG_ENV_IS_IN_FLASH 1 |
||||
#define CFG_ENV_SIZE 0x20000 |
||||
#define CFG_ENV_SECT_SIZE 0x20000 |
||||
#define CONFIG_ENV_OVERWRITE 1 |
||||
|
||||
/*
|
||||
* Memory map |
||||
*/ |
||||
#define CFG_MBAR 0xF0000000 |
||||
#define CFG_SDRAM_BASE 0x00000000 |
||||
#define CFG_DEFAULT_MBAR 0x80000000 |
||||
|
||||
/* Use SRAM until RAM will be available */ |
||||
#define CFG_INIT_RAM_ADDR MPC5XXX_SRAM |
||||
#define CFG_INIT_RAM_END MPC5XXX_SRAM_SIZE /* End of used area in DPRAM */ |
||||
|
||||
|
||||
#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */ |
||||
#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) |
||||
#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET |
||||
|
||||
#define CFG_MONITOR_BASE TEXT_BASE |
||||
#define CFG_MONITOR_LEN (192 << 10) /* Reserve 192 kB for Monitor */ |
||||
#define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ |
||||
#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ |
||||
|
||||
/*
|
||||
* Ethernet configuration |
||||
*/ |
||||
#define CONFIG_MPC5xxx_FEC 1 |
||||
/*
|
||||
* Define CONFIG_FEC_10MBIT to force FEC at 10Mb |
||||
*/ |
||||
/* #define CONFIG_FEC_10MBIT 1 */ |
||||
#define CONFIG_PHY_ADDR 0x00 |
||||
|
||||
/*
|
||||
* GPIO configuration |
||||
*/ |
||||
//#define CFG_GPS_PORT_CONFIG 0x10002004
|
||||
#define CFG_GPS_PORT_CONFIG 0x00002004 //no CAN
|
||||
|
||||
/*
|
||||
* Miscellaneous configurable options |
||||
*/ |
||||
#define CFG_LONGHELP /* undef to save memory */ |
||||
#define CFG_PROMPT "=> " /* Monitor Command Prompt */ |
||||
|
||||
#if (CONFIG_COMMANDS & CFG_CMD_KGDB) |
||||
#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ |
||||
#else |
||||
#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ |
||||
#endif |
||||
#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ |
||||
#define CFG_MAXARGS 16 /* max number of command args */ |
||||
#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ |
||||
|
||||
#define CFG_MEMTEST_START 0x00100000 /* memtest works on */ |
||||
#define CFG_MEMTEST_END 0x00f00000 /* 1 ... 15 MB in DRAM */ |
||||
|
||||
#define CFG_LOAD_ADDR 0x100000 /* default load address */ |
||||
|
||||
#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */ |
||||
|
||||
/*
|
||||
* Various low-level settings |
||||
*/ |
||||
#if defined(CONFIG_MPC5200) |
||||
#define CFG_HID0_INIT HID0_ICE | HID0_ICFI |
||||
#define CFG_HID0_FINAL HID0_ICE |
||||
#else |
||||
#define CFG_HID0_INIT 0 |
||||
#define CFG_HID0_FINAL 0 |
||||
#endif |
||||
|
||||
#define CFG_BOOTCS_START CFG_FLASH_BASE |
||||
#define CFG_BOOTCS_SIZE CFG_FLASH_SIZE |
||||
#define CFG_BOOTCS_CFG 0x00047801 |
||||
#define CFG_CS0_START CFG_FLASH_BASE |
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#define CFG_CS0_SIZE CFG_FLASH_SIZE |
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|
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#define CFG_CS_BURST 0x00000000 |
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#define CFG_CS_DEADCYCLE 0x33333333 |
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|
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#define CFG_RESET_ADDRESS 0xff000000 |
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|
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#endif /* __CONFIG_H */ |
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Reference in new issue