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@ -400,7 +400,7 @@ static void set_bandwidth_ratio(const struct chan_info *chan, u32 channel, |
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if (n == 1) { |
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setbits_le32(&pctl->ppcfg, 1); |
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writel(RK_SETBITS(1 << (8 + channel)), &grf->soc_con0); |
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rk_setreg(&grf->soc_con0, 1 << (8 + channel)); |
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setbits_le32(&msch->ddrtiming, 1 << 31); |
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/* Data Byte disable*/ |
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clrbits_le32(&publ->datx8[2].dxgcr, 1); |
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@ -410,7 +410,7 @@ static void set_bandwidth_ratio(const struct chan_info *chan, u32 channel, |
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setbits_le32(&publ->datx8[3].dxdllcr, DXDLLCR_DLLDIS); |
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} else { |
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clrbits_le32(&pctl->ppcfg, 1); |
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writel(RK_CLRBITS(1 << (8 + channel)), &grf->soc_con0); |
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rk_clrreg(&grf->soc_con0, 1 << (8 + channel)); |
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clrbits_le32(&msch->ddrtiming, 1 << 31); |
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/* Data Byte enable*/ |
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setbits_le32(&publ->datx8[2].dxgcr, 1); |
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@ -571,8 +571,7 @@ static void dram_all_config(const struct dram_info *dram, |
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dram_cfg_rbc(&dram->chan[chan], chan, sdram_params); |
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} |
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writel(sys_reg, &dram->pmu->sys_reg[2]); |
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writel(RK_CLRSETBITS(0x1F, sdram_params->base.stride), |
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&dram->sgrf->soc_con2); |
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rk_clrsetreg(&dram->sgrf->soc_con2, 0x1f, sdram_params->base.stride); |
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} |
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static int sdram_init(const struct dram_info *dram, |
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